JPH01192073A - System for inspecting electronic device - Google Patents

Abstract

PURPOSE:To realize the labor saving and the acceleration of the inspection of an electronic device to be inspected and to improve the reliability of the inspection by executing the inspection of an FDC requiring much time and that of a RAM and a ROM, etc., in parallel. CONSTITUTION:When the electronic device 12 to be inspected incorporating an FD driving unit control circuit 115 and CPUs 101 and 111 is placed at an inspecting position, a controller 20 makes the CPU on one side in the device 12 execute the inspection of the control circuit 115 requiring much time by controlling each CPU, and also, in parallel with the inspection, makes the CPU on the other side execute the inspection of the RAMs 102 and 112, and the ROMs 103 and 113, etc., and inspection results are taken out by the controller 20. Therefore, it is possible to realize the complete automation and the acceleration of the inspection.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device for inspecting electronic circuits incorporated in electronic devices, and in particular to a device for inspecting a floppy disk drive unit control circuit, memory, etc. mounted on a printed wiring board. The present invention relates to an electronic device testing system suitable for testing other electronic circuits.

[Conventional technology]

An electronic device is a printed wiring board (hereinafter referred to as a board) that is made up of male parts mounted to form a desired electronic circuit, or a combination of these, and is, for example, a part of a personal computer or a word processor. There are circuit boards, personal computers, word processors, etc. that combine these boards. In such electronic devices, after a desired electronic circuit is constructed by mounting components on a board, the electronic circuit and components are first inspected to see if they operate normally. Adjustments are made by adjusting the movable parts of the parts.

In addition, electronic devices are energized at the final stage of the assembly process and are actually operated to perform a functional test to see if they are exhibiting the performance as designed.

Conventionally, electronic devices, particularly electronic circuits such as a floppy disk drive unit control circuit that controls a floppy disk drive unit mounted on a board and a memory, have been inspected as shown in FIG.

That is, the operator 10 attaches the board 12 to be tested, which is the electronic device to be tested, which has been transported to the testing process, to a current testing jig (not shown). Thereafter, the operator 10 moves the needle-shaped current-carrying connection member provided on the current-carrying test jig to electrically connect the board to be tested 12, the test program (test ROM) 14, and the floppy disk drive unit (FDD) 15. The operator 10 connects the board to be tested 12 to the CRT display 16 and prepares for testing.
When the preparation for the inspection in step 2 is completed, step lla in Fig. 6 is completed.
The floppy disk drive unit control circuit (FD)
Perform C) inspection. In this test, after loading a floppy disk (not shown) into the floppy disk drive unit 15, the advance switch 18 is pressed according to the step of the test, and the test image is displayed on the CRT display 16 to obtain a predetermined image. Make sure that the If a predetermined image is obtained, it is determined that the function of the drive unit control circuit is normal, and if a predetermined image is not obtained, it is determined that the function of the drive control circuit is not normal, that is, it is defective.

After completing the FDC function test, the operator performs the random access memory (R
AM), read-only memory (ROM), modem, etc. are sequentially tested to see if they are working properly.

After completing the test in this way, the operator moves the needle-shaped current-carrying connection member provided on the current-carrying test jig to electrically connect the board to be tested 12, the test program 14, and the floppy disk drive unit 15. Remove the board to be inspected 1
2 from the energization test jig (not shown).

[Problem to be solved by the invention]

However, the inspection according to the above-mentioned inspection method requires much work by the operator 10, such as operating the advance switch 18 and switching switches according to the inspection contents, and since various inspections are performed in order, It takes time and increases inspection costs. Moreover, when the operator
In order to determine the quality of the test, there is a risk that the quality of the test will be lowered due to variations among workers.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device testing system that can solve the above-mentioned problems, save labor in testing, and improve testing reliability.

[Means to solve the problem]

In order to achieve the above object, an electronic device inspection system according to the present invention includes a floppy disk drive unit that drives a floppy disk, a drive unit control circuit that controls the floppy disk drive unit, and a plurality of control circuits. a testing mechanism electrically connected to the electronic device to be tested and equipped with a predetermined testing program; controlling an inspection mechanism, giving an inspection command to the control circuits of the electronic device to be inspected, causing one of the control circuits to execute an inspection of the drive unit control circuit according to the predetermined inspection program; at least one control circuit in the electronic device to be tested according to the predetermined test program.

Execute other inspections such as mortar, and take the results of each of these inspections.
The controller is characterized in that it has a controller that takes out the data.

[Operation] In the present invention configured as described above, when an electronic device to be tested that includes a floppy disk drive unit control circuit and a plurality of control circuits is placed at a testing position, the controller controls the control circuit of the electronic device to be tested. Then, one of the control circuits executes a time-consuming test of the floppy disk drive unit control circuit, and in parallel with this test, another control circuit executes other tests such as a memory test. Since the test results can be retrieved by the controller, there is no need for workers to be involved in the testing process, which not only makes testing completely automated and quick, but also saves labor and improves reliability. Can be done.

〔Example〕

A preferred embodiment of the electronic device inspection system according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing an embodiment of an electronic device inspection system according to the present invention.

The substrate to be inspected 12 includes a main control section 100 and a sub-control section 110. The main control unit 100 is a main central processing unit (
Main CPU) 101, RAMIO2, ROM103,
Parallel input/output interface (parallel l10)
104 and an expansion bus slot 105, which are interconnected by a bus 106. The sub-control unit 110 also includes a sub-central processing unit (sub-CPU) 111, an RA
M112, ROM113, bar) Ltllo 11
4. Floppy disk drive unit control device (FDC)
) 115, which are interconnected by a bus 116. Then, the parallel l1 on the main control unit 100 side
0104 and the parallel I10114 of the sub-control unit 110 are connected by a parallel signal line 120, and the main control unit 1
The 00 side and the sub-control unit 110 side can mutually exchange data. ``An input/output board (10 board) 23 is connected to the expansion bus slot 105 via an external bus 21.

The I10 board 23 is connected to the I10 board 27 on the controller 2o side via a parallel signal line 25. Furthermore, a test program (test ROM) 14 built into a test mechanism, which will be described later, is connected to the external bus 21. On the other hand, the FDCI provided in the sub-control unit 110
I5 has a floppy disk drive unit (FDD) 1
5 is connected.

As will be described in detail later, the CPU of main control unit 100
101! The sub CPU 111 of the sub control unit 110 checks the tRAM 102, ROM 103, etc.
Execute the test in step 5.

The inspection mechanism 22 consists of a robot part 24 and a fixture middle part 26, as shown in FIG.

The robot section 24 has a plurality of robots 32 attached to a bracket 30 that is moved up and down by a press 28. The robot 32 has a driver 3 controlled by a controller 2o.
4 to move movable parts of movable parts such as switches built into the board 12 to be inspected.

The fixture section 26 contains the inspection program 14 and the I10 board 23, and is connected to the floppy disk drive unit 15 and the controller 20 via a connector 36. The fixture section 26 also includes guide pins 3 for positioning the substrate 12 to be inspected that has been transported to the inspection position.
8 and a contact pin 40 as a contact member are provided on the top surface.

The transport mechanism 42 that carries the substrate 12 to be inspected into and out of the inspection position is composed of rails 44, 46, 48, a horizontal movement mechanism 50, and a vertical movement mechanism 52. The rail 46, which serves as the inspection position, has a mechanism in which it descends when a rolling blade is applied, and rises to the illustrated position when the rolling blade is released.

The controller 20 includes a computer device 58 equipped with a memory 54 and a floppy disk device 56, a CRT display 60 connected to the computer device 58, a keyboard 62, a printer 64, an expansion bus 66, and a comparator connected to the expansion bus 66. (COMP) 68, CP
- IB70, I10 board 27, input/output (Ilo) interface 74, relay unit 76 connected to I10 board 27, control panel 78 connected to I10 interface 74, fast Fourier transformer (FFT) 80 connected to CP-IB70 , counter 82,
Digital storage oscilloscope 84, these FFT
80. A power supply 8 supplies power to the fixture unit 26 via a multiplexer unit (MPX unit) 86 that inputs test signals to the counter 82 , digital storage oscilloscope 84 and comparator 68 , and the connector 36
It consists of 8.

The MPX unit 86 receives a signal from the fixture section 26 via the connector 36, and the relay unit 76 provides a signal to the fixture section 26 via the connector 36. Also, I1
0 board 27 is also connected to the plug 36, and the fixture part 2
A control panel 7 that sends and receives signals to and from the I10 board 23 in B 6. A horizontal movement mechanism 50 for the press machine 28, driver 34, and transport mechanism 42 of the BCL corobot 24.
, drives and controls the vertical movement mechanism 52.

The general inspection process according to the embodiment configured as above is as follows:
It is as follows.

The horizontal movement mechanism 50 of the transport mechanism 42 is moved up and down by the vertical movement mechanism 52, and transfers the substrate 12 to be inspected carried onto the rail 44 from the direction of arrow A onto the rail 46 which is the inspection position. The rail 46 is connected to the board 12 to be inspected.
When the board is carried in, it descends by receiving the reduction blade, and the board to be inspected 12
contacts the contact pins 40, and the substrate to be inspected 12 and the fixture section 26 are electrically connected. When this electrical connection is made, test signals and various data are transmitted from the computer device 58 to the expansion bus 66, the I10 board 27, and the plug 36.
is applied to the fixture section 26 via the substrate to be inspected 1.
Various tests are performed on the FDC 115, RAM, ROM, etc. Further, the robot unit 24 is configured such that the bracket 30 is lowered by the operation of the press machine 28, and the robot 32
The board to be tested 1 is driven to check the operation of movable parts such as switches mounted on the board to be tested 12.
2 data signals and test results are sent to the fixture section 2.
6 to the MPX unit 86 and I10 board 27 of the controller 20 via the connector 36, and is sent to the computer device 58. When the operation check of the movable parts of the board to be inspected 12 is completed, the bracket 30 is moved to the press 112.
B, the rail 46 is raised and returned to the standby position shown in FIG. It is carried out via the rail 48 in the direction of arrow B.

FDC 115, RAM 102, RO of the board to be inspected 12
Tests such as M103 are performed as follows.

The board 12 to be inspected is carried onto the rail 46 which is the inspection position, and the rail 46 is lowered and the contact bin 40 is placed on the board 1 to be inspected.
2, the expansion bus slot 1 of the board to be tested 12
05 is connected to the inspection program 14 in the fixture section 26 and the I10 board 23 by an external bus 21, and the FDC 115 is connected to the floppy disk drive unit 15 via the fixture section 26. And, the I10 board 23 installed in the middle part 26 of the fixture is
■10 board 2 on the controller 20 side via the connector 36
7.

When preparations for testing the board to be inspected 12 are completed in this way, the main controller 100 and the sub-controller 11O
PUl0I and sub CPUI 11 are each ROM
The main control unit 100 according to the program in 103.113
After that, the sub CPU III of the sub control unit 110 reads the contents of the ROM 113, and as shown in step 160 in FIG. , requests to transfer the FDC inspection program for executing the FDCII5 inspection. The main CPU l01 is the sub control unit 1
When there is a request to transfer the FDC inspection program from the 10 side, the FD is transferred from the inspection program 14 in the fixture central 26.
The program for C inspection is read out and transferred to the sub-control unit 110 (step 140 in FIG.
Waits for an FDC inspection execution command from (step 141), and then sub CPU 1ll of sub control unit 110
When the FDC inspection program is transferred from the main control unit 100, it is received, written to the RAM 112, and waits for an inspection start command (steps 161 and 162).
.

On the other hand, when the controller 20 completes the preparation for testing the board 12 to be tested, it sends an FDC test execution command to the main CPU 101 via the I10 board 23.27 and the expansion bus slot 105 (step 130 in FIG. 3(A)). .

When the test execution command is sent from the main CPU 10I wide controller 20, the process advances to step 142, and a test start command is sent to the sub CPUI 11 of the sub control unit 110 (step 143).
When receiving a test start command from the main CPU 10I, reads the FDC test program written in the RAM 112, gives a command to the FDC 115 to operate the floppy disk drive unit 15, and performs operations such as writing to the floppy disk and reading from the floppy disk. A test is performed (step 163).

The main CPU 10I, which sent the inspection start command for the FDC 115 to the sub CPU 11, is waiting for the next command to be input from the controller 20 (step 1).
44), controller 20fJ < When the controller 20fJ sends a test execution command for the RAM, ROM, parallel I10, modem (not shown), etc. as in step 131, it receives these commands, analyzes the contents of the command, and executes the test program 14. Load the programs necessary for each test from
3. Execute inspection of parallel l10104, modem, etc. After the main CPU Ol completes all inspections of RAM, ROM, etc., it sends these inspection results to the controller 20 and sends them from the sub CPU 11 to the FDC 1.
Wait for 15 test results to be sent (step 14)
6.147).

When the sub CPU 11 finishes inspecting the FDC 115, it sends the inspection result to the main CPU I0I (step 164) and ends the flow. When the main CPU 10I receives the inspection result for the FDC 115 from the sub CPU 11, it sends it to the controller 20 (step 148), and the flow ends. Further, the controller 20 in step 132 performs main CPtJ1
01 receives the inspection results of the RAM, ROM, etc. inspected, and also transmits the inspection results of the FDC 115 inspected by the sub CPU III in step 133 to the main CPU.
A check is taken from 0I, and based on these results, it is determined whether the board to be inspected 12 is good or bad (step 134). Then, when the inspection result indicates that the substrate 12 to be inspected is normal in step 134, the controller 20 performs processing as OK, such as transporting the substrate 12 to be inspected to the next process. If it indicates an abnormality, the process proceeds to step 136, where the test board 12 is processed as NG, such as being transported to a rework process, and the flow ends.

In this way, the inspection system of the embodiment has the substrate to be inspected 12
The sub CPU 11 installed in the FDC1 takes several minutes.
15, the main CPU10I mounted on the board to be inspected 12 is running as RAM.

Since the inspection of the ROM and the like is performed in parallel with the inspection of the FDC 115, the inspection time for the substrate to be inspected 12 can be significantly shortened. Moreover, these inspections are performed on the substrate to be inspected 12.
The main CPU1011 sub CPUI 11 installed in the controller 20 executes the inspection based on the inspection command from the controller 20, sends the inspection results to the controller 20, and the controller 20 determines the quality of the inspected substrate 12, so the inspection of the inspected substrate 12 is performed. can be performed automatically, saving labor, speeding up testing, reducing costs, and improving reliability of testing.

In addition, in FIG. 4, the main C
The flow of commands and data transfer between P U 1-01 and sub CPU 11 is shown in Figure 4 (A) on the sending side and Figure 4 (B) on the receiving side. It shows the flow.

The transmitting side outputs a reception preparation request signal to the receiving side as in step 200, and waits for the receiving side to complete reception preparation (step 202).The receiving side receives the reception preparation request signal. After preparing for reception and sending a reception preparation completion signal to the transmitting side (steps 220 and 222), it waits for a data transmission signal to be input from the transmitting side (step 224).

When the transmitting side receives the reception preparation completion signal from the reception side, it resets the reception preparation request signal (step 204), sets commands and data to the output port, and outputs a data transmission signal to the reception side (steps 206 and 208). ), the receiving side proceeds from step 224 to step 226 after receiving the data transmission signal, resets the reception ready signal, and receives and receives data from the input port (step 228).
, sends a data reception signal to the transmitting side (step 2'3
0').

The transmitter that has output the data transmit signal is waiting for a data receive signal to be input from the receiver (step 210).
, when a data reception signal is input, a data transmission completion signal is output to the transmission side (step 212). Then, when the receiving side receives the data transmission completion signal from the sending side, it outputs a data reception completion signal to the sending side (step 234).
, end the flow. Furthermore, after outputting the data transmission completion signal, the transmission side receives the data reception completion signal and confirms that the reception side has received the data (step 214);
Finish the send flow.

In the above embodiments, the inspection of a board such as a personal computer has been described, but the electronic device to be tested may be a personal computer, a word processor, etc. In the case where is 3 or more, the test can be performed in the same way.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of control circuits in the electronic device under test execute the time-consuming test of the FDC and the test of the RAM, ROM, etc. in parallel based on the test command from the controller. However, since the controller takes out these test results, it is possible to save labor and speed up the test of the electronic device to be tested, and the reliability of the test is improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the overall configuration of an embodiment of an electronic device testing system according to the present invention, FIG. 2 is a block diagram of the same embodiment, and FIG. 3 is a flowchart showing a procedure for testing an electronic device to be tested. Figure 4 is a flowchart showing the procedure for receiving and passing commands and data between the board to be inspected and the controller;
FIGS. 5 and 6 are explanatory diagrams of a conventional method for testing an electronic device to be tested. 12 ...--Tested board (tested electronic device), 1
4--Testing program, 15--Floppy disk drive unit, 20--Controller, 22--Testing mechanism, 101--Main CPU (control circuit) , 111 --- Sub CPU (control circuit), 115 --- Floppy disk drive unit control circuit. Agent Patent Attorney Tomo Murakami - Figure 2

Claims (1)

[Claims] (1) An electronic device to be tested that includes a floppy disk drive unit that drives a floppy disk, a drive unit control circuit that controls the floppy disk drive unit, and a plurality of control circuits, and that is electrically connected to the floppy disk drive unit. When placed in the testing position, the test mechanism is electrically connected to the electronic device under test and is equipped with a predetermined test program; to cause any one of the control circuits to test the drive unit control circuit according to the predetermined test program, and cause at least one other control circuit to test the drive unit control circuit according to the predetermined test program. 1. A testing system for an electronic device, comprising: a controller that executes other tests such as a memory in the test electronic device and takes out the results of each of these tests.