JPH01191938A - Information processor - Google Patents

Abstract

PURPOSE:To perform the input/output interruption processing at a high speed by loading the using data in advance to a register for input/output interruption processing programs in a program non-executing state. CONSTITUTION:When a CPU 2 is not executing any program, this fact is designated to a program state display word PSW 21 and an idle state is set. Then it is checked whether an interruption is produced or not. If not, the data is loaded to a register for input/output interruption programs. When this data loading action is through, a load end flag is turned on to check again whether an interruption is produced or not. If so, it is checked whether the load end flag is turned on or not. If so, the contents of the PSW 21 are saved when an interruption is produced. Then the contents showing the PSW of the input/ output interruption are loaded to the PSW 21 and the execution is started for an input/output interruption program.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an information processing device.

(Prior art) In a conventional information processing device, after an interrupt occurs, the
Durham status words were being switched and data was being loaded into registers.

[Problem to be solved by the invention]

The above-described conventional information processing apparatus has a disadvantage in that it takes a long time to process the interrupt because data is loaded into the register after the interrupt occurs.

[Means for Solving the Problems] The information processing device of the present invention is such that when the main storage device generates any of the interrupts including an input/output interrupt, the central processing unit executes a program other than the generated interrupt processing. If it is, the program status display word indicating the execution status of the central processing unit at that time and the contents of the registers used by the program being executed are saved.
a first storage area for each interrupt process; and a second storage area for each interrupt process that stores a program status display word and the contents of a register used when executing the interrupt process; Information about the central processing unit, including registers used by the program to be executed by the processing unit, and information such as the address of the instruction being executed in the program, indicating whether or not the program is being executed. When an interrupt occurs during program execution, the program status display word at that time and the register contents of the program being executed are stored in the first storage area corresponding to the interrupt. Along with saving,
Similarly, the program status display word and the contents of the registers to be used are loaded from the corresponding second storage area to the program status display word and the register group, respectively, and the generated interrupt is executed, and any interrupt is executed in the program non-execution state. If no interrupt occurs, load the contents of the register from the second storage area corresponding to the input/output interrupt into the register group, wait, and then, when an interrupt occurs, determine whether the interrupt is an input/output interrupt or not. However, if the human output section is included, the contents of the program status display word at that time are displayed as the first input/output interrupt corresponding to the input/output interrupt.
, and also save the corresponding second storage area in the same way.
Loading the contents of the program status display word from the storage area of the program status display word into the program status display word and executing an input/output interrupt;
If the interrupt is other than an input/output interrupt, the contents of the program status display word at that time are saved in the first storage area corresponding to the interrupt, and similarly used as the program status display word from the corresponding second storage area. The contents of the registers are loaded into the program status display word and the register group, respectively, and the generated interrupt is executed.

[Effect]

When the central processing unit is not executing the program, the data is loaded into the register of the human output section program in advance, so there is no need to load data when an input/output interrupt occurs, and it is processed immediately. be able to.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a flowchart showing the operation of the central processing unit 2 of FIG. 1 when the program is not executed, and FIG. It is a diagram showing an example of a storage area of the main storage device 4 in the figure.

This information processing device includes a central processing subsystem 1 having a central processing unit 2 and a main storage device 4, and an input/output subsystem 3. The input/output subsystem 3 is the human output section of information. When any interrupt processing including an input/output interrupt occurs and the central processing unit 2 is executing a program other than the generated interrupt processing, the main storage device 4 stores the execution status of the central processing unit 2 at that time; In other words, the PSW save saves the contents of the program status display word 21 (hereinafter abbreviated as PSW), which indicates whether or not a program is being executed, and if it is running, indicates information such as the address of the instruction being executed in the program. An area 33, a register save area 34 where the contents of registers used in the program being executed are saved, and a PSW load area 31 which stores the contents indicating the PSW related to self-interrupt processing, and a PSW load area 31 used when executing interrupt processing. A register save area 32 storing the contents of registers to be processed is provided for each possible interrupt process. The central processing unit includes a group of registers (not shown) used in the program to be executed and a PSW 21 that loads the contents of the PSW load area 31, and when an interrupt occurs while the program is being executed, it responds to the generated interrupt. PSW in PSW save area 33
21 and the contents of the registers of the program being executed in the register save area 34, and similarly save the contents of the PSW from the corresponding PSW load area 31.
Load the contents indicating W to the PSW 21, and load the contents of the registers to be used from the register load area 32 to the register group, process the generated interrupts, and when the program is not running and no interrupts occur, , loads the contents of the register to be used from the register load area 32 corresponding to the input/output interrupt into the register group, waits, and then, when an interrupt occurs, determines whether or not the interrupt is an internal interrupt. , if it is an input/output interrupt, the contents of the PSW 21 at that time are saved in the PSW save area 33 corresponding to the in-output interrupt, and the corresponding PS is saved in the same way.
The contents indicating the PSW are loaded from the W load area 31 to the PSW 21 to process the input/output interrupt, and if the interrupt is other than the input/output interrupt, the contents of the PSW 21 at that time are saved in the PSW save area 33 corresponding to the interrupt that occurred. At the same time, similarly, the PS
The contents indicating W are loaded to the PSW 21, and the contents of the register from the register load area 32 are loaded to the register group, respectively, and the generated interrupt is processed.

Next, the operation of this embodiment will be explained with reference to FIG.

Normally, the central processing unit 2 reads a program from the main storage device 4 and executes it. At that time, when an interrupt occurs,
The contents of the PSW 21 at that time are saved in the PSW save area 33 corresponding to the interrupt, and the data of the registers used by the program being executed are saved in the register save area 34, and from the PSW load area 3I of the own interrupt. The contents indicating the PSW are loaded into the PSW 21, and the data of the register to be used is loaded from the self-interrupt register load area 32 to execute interrupt processing. When the processing is completed, the saved contents of the PSW and the register data are loaded again, so that the processing of the program being executed can be resumed.

Furthermore, if the central processing unit 2 is not executing a program, that fact is specified to the PSW 21, and the central processing unit 2 shifts to an idle state as shown in FIG. Subsequently, the load completion flag indicating whether loading of data to the register of the input/output interrupt program has been completed is turned off (step IO), and it is checked whether an interrupt has occurred (step I+).

If it has not occurred, check whether the load completion flag is off (step 12). Since it is off here, the data is subsequently loaded into the register of the internal internal program (step 13). When the data loading is completed, the load completion flag is turned on (step 14), and it is checked whether an interrupt has occurred again. When an interrupt occurs, it is checked whether the load completion flag is on (step 15), and if it is not on, a predetermined interrupt other than the input/output interrupt program is processed, and if it is on, the PSW 21 when the interrupt occurs is processed. Save the contents of (
Step 16). Thereafter, the contents indicating the PSW of the input/output interrupt are loaded into the PSW 21 (step 17), and the execution of the input/output interrupt program is started.

(Effects of the Invention) As explained above, the present invention provides
Since these are often input/output interrupts, by loading the data to be used into the registers of the input/output interrupt handling program in advance when the central processing unit is in a program non-execution state, internal interrupts actually occur. This has the effect of making it unnecessary to load data into the register at the moment the input/output interrupt processing is performed, thereby speeding up input/output interrupt processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a flowchart showing the operation of the central processing unit 2 shown in FIG. 1 when the program is not executed, and FIG. It is a diagram showing an example of a storage area of the main storage device 4 in the figure. l...Central processing subsystem, 2...
...Central processing unit, 3...Human output subsystem, 4...
...Main memory, ■O~I7...Step, 21... psw. 31...PSW load area, 32...
...Register load area, 33...P
SW save area, 34...Register save area.

Claims (1)

[Scope of Claims] In an information processing device, when any of the interrupts including an input/output interrupt occurs in the main memory, and the central processing unit is executing a program other than the interrupt processing that occurred, The program status display word indicating the execution status of the central processing unit and the contents of the registers used by the program being executed are saved.
a first storage area for each interrupt process; and a second storage area for each interrupt process that stores a program status display word and the contents of a register used when executing the interrupt process; Information about the central processing unit, including registers used by the program to be executed by the processing unit, and information such as the address of the instruction being executed in the program, indicating whether or not the program is being executed. When an interrupt occurs during program execution, the program status display word at that time and the register contents of the program being executed are stored in the first storage area corresponding to the interrupt. Along with saving,
Similarly, the program status display word and the contents of the registers to be used are loaded from the corresponding second storage area to the program status display word and the register group, respectively, and the generated interrupt is executed, and any interrupt is executed in the program non-execution state. If no interrupt occurs, load the contents of the register from the second storage area corresponding to the input/output interrupt into the register group, wait, and then, when an interrupt occurs, determine whether the interrupt is an input/output interrupt or not. If it is an input/output interrupt, the content of the program status display word at that time is displayed as the first word corresponding to the input/output interrupt.
, and also save the corresponding second storage area in the same way.
Loading the contents of the program status display word from the storage area of the program status display word into the program status display word and executing an input/output interrupt;
If the interrupt is other than an input/output interrupt, the contents of the program status display word at that time are saved in the first storage area corresponding to the interrupt, and similarly used as the program status display word from the corresponding second storage area. An information processing apparatus characterized in that the contents of the registers are loaded into the program status display word and the register group, respectively, and the generated interrupt is executed.