JPH01191395A - Output circuit - Google Patents

Abstract

PURPOSE:To speed up an output circuit without increasing a consuming current by disposing a data inverting means for inverting an outputted data signal in the prestep of a final output step and temporarily supplying reverse data obtained by inverting the previous data immediately before an output signal is changed to the output step. CONSTITUTION:Based on the output data signals DT, -DT supplied from an internal circuit, AND gates G1, G2 forming the driving signal of MOSFET Q1, Q2 and exclusive OR logical gates G3, G4 are disposed on the prestep of the output step to temporarily supply the reverse data obtained by inverting the previous data to the output step immediately before the output signals DT, -DT are changed. Namely, according to the reverse data supplied to the output step, output transistors Q1, Q2 are reversely operated to a preceding time to preset an output terminal to Vcc/2. Thereby, an equalizing MOSFET is not required nor passes a through current to speed up the output circuit without increasing the consuming current.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit technology and a technology that is particularly effective when applied to speeding up output circuits, such as a semiconductor memory formed into an MO8 integrated circuit. This invention relates to techniques that are effective for use in output circuits of devices.

[Prior Art] Semiconductor storage devices are becoming faster and larger in capacity, but static RAM integrated with MO3
I Nis Nis C C 87, Digest
Of Technical Papers F.A.M.19
．． 7 pages 262-263 (ISSCC'87
DZGESTOF TECHNICAL PAPE
As discussed in R3FAM 19.7 Pp262-263), the delay time in the output circuit section accounts for a very large proportion of the access time. Therefore, as a method for increasing the speed of the output circuit section, a method has been proposed in which, for example, the output terminal is equalized and preset to the 1/2 Vcc level.

That is, as shown in FIG. 6, the power supply voltage Vcc-Vs
Equalizing MOSFETs Q, , Q are connected in parallel with output transistors Q, , Q2 connected in series between s. and a data signal DT.

Immediately before the change in DT, the output transistor Q2 is turned off by the output control signal φDOC, and the MOSFET
Q, , Q are simultaneously turned on by the equalize signal φE, the output signal Vout is once preset to the Vcc/2 level, and then the next read data signals DT, D are turned on.
It changes to low level or high level depending on the situation. By this, MO8F for equalization
ET Q.

If there is no G4, DT as shown in Figure 7 (D).

(2) After the signal changes, the output signal begins to change in response to this change, but the delay time until the Dout signal cross point is accelerated due to the effect of equalization, as shown in FIG. 2(C).

[Problems to be Solved by the Invention] However, in the above-described equalization method, MO3FETs Q, Q, are simultaneously turned on during the equalization operation, and a through current flows. Therefore, if you try to reduce the through current, you will not be able to sufficiently equalize the output terminals, and you will not be able to achieve high speed.
MO5FET for equalization to achieve sufficient speedup
Q,,Q.

Increasing the element size increases the through current, which has the contradictory drawback of increasing current consumption.

An object of the present invention is to provide a semiconductor integrated circuit technology that can increase the speed of an output circuit without increasing current consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, data inversion means for inverting the output data signal is provided at the stage before the final output stage, and immediately before the output signal is changed, reverse data obtained by inverting the previous data is temporarily supplied to the output stage. It is meant to be.

[Function] According to the above-described means, the output transistor is operated in the opposite direction by the reverse data supplied to the output stage, and the output terminal is preset to V c c / 2, so there is no need for an equalizing MOSFET. As a result, no through current flows, and the above objective of increasing the speed of the output circuit can be achieved without increasing current consumption.

[Embodiment] Fig. 1 shows an embodiment of the output circuit according to the present invention. The final output stage of the output circuit of this embodiment is connected to the power supply voltage terminal v.
Two N-channel MO3FETs between cc and vSS
Q□, G2 are connected in series, resulting in two MOS F
A connection node n8 of E T Qz -Qz is connected to the output terminal OUT. In large-capacity semiconductor storage devices such as static RAM, the circuit is sometimes configured with CMO8 circuits to reduce power consumption.
Even in the case of an i-type circuit configured with 8 CMO circuits, the buffer is configured by connecting two N-channel MO5FETs in series in order to prevent latch-up regarding the output buffer through which a relatively large current flows.

and an output data signal DT supplied from the internal circuit,
Based on DT, the above MO8FET Q engineering.

An AND gate G1.G2 forms a drive signal for G2. G2, and an exclusive OR logic gate G3. G4 is provided before the output stage.

In the output circuit of this embodiment, when the read data signal DT is at a high level (the clove is at a low level) in an output enable state where the output control signal φDoc is set to a high level, the output circuit is output on the condition that the control signal φE is at a low level. The transistor is turned on, G2 is turned off, and the output signal V o
ut becomes high level. On the other hand, when the read data signal DT is at a low level in the output enable state, the output signal V out is at a low level. In such an output state, when the equalize signal φE is changed to high level, the exclusive OR logic gate G3. G4
Since a reverse data signal is supplied to the gate terminal of the transistor Q2, the transistors Q1 and G2 operate in the opposite manner, that is, if they are off, they shift to the on state, and if they are on, they shift to the off state.

Therefore, for example, by appropriately delaying the detection signal φATD output from the address change detection circuit that detects a change in the address signal Add, the equalize signal φE can be changed to a high level just before the read data signals DT and D lower change. Then, the gate voltage Va of transistors Q, ,Q,
, Vb can be set to opposite levels. As a result, the output voltage V out begins to transition toward the opposite level. Then, by appropriately setting the pulse width of the equalize signal φE according to the size of the transistors Q, , Q, and the magnitude of the load, the output voltage V ou It is possible to set t to a level of Vcc/2, which is between the high level and the low level.

In other words, the equalize signal φE returns to low level at the timing when the output voltage Vout is preset to V c c /2, and then the next read data signals DT, DT
, the output voltage Vout becomes the data signal DT as shown in FIG. 2(H).

■Transition occurs depending on the lower level, and the high level or low level is quickly determined.

As a result, exclusive OR gate G,.

Compared to the case where G and k are not provided, data reading speed is increased and almost no through current flows.

Note that in the output circuit of FIG. 1, the output control signal φD
When oc is set to a low level, transistors Q□ and G2 are both turned off regardless of whether the data signals DT or D are low, and the output terminal OUT becomes a high impedance state. That is, it operates as a tri-state buffer.

FIG. 3 shows a second embodiment of the output circuit according to the invention.

This embodiment uses transfer gates G, , G, in place of the exclusive OR gates G, , G4 in the embodiment of FIG. is configured to supply.

That is, an inverter INV1 is provided immediately (or immediately before) the transfer gate G6, and the gate Gs transmits the equalize signal φE, which is a control signal for the gate G6, to the inverter INV.

The on/off control is performed in a complementary manner to Gs by the inverted signal.

Therefore, the read data signal DT is equalized by the equalize signal φE
is at low level, it passes through gate G5 to inverter I.
After being inverted at NV, it is supplied to the output stage. As a result, the output transistor Q1: output control signal φI)O
It is turned on (output transistor Q2 is off) on the condition that C is at a low level, and the output voltage Vout becomes the same level as the read data signal DT.

On the other hand, when the equalize signal φE becomes high level, the read data signal DT is supplied to the output stage through G instead of the gate G, and the output voltage V.

ut is changed to a level opposite to that of the read data signal DT. Therefore, as in the first embodiment, the equalize signal φ
By appropriately setting the timing and pulse width of ε, the opposite data is supplied to the output stage immediately before the read data signal DT changes, causing the output voltage V out to transition in the opposite direction, resulting in a Vc/2 level. After being preset, it can be quickly changed according to the next read data signal (see FIG. 4).

In addition, in FIG. 3, the NOR gate G7. to which the output control signal φL)QC is applied. G@ is a gate provided so that the output stage can be brought into a high impedance state, and is the AND gate G and G in the embodiment shown in FIG.
This corresponds to 2.

In the above embodiment, the equalize signal φE is generated by delaying the detection signal of the address change detection circuit, but the equalize signal φE may be generated by detecting a change in read data.

FIG. 5 shows a configuration example of a dynamic RAM to which the output circuit of the above embodiment is applied.

In the same figure, M-ARY has a plurality of memory cells MC,
Memory array arranged in matrix, ADB is address buffer, X-DEC is memory cell array M-A
X decoder that selects one word line W in RY, Y-
The DEC selects a pair of data lines DL and DL in the memory array and selects a signal to control on/off the column switch Qy for connecting the sense amplifier SA connected to it to the common input/output signal line i/o. This is a Y decoder to be formed.

The potential difference of the selected data line is amplified by the sense amplifier SA to produce a read data signal DT.

■It is supplied to the output buffer DOB as 〒. In this embodiment, the address change detection circuit ATD
is provided, and the detection signal φATD formed here is delayed by a delay circuit DLY to form an equalize signal φE, which is supplied to the output circuit DOB.

Further, an input buffer sofa DIB is connected to the input terminal IN, and the complementary write data signals Din, Din formed by the input buffer DIH are sent to the common input/output signal via the write control gates Ge□, Ge2. Line i/
o and is placed on the data line DL.

The data is written into the currently selected memory cell via the DL.

Furthermore, the write control gate G is provided in the memory chip based on the detection signal φATD outputted from the address change detection circuit ATD, the address strobe signals RAS and CAS supplied from the outside, the write control signal WE, etc.
w1. An internal control signal forming circuit TMG is provided for forming a control signal we of Gw2, an output control signal φDoc supplied to the output buffer, a control signal φsa providing the operation timing of the sense amplifier SA, and the like.

Output buffer DOB and input buffer DIB as above
The number of parallel input/output data bit lines corresponds to the number of parallel input/output data bit lines. In that case, the output terminal OUT and the input terminal IN may share one terminal.

As explained above, in the above embodiment, a data inverting means for inverting the output data signal is provided at the stage before the final output stage, and immediately before the output signal is changed, the inverse data obtained by inverting the previous data is temporarily transferred. I decided to supply it to the output stage, so
The reverse data supplied to the output stage causes the output transistor to operate in the opposite direction, and the output terminal becomes V c c /
Since it is preset to 2, the MOSFE for equalization
Since T is no longer necessary and no through current flows, there is an effect that the speed of the output circuit can be increased without increasing current consumption.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the logic gates 02 to G for forming the drive signal for the final output stage in the above embodiment are just examples, and any other logic gates may be used.

The above explanation will mainly focus on the static RAM, which is the field of application that was the background of the invention made by the present inventor.
However, the present invention is not limited thereto, and can be applied to general semiconductor memories such as dynamic RAM, pseudo-static RAM, ROM, and EPROM, and general MO8 logic integrated circuits other than memories. Can be done.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, the output transistor is operated in the opposite direction by the reverse data supplied to the output stage, and the output terminal becomes V c
Since it is preset to c/2, no equalizing MOSFET is required and no through current flows.
Do not increase current consumption.

This makes it possible to increase the speed of the output circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the output circuit according to the present invention, FIG. 2 is a waveform diagram showing signal waveforms of each part thereof, and FIG. 3 is a second embodiment of the output circuit according to the present invention. FIG. 4 is a waveform diagram showing the signal waveforms of each part of the circuit; FIG. 5 is a block diagram showing a configuration example of a static RAM to which the output circuit according to the present invention is applied; FIG. 6 is a conventional static RAM diagram. R
A circuit diagram showing an example of an output circuit in AM, and FIG. 7 is a waveform diagram showing signal waveforms of each part thereof. Q,,Q2...Output MO3FET, M-ARY・
...Memory array, SA...Sense amplifier, AT
D: Address change detection circuit, DOB: Output buffer, DIR: Input buffer. Figure 1 Figure 2 (H) Audience / - Figure 3 Figure 4 CD) Vtut --- Figure 5

Claims (1)

[Claims] 1. A data inverting means for inverting the output data signal to form reverse data is provided at the stage before the final output stage, and immediately before outputting the regular data, the reverse of the data of the previous cycle is provided. An output circuit characterized in that data is temporarily supplied to a final output stage to temporarily cause an output voltage to transition between a high level and a low level. 2. The final output stage includes a pair of MOS connected in series between the first power supply voltage terminal and the second power supply voltage terminal of the circuit.
2. The output circuit according to claim 1, wherein the output circuit is constituted by a FET. 3. A logic gate circuit is provided at a stage preceding the final output stage to form a signal that causes the final output stage to enter an output high impedance state in response to an output control signal. Output circuit described in item 2.