JPH01189088A - Editing method for digital signal - Google Patents

Abstract

PURPOSE:To facilitate the discrimination of the editing point of a digital signal without increasing the recording track of a recording medium and a constitution by setting an editing flag to indicate an editing point with the use of a flag bit in one block. CONSTITUTION:To express addresses 0-249 of the 250 blocks to be a repeating cycle, four bits B0-B3 are used over the two blocks, the lowest-order bit A0 of the block address is allotted to the lowest order-bit B0, and the two block portions of B1-B3 indicate six bits A1-A6 of the block addresses. The 16 blocks as one cycle can express the 16 types of flags. Flag bits F of the respective second and fourth blocks out of the 16 blocks are made into the edition completing point flag and the edition starting point flag, the first F is made into the emphasis flag, the Fs of the block addresses 1, 17... are made into the edition completing point flags, the Fs of the 3 and 19 blocks are made into the edition starting point flags, and the Fs of the 0 and 16 blocks are made into the emphasis flags.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for editing a digital signal, and more particularly to a method for editing a digital signal in which each block of data is assigned an address and transmitted.

[Summary of the invention]

The present invention is an editing method for editing a digital signal transmitted with a block address attached to each block consisting of a plurality of words of digital data. By using the flag bit in the address block as an edit flag and setting the edit flag corresponding to the edit point of the digital signal, the edit point can be easily identified.
This reduces the rate of data rejection.

[Conventional technology]

When recording, reproducing, or transmitting a digital signal such as an audio PCM signal, it is necessary to predetermine a formant including a sampling frequency, the number of bits of one sample, and the like.

For example, the present applicant has previously proposed the so-called DASH method as a fixed head type audio PCM signal recording method for professional use in Japanese Patent Application Laid-Open No. 57-36410 and Japanese Patent Application Laid-Open No. 59-104714. In this audio PCM signal recording method, one sample is 16 bits and 32kllz.

The format is compatible with sampling frequencies of 44.1 kHz and 48 kHz, and the recording pattern on the tape consists of multiple (8 to 48) digital audio tracks and 2 analog audio tracks. A time code track and a control trunk are formed along the tape running direction. Furthermore, the audio data is divided into blocks of a predetermined number of samples (for example, 12 samples), and each block is assigned a block address and recorded on the digital audio trunk together with a block synchronization signal, etc. There is.

Incidentally, in a digital VTR (video tape recorder) for recording and reproducing digital video signals on a magnetic tape, audio signals are also digitally recorded. For example, the applicant of the present invention previously disclosed a VTR for digitally recording so-called high-definition television signals in Japanese Unexamined Patent Publication No. 199179/1983. This prior art shows examples of three types of audio signal recording modes. ), digital recording of audio signals using a fixed head using the so-called DASH format has been considered.

[Problem to be solved by the invention]

Here, when the above-mentioned fixed head digital audio signal recording method is applied to audio recording of a VTR,
If you edit the above digital audio signal while adjusting the head tracking for the video track, the above data blocks may not be connected consecutively at the editing point, and the internal blocks that are counting on the flywheel 2. - The value from the address counter and the reproduced block address may not match. This is usually determined to be a missed CRCC (error detection code), and the data in that block is discarded. However, if they do not match twice in a row, it is determined that there is a block shift, the internal block address counter is corrected, and data fetching is restarted. In other words, the causes of the discrepancy between the reproduced block address value and the value from the internal counter mentioned above are: ■ When a wrong block address is reproduced due to a missed CRCC, and ■ When blocks are consecutive at an edit point. This may be due to poor quality, but in order to discern this, it is necessary to wait to check whether the above-mentioned discrepancy has occurred twice in a row.

By the way, in order to clearly distinguish the above-mentioned editing points, it is possible to record an editing point identification signal on a recording medium, for example, according to Japanese Patent Publication No. 62-
43272, Japanese Patent Application Laid-open No. 58-224483, etc., but it requires an extra track such as an editing control track, or the signal frequency of the servo track for tape running control is changed to the editing point. This may require additional configuration, such as different settings.

The present invention has been made in view of the above-mentioned circumstances, and provides a digital signal editing method that allows easy identification of editing points of a digital signal without increasing the number of recording tracks or the configuration of a recording medium. For the purpose of providing.

[Means to solve the problem]

In order to solve the above-mentioned problems, the digital signal editing method according to the present invention creates a digital signal in which a plurality of digital data or words are divided into blocks, and a block address is sequentially assigned to each block. In a digital signal editing method for editing, at least one predetermined pin in one block is set as a flag bit, and by defining the flag bit according to the block address, a specific block address can be edited. The present invention is characterized in that the flag bit in the block is used as an edit flag, and the edit flag is set corresponding to the edit point of the digital signal.

[For production]

Since the flag bit in one block is used to set an edit flag to indicate the edit point, there are cases where a wrong block address is played due to a missed CRCC, etc., and the block continuity at the edit point is poor. Discrimination between cases can be made instantaneously, and data that was conventionally rejected during this discrimination can now be taken in.

〔Example〕

Hereinafter, preferred embodiments of the digital signal editing method according to the present invention will be described with reference to the drawings.

Figure 1 shows an example of a synchronization signal word in a recording format for recording and reproducing audio PCM signals with a fixed head, and is used in a VTR (video tape recorder) for digitally recording and reproducing so-called high-definition television signals. 2 shows a synchronization signal word in a recording format applied to audio PCM signal recording and reproduction in .

In this recording format, a digital audio signal is divided into blocks of a predetermined number of words, and each block is subjected to error correction encoding processing as a delay unit of interleaving to form one block (recording block) of the recording format. The synchronization signal word in FIG. 1 is placed at the beginning of this recording block.

The synchronization signal word shown in FIG. 1 has a length equivalent to 16 bits, which is the same as the length of one word of the following data part. In the above 11-bit synchronization pattern where the bits are a block address (4 bits) and a flag (1 bit), when the bit period is T, the bits are 1.5T, 6. OT, 10
．． A transition (transition, inversion) occurs at each position of 5T. In this case, the & continuation data word, parity word, etc. are modulated, for example, by a modulation method called HDM-1, and in this modulation method, the above transition interval is the shortest. 1.5T
to a maximum of 4.5T, and 4.5T of this longest transition interval.
Although 5T is designed not to appear consecutively,
In the above synchronization pattern, transition intervals of 4.5T appear continuously.

Therefore, the synchronization pattern is a so-called out-on-rule pattern that deviates from the above-mentioned predetermined modulation method, thereby distinguishing the synchronization signal word from the data word.

4 bits that are the above block address (B in transmission order)
i, Bz, B+, Be), an even address block and an odd address block form one significant address. This means that an 8-bit block address is required in order to be able to identify 250 blocks with a repetition period of multiple blocks in the data format of FIG. 3, which will be described later. This takes into consideration that the address area in a word is 4 bits, and the 8 bits of the required block address are sequentially arranged from the LSB to AO, A, ...+A? Then, in an even address block, Ao(=
0), A++Az, and Aa, and in odd address blocks, An is assigned to each bit of B0 to B.
(= 1), An+'As+Ai is assigned.

The last 1 bit is used as a flag F to indicate on/off of emphasis, editing start point, editing end point, etc.

FIG. 2 shows a concrete example of the block address part and flag bit F of the above (pips) Be to B. In FIG. 2, the above 4 bits 80 to B3 are used across two blocks to represent block addresses 0 to 249 of 250 blocks, which are the repetition period as described later. Since the lowest pinpoint 80 of the block address is always assigned to the lower bit B0, the remaining 3 bits B1-B, two blocks, represent 6 bits A1-A of the block address. In this case, the repetition period is 250 blocks (
Since the address is 0 to 249), the topmost pi)A
? Even if omitted, it can be easily restored during playback.

Next, regarding the flag Pino) F, for example, 16 blocks are set as the IFI period so that up to 16 types of flags can be displayed, and the flags of the second and fourth blocks of these 16 blocks are・Pi) F is used as the ta end point flag and editing start point flag, respectively, and the first professional and ivy flag bit F is used as the emphasis flag. In other words, block
Address 1, 17. ... Set the flag bit F of the block to the final point flag, and set the block address 3, 1.
The flag bit F of the block at 9° . . . is used as the editing start point flag, and the block addresses 0, 16 . ...
The flag bit F of the block is set as an emphasis flag.

Next, FIG. 3 shows a data format for recording the above-mentioned high-definition television signal in a fixed head type audio PCM signal in a digital VTR.

In this Fig. 3, 3 of the above-mentioned high-definition television signals are shown.
Fifty large blocks of digital audio data are allocated to a field period (three vertical periods), and 48 samples each having a word length of 20 bits are allocated within one large block. That is, there are 3 fields, 2400 samples, and 800 samples per field.The field frequency of a high-definition television signal is 60Hz, so the sampling frequency of an audio signal is 48kHz.The above-mentioned 1 large block is divided into 5 blocks (or sub-blocks). ), and each (sub)block is composed of 12 symbols of data of 16 bits per symbol. Here, 5 blocks in the large block are sequentially divided into blocks O to 4.
When the data of the above 48 samples are sequentially Do to D47, the first four blocks 0 to 3 (12X4
= 48 symbols) is the above sample data Do-04.
The upper 16 bits of data of each of the sample data DO to D47 are sequentially arranged in the last block 4, and the lower 4 bits of each of the sample data DO to D47 are sequentially arranged. In the 12 symbols of this last block 4, four lower 4 bits of sample data are sequentially arranged from SR (13 lower bits) to MSB (i upper pin date) of each symbol. , 4×12=48 samples of lower 4 bits are allocated.

In this way, the sample data with a word length of 20 bits is divided into the upper 16 bits and the lower 4 bits, and the upper 16 bits of the 48 samples are assigned to 4 blocks of 48 symbols in the large block of 60 symbols, and the remaining l Each lower 4 of the same 48 samples in 12 symbols of the block
Bits are assigned and arranged. Each symbol of the data format having such a structure is subjected to error correction encoding using one block as a delay unit of interleaving processing.

To explain the error correction encoding process in this case, 12 symbols for one block in FIG.
1) ~WQE, these 12 symbols are first divided into odd-numbered words W+lLW+3+, . . . .

Vllll and the even-numbered word W (21, W f4
1, . . . , WU, and generate and add first parity words P and P2 to each series. Next, each data of the odd and even data series is subjected to interleaving processing with a predetermined delay, and then second parity words Ql and Q2 are generated and added, respectively. Further, in addition to applying a predetermined delay to each data, delay interleaving processing is also performed between the odd numbered sequence and the even numbered sequence to obtain a data sequence subjected to error correction encoding processing. The output data subjected to the error correction encoding process has P and Q parity added to both the odd and even data series, resulting in 8 symbols each, that is, 1) 16 symbols per lock.

Next, when actually recording the output data (16 symbols) corresponding to one block after being subjected to this error correction encoding process, a recording block as shown in FIG. 4 is formed. That is, a synchronization signal word equivalent to 16 bits as shown in FIG. The above P and Q parities are placed at each position of the symbol, and an error check code CRCC is placed at the end. The order of the 16 symbols of the data and parity part between this synchronization signal word and the error check code CRCC is W(12-7D ) W (7-6D x12) W (4-5D X12-5Xi2) W (3-5D x12) Q (2-4D x12-5 x12) Q (1-4D (1-3DX12) W (10-2D X12-5X12) W (9-2D x12) W (6-Dx12-75x12) W (5-D . In these formulas, D = 17 blocks = 17 x 12 symbols b = 9 D =
It is 9 x 17 x 12 symbols.

Next, regarding the state near the editing point when editing is performed,
The relationship with the edit point flag will be explained with reference to FIGS. 5 to 7.

First, FIG. 5 shows a case where the inserted recorded portion during editing is ideally connected to the recorded content on the tape without any positional shift of the above (sub) blocks, and A indicates the field reference signal (at least of the video signal). 3 fields), B is the digital audio signal played from the tape, C is the part to be inserted and recorded for the above editing, D is the digital audio signal played from the edited tape, E is the so-called Each block address from the flywheel counter is shown, and for the above B-D, each block of the digital audio signal is assigned to the above block address.
Displayed by address. In the case of FIG. 5, the continuity of the block address of the inserted portion of C is maintained, and editing is performed without any block position shift.

However, as described above, when so-called video tracking is performed, the digital audio signal is reproduced in analog fashion, for example, by dividing it into several (sub) blocks with respect to the video field reference signal. An example of this case is shown in FIG. A to E in FIG. 6 correspond to A to E in FIG. 5, respectively.

In FIG. 6, due to the video tracking adjustment, the digital audio signal is reproduced with a delay of 2.4 blocks with respect to the field reference signal in FIG. 6A (FIG. 6B). On the other hand, on the recording side, recording is performed in block-by-block timing with respect to the field reference signal, so even if a block of the playback signal is read out and the block address matches, it will be inserted by editing. The section (FIG. 6C) can only be delayed by two blocks compared to the case of FIG. 5 above. Therefore, each block of the audio signal after processing j1 becomes as shown in Figure 6, and there are 0.6 blocks and 0.4 blocks before and after the editing area inserted into the original signal, respectively.
An odd half of the block will be generated. However, the so-called flywheel counter performs a count-up operation for odd parts of 0.5 blocks or more, so
The address value of the edit start block in FIG. 6 and the output address value from the flywheel counter in FIG. 6E match. Also, the next half of the editing end block is 0.
Since it is shorter than 5 blocks, the flywheel counter does not count up and the plot and address match.

However, due to so-called wow flags and problems with mechanical precision, the lines do not connect as shown in Figure 6 above, and for example, as shown in Figure 7, the half-edge part at the editing start point becomes shorter than 0.5 block. In this case, the address value (3) of the editing start block and the output address value (2) from the flywheel counter in FIG. It takes at least two blocks to determine the result, and the data during this time will be discarded.

Therefore, in the embodiment of the present invention, the edit start block (address value 3) and the edit end block (address value 1) are
), the above judgment can be made quickly and the amount of rejected data is reduced.

Here, the symbol * attached to the left shoulder of the block address value in FIGS. 5 to 7 indicates that an edit flag is set, and the block at address 3 has an edit start point flag. In addition, an edit end point flag is set for each block at address 1. At the time of playback, by looking at these edit flags, it is possible to easily determine whether or not a part has been edited, and the number of errors at edit points can be reduced. For example, when block addresses are recorded in two blocks as in the above embodiment, two blocks are required just to obtain the block address. It takes 4 blocks to perform the comparison twice, and all data during this time is discarded.However, if it is an edit point, the data is immediately returned even if the playback block address does not match the value from the flywheel counter. Since the operation can be shifted to correcting the count value of the wheel counter, the amount of rejected data is reduced by more than half.

By the way, FIG. 8 shows the recording format or track recording pattern on the magnetic tape (videotape) MT of the high-quality digital VTR, and the digital audio signal is recorded along the tape running direction (direction of arrow A). The information is recorded on eight parallel tracks T, , #T, , which are provided parallel to each other. Furthermore, high-definition television video signals are recorded on the tape MT by a rotating head so as to form a plurality of diagonal video tracks Tv parallel to each other. In this case, for example, two sets of integrated four magnetic heads are mounted on a rotating drum at an angle of 180 degrees, and the magnetic tape is wound around the drum at an angle of approximately 330 degrees. By being guided by
Eight video trunk TVs are recorded and formed substantially simultaneously by the set of heads. Rotating drum is 7200 rpm
(120%), 16 video tracks Tv are recorded and formed by two rotations in one field period. The direction of arrow B in the figure is W1%
The running direction of the rotating video head is shown for a 1% Chi T. Further, on the magnetic tape MT, time code trunks T, c, a control track T ctL, and a cue track T0 are provided along the tape running direction (arrow entry direction).

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied not only to formats in which block addresses are recorded in two blocks, but also in formats in which block addresses are recorded in one block or three or more blocks. can do.

Of course, various modifications can be made without departing from the gist of this invention.

〔Effect of the invention〕

According to the digital signal editing method of the present invention, a flag in a block of a specific block address is used as an editing flag, and by setting this editing flag in accordance with editing of a digital signal, the reproduced block address is If there is a discrepancy with the address value from a so-called flywheel counter, etc., it can be immediately determined whether the discrepancy is due to an oversight such as a CRCC or an edit by looking at the above edit flag. It becomes possible to import data that was previously rejected.

[Brief explanation of the drawing]

All figures are for explaining a digital signal editing method according to an embodiment of the present invention, and FIG. 1 shows an example in which an audio PCM signal is recorded with a fixed head in a VTR that digitally records a so-called high-definition television signal. FIG. 2 is a diagram illustrating an example of the block address and flag in this synchronization signal word, and FIG. The diagram shows the above audio PC
Figure 4 shows the data format when converting M signal data into blocks. Figure 4 shows the recording format of audio data for one block. Figures 5 to 7 show the data format used when editing the audio signal. FIG. 8 is a schematic plan view showing a specific example of a recording pattern of a recording track on a magnetic tape. 1'''7゛口=-, '7 Ka's Ishiki - Figure 4 Feema lhi

Claims (1)

[Claims] Digital data is divided into blocks for each word,
In a digital signal editing method for editing a digital signal in which block addresses are sequentially assigned to each block, at least one predetermined bit in one block is set as a flag bit, and the above-mentioned data according to the block address is set as a flag bit. A digital signal characterized in that by defining a flag bit, the flag bit in a block of a specific block address is set as an editing flag, and the editing flag is set corresponding to an editing point of the digital signal. How to edit.