JPH01188140A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To attain high speed transmission by executing arbitration in an arbitration control part in correspondence to a transmission allowing signal to be sent from a data transmission path in an output side. CONSTITUTION:Whether the arrival time difference of packet data 1 and 2, which are an input to data transmission pathes 10 and 40, is in the range of a constant time difference or not is detected in a competition detecting part 70. When the difference is out of the range of the constant time difference, time adjustment is not executed. When the difference is in the range of the constant time difference, in order to execute the time adjustment, the packet data of late arrival are temporarily stopped in a data transmitting path 20 (50) until the difference goes out of the range of the constant time difference. In a word number counting part 800, a data number to pass through the data transmission pathes 20 and 50 is counted and a pulse for the unit of packets is generated. In an arbitration control part 80. in correspondence to the transmission allowing signal to be sent from a transmission path 100, which is the transmission path in the output side, an output order is arbitrated according to the crowded condition of the respective packet data in the parallel transmission pathes in an input side and the data for the unit of the packets to be composed of the arbitrary word number are outputted to the data transmission path 100. Thus, the high speed transmission can be executed.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a data transmission device, and in particular, to a data transmission device that serially transmits packet data transmitted via a plurality of parallel input-side transmission paths to an output-side transmission path. The present invention relates to an improvement in a data transmission device that transmits packet-based data consisting of an arbitrary number of words.

<Prior Art> In a data processing device using an electronic computer or the like, a plurality of processing devices are coupled through communication using digital signals. When data processing is distributed and processed by multiple processing devices, the results obtained by each processing device are sent to a second processing device that is different from the group of processing devices, and this second processing device Now, we will execute the process using the multiple received results. For example, there is a device disclosed in Japanese Patent Application No. 61-17543. <Problems to be Solved by the Invention> In each of the above-mentioned processing devices, the time required to process distributed data depends on the received data and the demands on the device. Depending on the content of the processing to be performed, data groups resulting from each process are not always transmitted in the same order and at the same time intervals. However, if the transmission path itself can have a buffer function that minimizes the retention of transmitted data groups caused by variations in processing time in the second processing device, the amount of hardware in the processing device can be reduced. be able to.

Therefore, the main object of the present invention is to be able to accept data transmitted through a plurality of parallel input transmission lines up to the capacity limit of the transmission line, and to output data in the order in which the transmitted data groups arrive. To provide a data transmission device capable of transmitting data to a side transmission line, arbitrating the output when a group of transmission data is retained, and transmitting data in packets consisting of an arbitrary number of words to an output side transmission line. .

<Means for Solving the Problems> The data transmission device according to the present invention transmits data to a plurality of parallel input side transmission lines at an arbitrary time interval that is longer than the time interval specific to each transmission line and asynchronously with each other. It is possible to receive the transmitted number of packet data up to the limit of the physical capacity of the transmission path. Furthermore, data in packet units consisting of an arbitrary number of words can be transmitted serially to the output transmission path in order to reduce the stagnation as much as possible in the order in which the packet data arrives and when the packet data is stagnant.

For this purpose, the data transmission device includes a data transmission means having a conflict detection function provided corresponding to each of two arbitrary sets of a plurality of parallel transmission paths, and a transmission permission signal sent from the transmission path on the output side. In response to this, the data transmission means having the contention detection function arbitrates in the order of arrival of packet data and, if packet data is accumulated, to alleviate the accumulation as much as possible, and serially connects the data transmission means to the output side transmission line. and arbitration control means for transmitting data in packet units consisting of an arbitrary number of words.

Effects> The data transmission device according to the present invention uses a plurality of transmission means having a conflict detection function to determine the order of arrival of packet data and the order of arrival of packet data in response to a transmission permission signal sent from the transmission path on the output side. If there is a stagnation, arbitration is performed to alleviate the stagnation as much as possible, and the packet data sent from the corresponding transmission path is accepted up to the limit of the physical capacity of the transmission path, and the delay time required for arbitration control is Data in units of packets consisting of an arbitrary number of words can be sequentially transmitted to the output side transmission line within the transfer time specific to the transmission line.

<Example> FIG. 1 is a schematic block diagram of an embodiment of the present invention.

In the embodiment shown in FIG. 1, two data transmission lines 10
．． 20.30 and 40.50°60 are provided in parallel, and if the arrival time difference of packet data l and packet data 2, which are input to the data transmission lines 10 and 40, is within the constant time difference range. In order to perform time adjustment, packet data arriving later is sent to the data transmission path 20.
Or set it to 50 to pause until it is out of the fixed time difference range. In the word number counting section 800, the data transmission line 20
Then, the number of data passing through the data transmission path 50 is measured to generate pulses in units of packets. In the arbitration control unit 80,
In response to a transmission permission signal being sent from the transmission line 100, which is the output side transmission line, the output order is adjusted according to the congestion of each packet data on the parallel input side transmission lines, and a packet consisting of an arbitrary number of words is generated. The unit data is output to the data transmission path 100.

Next, the specific operation of the embodiment shown in FIG. 1 will be explained. In the initial state, data transmission path 1 on the output side
00 is a state in which packet data can be received, and AC
A K signal AK100 is sent back to the arbitration control section 80. Arbitration control section 80 receives ACK signal AK100 from data transmission line 100 on the output side and outputs ACK signals AK30 and AK60 to data transmission lines 30 and 60.

The ACK signals AK30 and AK60 are not allowed to be sent to the data transmission path 100 at the same time, but only one of them is allowed to be sent to the data transmission path 100. In this embodiment, for example, consider a state in which the data transmission path 60 is permitted and the data transmission path 30 is prohibited.

When the first word of packet data arrives at the data transmission path IO, the first word data and the transmission signal C10 are transmitted to the data transmission path 30 via the data transmission path 20, and the transmission signal CIO is sent to the word number counting section 800. transmitted.

The word number counting section 800 measures the number of data passing through the data transmission path 20, generates pulses in units of packets, and transmits the generated pulses to the arbitration control section 80. The arbitration control unit 80 confirms that there is no packet data on the data transmission path 60, and if there is no packet data, permits the data transmission path 30 to transmit data to the data transmission path 100, and also allows the data transmission path 60 to transmit data. On the other hand, data transmission to the data transmission path 100 is prohibited. The data transmission path 30 is the data transmission path 10
Since transmission to 0 is permitted, data in packet units consisting of an arbitrary number of words is transmitted to the data transmission path 100.

When the packet yl-data passes through the data transmission path 100, an ACK signal AK30 is sent back from the data transmission path 100 to the data transmission path 30 via the arbitration control unit 80, and from the data transmission path 30 to the data transmission path 100. Then, when the first word of the packet data arrives at the data transmission path 40, the first word data and the transmission signal C20 are transmitted to the data transmission path 60 via the data transmission path 50. At the same time, the transmission signal C20 is transmitted to the word number counting section 800. The word number counting section 800 measures the number of data passing through the data transmission path 50, generates a pulse in units of packets, and transmits the generated pulse to the arbitration control section 80. The arbitration control unit 80 confirms that there is no data on the data transmission path 30, and if there is no data, the data transmission path 60 is
0 and data transmission path 30.
However, data transmission to the data transmission path 100 is prohibited. Since the data transmission path 60 has been permitted to transmit data to the data transmission path 100, it transmits data in packet units consisting of an arbitrary number of words to the data transmission path 100. Then, when the packet data passes through the data transmission path 100, the AC
The K signal AK60 is sent from the data transmission path 100 to the arbitration control unit 8.
0 to the data transmission path 60.
Allow data to be sent from 0.

Next, a case where packet data 2 is input a little later than packet data 1 will be described. When the first word of packet data arrives at the data transmission path 10, its transmission signal CIO is sent to the data transmission path 20 and also to the conflict detection section 70, and the conflict detection section 70 transmits the data within a certain time difference. If data exists on the data transmission path 40, the packet data 2 is temporarily stopped on the data transmission path 50, but after the packet data 1 passes through the data transmission path 20, the packet data 2 that was stopped on the data transmission path 50 starts moving. . In this way, the conflict detection section 70 detects the degree of conflict between the packet data 1 and the packet data 2, temporarily stops the packet data whose arrival time is late on the data transmission path 20 or the data transmission path 50, and prevents malfunction in the arbitration control section 80. prevent.

FIG. 2 is a specific circuit diagram of an embodiment for arbitrating two independent two-word structured packet data. In addition, the second
In the specific example shown in the figure, transmission permission signals from the data transmission lines 3o and 60, which are signals based on data transmission, are input to the word number counting section 800.

First, the configuration will be explained with reference to FIG. 1st
The data transmission sections 10 to 30 and 40 to 60 shown in the figure are respectively composed of transfer control sections 11 to 31 and 41 to 61 and data holding means 12 to 32 and 42 to 62.

Further, the data transmission path 100 is composed of a transfer control section 101 and a data holding means 102. Transfer control unit 11.21
．． 31.41.51. and 61 each have one transmission signal input, one transmission permission signal input, one transmission signal output,
Handshake transfer control is performed by outputting one transmission permission signal. However, the transfer control units 21 and 51 have an added function of forcibly prohibiting independent transfer control and not transmitting a transmission signal by inputting a transmission prohibition signal. However, the transfer control unit 101 has a built-in function to perform a logical sum on two different transmission signal inputs, and performs handshake control similar to transfer control units 11, 31, 41, and 61 for transfer control. .

A detailed circuit of the transfer control units 11, 31, 41 and 61 is shown in FIG. 3, a detailed circuit of the transfer control units 21 and 51 is shown in FIG. 4, and a detailed circuit of the transfer control unit 101 is shown in FIG. Data holding means 12.22.32.42゜52.62 and 1
02 is the content of Di at the falling edge of the clock pulse.
The configuration is such that the data is transferred to i. The conflict detection unit 70 includes D type flip frogs 71 and 72 and an inverter 73.
and 74 and AND gates 75 and 76. The D-type flip-flops 71 and 72 are configured to output the contents of the D input to the Q output at the falling edge of the clock pulse.The arbitration control section 80 consists of Nant gates 81, 82, 83 and 84, and AND gates 85 and 86. , D-type flip-flops 87 and 88, and NOR gates 89 and 90. D type flip-flops 87 and 88 are configured to output the contents of the D input to the Q output at the falling edge of the clock pulse. Word number counting section 800 is composed of D type flip-flops 801, 802, 803 and 804 and NOR gates 805 and 806.

D-type flip-flops 801 and 802 are configured to output the contents of the D input (02-Ql) to the O1 output at the falling edge of the clock pulse, and D-type flip-flops 803 and 804 output the contents of the D input (02-Ql) to the O1 output at the rising edge of the clock pulse. The configuration is such that the contents of Q2=Ql) are output to the Ql output.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

In the initial state, the reset signal RESET (“L” level) is applied to the transfer control unit 11.21°31.41.51.6
1 and 101 and and myo 75.76.85 and 86
and Nantes Gate 82, transfer control unit 11.21.31
．． 41.51 and 61 are each initial reset,
The respective Q1 outputs go to the °H° level, and the Q2 outputs also go to the "H" level. When the transfer control unit 101 is reset, the Q1 output goes to “H” level, and the Q2 output goes to °L°.
become. The transfer control units 21 and 51 can inhibit data transmission to the next stage using the inhibit signal INH. Also, D type flip-flop 801.802
．． 803 and 804 set the Q1 output to the "H" level and the Q2 output to the L" level by the reset signal. The D type flip-flops 71 and 72 set the Q output to the °H" level by the reset signal. The D type flip-flops 87 and 88 change the Q output to °L" by the reset signal.
level. The output of the Nant gate 82 becomes "Ho" by the reset signal, and is input to the Nant gate 81 forming a flip-flop.The remaining inputs of the Nant gate 81 are connected to D-type flip-flops 801 and 8.
Since the Q2 outputs of 03 are both "L", they become "H", and the output of the Nant gate 81 becomes "L", and the flip-flop in the previous stage composed of the Nandt gates 81 and 82 becomes stable. The subsequent stage flip-flop I77, which is composed of Nant gates 83 and 84, receives the output from the previous stage, and since the reset signal is input to the Nant gate 83, the output of the Nant gate 83 becomes "H", and the Nant gate 83 receives the output from the previous stage.
The output of the gate 4 becomes "Lo" and the flip 70 at the subsequent stage is also stabilized.The output of the Nand gate 83 is given to the input of the NOR gate 89, so the output of the NOR gate 89 becomes "L".
Therefore, data transmission from the data transmission line 30 to the transmission line 100 is prohibited. The output of the Nant gate 84 is given to the Noah gate 900 Å force by the Noah gate 90.
The output is “H”.

This enables data transmission from the data transmission path 60 to the transmission path 100.

In this state, the packet data l is not applied to the data holding means 12, and the pulse signal Cl0 ("L" level)
is given to the transfer control unit 11, the transfer control unit 11 receives the Q1 output since the Q2 output of the transfer control unit 21 is “■”.
The output is set to the °L° level, and the 01 output of the transfer control section 11 is transmitted to the transfer control section 21, and the data holding means 1
2 clock pulse and outputs the contents of packet data 1 to Qi of data holding means 12. Since the Q2 output of the transfer control unit 31 is “H”, the transfer control unit 21
1 output is set to °L" level, and is transmitted to the Ql ratio output transfer control section 31 of the transfer control section 21, and becomes a clock pulse of the data holding means 22, and the Qi of the data holding means 12.
The contents are outputted to Qi of the data holding means 22. D type flip-flops 801 and 803 and Noah gate 80
5 divides the Q2 output of the transfer control section 31 into two, and the output becomes the input of the Nandt gate 81. In this way, by arbitrarily dividing the frequency of the Q2 output of the transfer control section 31, the pulse input to the Nant gate 81 can perform arbitration control for data in units of packets consisting of an arbitrary number of words. The output of the NOR gate 805 becomes the input of the Nandt gate 81, changing the output of the Nandt gate 81 from "L" to "H", and this output becomes the input of the Nandt gates 82 and 83.

Since all the inputs of the Nant gate 82 become ``H'', the output becomes ``Lo'', thereby stabilizing the seven lip-flops at the front stage. In addition, as a result, the output of the Nant gate 84 in the subsequent flip-flop is stabilized as ``H°The output of the Nant gate 83 is L''.
9, and by activating the transmission permission signal from the transfer control unit 101, the Ql ratio output of the transfer control unit 31 is set to L'' level and is transmitted to the transfer control unit 101, and the transmission permission signal AK becomes ``H''.

In this case, the Ql ratio output of the transfer control unit 101 becomes °L°, and the clock pulse of the data holding means 102 is generated, and the contents of Di of the data holding means 102 are outputted to Qi. During the period when the transfer control unit 31 is outputting to the transfer control unit 101, the output °H of the Nandt gate 84 is held as the output of the subsequent flip-flop and input to the NOR gate 90, so the output of the NOR gate 90 is 'L'. The output Qi of the data holding means 62 is held by inhibiting the output from the transfer control unit 61 to the transfer control unit lo1 and setting the output of the D type clip flop 88 to “L” with the output of the transfer control unit 31. The Qi ratio output of the data holding means 32 is prevented from colliding with each other by setting the impedance to zero.

Next, when the packet data 2 is given to the data holding means 42 and the pulse signal C20 is given to the transfer control section 41, the explanation of the operation accompanying the input of the packet data 1 is omitted because it is completely the same as that described above.

Next, a case will be described in which packet data 2 is input a little later than kerato data 1 after the initial state. The first word of packet data 1 is given to the data holding means 12, the pulse signal CIO is given to the transfer control section 11, and the pulse signal CIO is given to the inno (-tough 3), and the pulse signal C1O changes from "Lo" to "H" again. By the time it returns, the first word of packet data 2, which was input slightly later than packet data 1, is given to the data holding means 42, and the pulse signal C
20 is given to the transfer control unit 41, the D input of the D type flip-flop 72 is "L", so the pulse signal C
When IO returns from “Lo” to “H3” again, Q output is °L°
Therefore, the pulse transmitted to the transfer control unit 51 is not sent to the transfer control unit 61 but is stopped by the transfer control unit 51. When the Q1 output of the transfer control unit 11 is transmitted to the transfer control unit 21, the output of the antenna 76 becomes “Lo”, setting the Q output of the D type flip-flop 72, and the pulse that had been stopped in the transfer control unit 51 is is again permitted to be transferred and is transmitted to the transfer control unit 61.The case where packet data 1 is input a little later than packet data 2 can be explained in exactly the same way, so the explanation will be omitted.

When two packet data 1 and data 2 are input in conflict, the packet data input late is temporarily stopped by the flip-flops of Nant gates 81 and 82 and the flip-flops of Nant gates 83 and 84.

As described above, according to this embodiment, the transmission line 1 on the output side
When 00 is empty, if only packet data 1 exists and packet data 2 does not exist, packet data l will be output sequentially, and if only packet data 2 exists and packet data 1 does not exist, packet data 2 will be output. Output sequentially. In addition, when packet data 1 and packet data 2 are transmitted at the maximum transfer capacity of the data transmission line, the processing capacity of the output side data transmission line 100 cannot keep up, so the data transmission line 30° 20 and 10 and the data transmission Data stays on paths 60, 50 and 40. In this case, the data transmission path 30 and the data transmission path 60 alternately transmit packet data on each transmission path to the data transmission path lOO in packet units.

<Effects of the Invention> As described above, according to the present invention, even when data on a plurality of parallel transmission paths is transmitted at arbitrary time intervals and asynchronously with each other, the transmission from the data transmission path on the output side is By arbitrating in the arbitration control unit in response to the permission signal being sent, it is possible to accept up to the physical capacity of the transmission line, and there is no delay time required for arbitration control. Data in packet units can be sequentially transmitted to the output transmission path according to the counting results at .

Therefore, a highly reliable arbitration mechanism can be realized along with high-speed transmission.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of an example in which data sent from two data transmission paths is transmitted to an output data transmission path. FIGS. 3, 4, and 5 are circuit diagrams of one embodiment of the transfer control section. In the figure, 10.20.30.40.50°60.1
00 is a data transmission path, 70 is a conflict detection unit, 80 is an arbitration control unit, 800 is a word count unit, 11.21.31.4
1.51.61.101 is the transfer control unit, 12.22.3
2.42.52.62゜10, 2 is data holding means, 7
1.72.87.88.801,802,803.80
4 is a D type clip flop, 73.74 is an inverter, 75°76.85.86 is an AND gate, 81.8
2゜83.84 is Nantes Gate, 89.90,805゜Representative Patent Attorney Takeshi Sugiyama (and 1 other person) -! 0 σ Procedural amendment (method) 1. Display of the case 1986 Patent Application No. 12784 2, Name of the invention Data transmission device 3, Person making the amendment Relationship to the case Patent applicant representative Haruo Tsuji 4, Agent

Claims (1)

[Claims] 1. A data transmission device for serially transmitting a plurality of packet data transferred via a plurality of parallel input-side transmission lines to an output-side transmission line, the plurality of data transmission lines comprising: conflict detection means for detecting that two sets of packet data exist on any two sets of parallel transmission lines, and that the arrival time difference between the two sets of packet data is within a certain time difference range; and in response to a transmission permission signal being sent from the output transmission path, the data transmission means having the conflict detection means outputs data according to the congestion of packet data of each of the plurality of parallel input transmission paths. 1. A data transmission device comprising an arbitration control means for arbitrating the order and transmitting data in packet units having an arbitrary number of words set in advance to the transmission path on the output side.