JPH01187963A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01187963A
JPH01187963A JP1307388A JP1307388A JPH01187963A JP H01187963 A JPH01187963 A JP H01187963A JP 1307388 A JP1307388 A JP 1307388A JP 1307388 A JP1307388 A JP 1307388A JP H01187963 A JPH01187963 A JP H01187963A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead frame
semiconductor
semiconductor device
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1307388A
Other languages
Japanese (ja)
Inventor
Takao Ando
安藤　隆夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP1307388A priority Critical patent/JPH01187963A/en
Publication of JPH01187963A publication Critical patent/JPH01187963A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the mounting area of a device by loading semiconductor chips onto both the surface and the rear of a lead frame. CONSTITUTION:At least one first semiconductor chip 5a loaded on one surface of a lead frame 2, at least one second semiconductor chip 5b loaded at the position of loading of the first semiconductor chip 5a on the other surface of the lead frame 2 and a sheathing resin 8 formed, covering the outer circumferences of said first and second semiconductor chips 5a, 5b are included. A semiconductor device is constituted, containing the lead frame 2, the first semiconductor chip 5a fixed onto the top face of an island 3 for the lead frame, the second semiconductor chip 5b fastened onto the underside of the island 3, bonding wires 7a connecting electrode pads 6a for the semiconductor chip 5a and lead terminals 4, bonding wires 7b connecting electrode pads 6b for the semiconductor chip 5b and the lead terminals 4 and the sheathing resin 8.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

〔従来の技術〕[Conventional technology]

従来の半導体装置は、第３図（ａ）及び（ｂ）に示すよ
うに、リードフレーム２のアイランド３の表又は裏のい
ずれか一方の面に半導体チップ５を搭載し、半導体チッ
プ５の電極パッド６とリードフレーム３のリード端子４
とを金又は銅のホンディングワイヤ７で接続し、半導体
チップ５の外周を覆いリード端子４の外側の先端を露出
させて外装樹脂８（第３図（ａ）では−点鎖線で示す）
で樹脂封止した後、リード端子４をリードフレーム２の
フレームから切離し、リード端子４の露出部を折曲げ加
工して半導体装置を形成していた。As shown in FIGS. 3(a) and 3(b), a conventional semiconductor device has a semiconductor chip 5 mounted on either the front or back surface of an island 3 of a lead frame 2, and electrodes of the semiconductor chip 5. Pad 6 and lead terminal 4 of lead frame 3
are connected with a gold or copper honding wire 7, the outer periphery of the semiconductor chip 5 is covered, and the outer tips of the lead terminals 4 are exposed, and an exterior resin 8 (indicated by the - dotted chain line in FIG. 3(a)) is formed.
After sealing with resin, the lead terminals 4 were separated from the frame of the lead frame 2, and the exposed portions of the lead terminals 4 were bent to form a semiconductor device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置は、同一装置に少くとも１個
の半導体チップを搭載する場合、リードフレームの表又
は裏のいずれか一方の面に半導体チップを固着している
ので、装置の外形が大きくなり、従って、基板への実装
面積が大きくなるという欠点がある。In the conventional semiconductor device described above, when at least one semiconductor chip is mounted on the same device, the semiconductor chip is fixed to either the front or back surface of the lead frame, so the external size of the device is large. Therefore, there is a drawback that the mounting area on the board becomes large.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、リードフレームの一方の面に搭
載した少くとも１個の第１の半導体装置ブと、前記リー
ドフレームの他方の面の前記第１の半導体チップの搭載
位置に搭載した少くとも１個の第２の半導体チップと、
前記第１及び第２の半導体チップの外周を覆って形成さ
れる外装樹脂とを含んで構成される。The semiconductor device of the present invention includes at least one first semiconductor device block mounted on one surface of a lead frame, and at least one semiconductor device block mounted at a mounting position of the first semiconductor chip on the other surface of the lead frame. a second semiconductor chip;
and an exterior resin formed to cover the outer peripheries of the first and second semiconductor chips.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）及び（ｂ）はそれぞれ本発明の一実施例の
平面図及びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention, respectively.

第１図に示すように、中央部に半導体チップを搭載する
アイランド３とアイランド３の対向する２辺の外側に放
射状に形成された複数のリード端子４を備えたリードフ
レーム２と、アイランド３の上面に固着された第１の半
導体チップ５ａと、アイランド３の下面に半導体チップ
５ａと反対向きに固着された第２の半導体チップ５ｂと
、半導体チップ５６の電極パッド６ａとリード端子４と
を接続する金又は銅のボンディングワイヤ７゜と、半導
体チップ６ａの電極パッド６ｂとリード端子４とを接続
する金又は銅のボンディングワイヤ７ｂと、半導体チッ
プ５ａ、５ｂの外周を覆いボンディングワイヤ７−．７
ｂを包んで形成される外装樹脂８（第１図（ａ）では１
点鎖線で示す）とを含んで構成される。As shown in FIG. 1, a lead frame 2 includes an island 3 on which a semiconductor chip is mounted in the center, a plurality of lead terminals 4 formed radially on the outside of two opposing sides of the island 3, and The first semiconductor chip 5a fixed to the upper surface, the second semiconductor chip 5b fixed to the lower surface of the island 3 in the opposite direction to the semiconductor chip 5a, and the electrode pads 6a of the semiconductor chip 56 and the lead terminals 4 are connected. gold or copper bonding wires 7°, gold or copper bonding wires 7b connecting the electrode pads 6b of the semiconductor chip 6a and the lead terminals 4, bonding wires 7-. 7
Exterior resin 8 (1 in Fig. 1(a)
(indicated by the dotted chain line).

第２図は第１図の実施例を用いて製作された半導体装置
の斜視図である。FIG. 2 is a perspective view of a semiconductor device manufactured using the embodiment shown in FIG.

第１図に示す外装樹脂８の形成後、リードフレーム２の
フレームからリード端子４を切離し、外装樹脂８からの
露出部を折曲げ加工することにより、第２図に示すよう
に、半導体装Ｎ１が得られる。After forming the exterior resin 8 shown in FIG. 1, the lead terminals 4 are separated from the frame of the lead frame 2, and the exposed portions of the exterior resin 8 are bent to form the semiconductor package N1 as shown in FIG. is obtained.

なお、本発明はＤＩＲ，ＱＦＰ型のパッケージについて
も適用できる。Note that the present invention can also be applied to DIR and QFP type packages.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、リードフレームの表と裏
の両面に半導体チップを搭載することにより、１個のリ
ードフレーム少くとも２個の半導体チップを搭載できる
ので、装置の実装面積を小さくできる効果がある。As explained above, the present invention allows at least two semiconductor chips to be mounted on one lead frame by mounting semiconductor chips on both the front and back sides of the lead frame, thereby reducing the mounting area of the device. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）及び（ｂ）はそれぞれ本発明の一実施例の
平面図及びＡ−Ａ’線断面図、第２図は第１図の実施例
を用いて製作された半導体装置の斜視図、第３図（ａ）
及び（ｂ）はそれぞれ従来の半導体装置の一例の平面図
及びＢ−Ｂ’線断面図である。 １・・・半導体装置、２・・・リードフレーム、３・・
・アイランド、４・・・リード端子、５．５−．５ｂ・
・・半導体チップ、６，６．．６ゎ・・・電極パッド、
７゜７ａ、７ｂ・・・ボンディングワイヤ、８・・・外
装樹脂。1(a) and (b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention, respectively, and FIG. 2 is a perspective view of a semiconductor device manufactured using the embodiment of FIG. 1. Figure, Figure 3(a)
and (b) are a plan view and a sectional view taken along the line BB' of an example of a conventional semiconductor device, respectively. 1... Semiconductor device, 2... Lead frame, 3...
・Island, 4...Lead terminal, 5.5-. 5b・
...Semiconductor chip, 6,6. ．． 6ゎ・・・electrode pad,
7°7a, 7b...Bonding wire, 8...Exterior resin.

Claims (1)

【特許請求の範囲】[Claims] 　リードフレームの一方の面に搭載した少くとも１個の
第１の半導体チップと、前記リードフレームの他方の面
の前記第１の半導体チップの搭載位置に搭載した少くと
も１個の第２の半導体チップと、前記第１及び第２の半
導体チップの外周を覆って形成される外装樹脂とを含む
ことを特徴とする半導体装置。At least one first semiconductor chip mounted on one surface of the lead frame, and at least one second semiconductor mounted at the mounting position of the first semiconductor chip on the other surface of the lead frame. A semiconductor device comprising: a chip; and an exterior resin formed to cover the outer peripheries of the first and second semiconductor chips.
JP1307388A 1988-01-22 1988-01-22 Semiconductor device Pending JPH01187963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1307388A JPH01187963A (en) 1988-01-22 1988-01-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1307388A JPH01187963A (en) 1988-01-22 1988-01-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01187963A true JPH01187963A (en) 1989-07-27

Family

ID=11822975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1307388A Pending JPH01187963A (en) 1988-01-22 1988-01-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01187963A (en)

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