JPH01187431A - Airtightness testing method for semiconductor device - Google Patents

Airtightness testing method for semiconductor device

Info

Publication number
JPH01187431A
JPH01187431A JP63013014A JP1301488A JPH01187431A JP H01187431 A JPH01187431 A JP H01187431A JP 63013014 A JP63013014 A JP 63013014A JP 1301488 A JP1301488 A JP 1301488A JP H01187431 A JPH01187431 A JP H01187431A
Authority
JP
Japan
Prior art keywords
light
cavity
airtightness
semiconductor device
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63013014A
Other languages
Japanese (ja)
Inventor
Hirokazu Yuasa
湯淺 啓和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63013014A priority Critical patent/JPH01187431A/en
Publication of JPH01187431A publication Critical patent/JPH01187431A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)
  • Examining Or Testing Airtightness (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To facilitate preparations for a test and to speed up the test by irradiating the semiconductor device which has a cavity internally with light from outside and measuring the quantity of light entering the cavity. CONSTITUTION:Plural light sources 1 are arranged around the device 2 whose airtightness is to be tested. The device 2 is structure by sealing a semiconductor chip 5 which has a light quantity detecting element 4 in a package 8 wit sealing glass 9 and the cavity 3 is formed in the package 8. When there is an airtightness defect part 10 whose airtightness is incomplete in the sealing glass 9, light emitted by a light source 1 such as a mercury vapor lamp enters the cavity 3 through the defect part 10 and is reflected irregularly by the internal wall surface of the cavity 3 and part of the irregularity reflected light illuminates the element 4 and is converted into a light quantity detection signal. This signal is supplied to a detector through a wire 6 and an external lead 7. Thus, the airtightness defect of the device 2 can be detected speedily with ease. A P-N junction diode is used as the element 4, but the diode which is present in the device 2 originally can be utilized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の気密性試験方法に関し、特に内部
に空洞を有する半導体装置の気密性試験方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing the airtightness of a semiconductor device, and particularly to a method for testing the airtightness of a semiconductor device having an internal cavity.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置の気密性試験方法としては、
ヘリウムガスによる方法、ラジオアイソトープにより方
法、フロロカーボンによる方法。
Conventionally, the hermeticity test method for this type of semiconductor device is as follows:
Helium gas method, radioisotope method, fluorocarbon method.

浸透性染料による方法及び重量増加による方法がある。There are methods using penetrating dyes and methods using weight increase.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置の気密性試験方法は、ヘリウ
ムガスによる方法では、被試験半導体装置にヘリウムガ
スを加圧しなあと真空雰囲気中に移し、質量分析式のヘ
リウムガス検知器で検査するので、加圧しなければ試験
できないなめ迅速に試験できないという欠点がある。又
、ヘリウムガスが濡れる箇所を検知できないので、気密
性の不完全な箇所を知ることができないという欠点があ
る。
In the conventional method for testing the airtightness of semiconductor devices described above, in the method using helium gas, the semiconductor device under test is pressurized with helium gas, then transferred to a vacuum atmosphere, and tested using a mass spectrometry type helium gas detector. It has the disadvantage that it cannot be tested quickly unless it is pressurized. In addition, since it is not possible to detect locations where helium gas gets wet, there is a drawback that locations where airtightness is incomplete cannot be detected.

ラジオアイソトープによる方法では、被試験半導体装置
に放射能を有するガスを圧入しな後放射能の存在しない
場所に移し、被試験半導体装置から漏れてくる放射能を
検出するので、加圧しなければ試験できないなめ迅速に
試験できないという欠点がある。又、放射能を有するガ
スを使用するので、完全上の管理が難しいという欠点が
ある。
In the radioisotope method, a radioactive gas is injected into the semiconductor device under test, and then the device is moved to a place where there is no radioactivity, and the radioactivity leaking from the semiconductor device under test is detected. The disadvantage is that it cannot be tested quickly. Furthermore, since a radioactive gas is used, there is a drawback that perfect control is difficult.

フロロカーボンによる方法では、被試験半導体装置にフ
ロロカーボンを圧入した後フロロカーボンの沸点より高
温の液体に浸し、発生するフロロカーボンの気泡の有無
を検査するので、フロロカーボンを圧入するなめ迅速に
試験をできないという欠点がある。又、気泡の有無を人
間が見て判断することは判定が主観的になり、試験の客
観性に欠けるという欠点がある。
In the method using fluorocarbon, the fluorocarbon is press-fitted into the semiconductor device under test, and then immersed in a liquid with a temperature higher than the boiling point of the fluorocarbon, and the presence or absence of air bubbles generated in the fluorocarbon is inspected, so the drawback is that the test cannot be performed quickly because the fluorocarbon is press-fitted. be. In addition, when humans judge the presence or absence of bubbles by looking at them, the judgment becomes subjective and there is a drawback that the test lacks objectivity.

浸透性染料による方法では、被試験半導体装置に浸透性
染料を圧入して外側に付着した浸透性染料を洗浄した後
、気密性の不完全な箇所に侵入した浸透性染料を紫外線
照射しなから拡大鏡で観察するので、浸透性染料を圧入
するため迅速に試験できないという欠点がある。又、浸
透性染料を拡大鏡で観察することは判定が主観的になり
、試験の客観性に欠けるという欠点がある。
In the method using penetrating dyes, the penetrating dye is press-fitted into the semiconductor device under test and the penetrating dye adhering to the outside is cleaned, and then the penetrating dye that has penetrated into the imperfectly airtight areas is not irradiated with ultraviolet rays. Since observation is performed using a magnifying glass, a penetrating dye is injected under pressure, so the test cannot be performed quickly. Furthermore, observing the penetrating dye with a magnifying glass has the disadvantage that the judgment becomes subjective and the test lacks objectivity.

重量増加による方法では、被試験半導体装置にフロロカ
ーボンを圧入して圧入前後における重量の差を測定する
ので、フロロカーボンを加圧するなめ迅速に試験できな
いという欠点がある。又、フロロカーボンが侵入した箇
所がわからないので、気密性の不完全な箇所を知ること
ができないという欠点がある。
In the weight increase method, fluorocarbon is press-fitted into the semiconductor device under test and the difference in weight before and after press-fitting is measured, which has the disadvantage that the fluorocarbon cannot be tested quickly because the fluorocarbon is pressurized. Furthermore, since it is not possible to determine where the fluorocarbon has penetrated, there is a drawback that it is not possible to determine where the airtightness is incomplete.

〔問題点を解決するための手段〕 本発明の半導体装置の気密性試験方法は、内部に空洞を
有する半導体装置に外部から光を照射し、前記空洞内に
侵入した光量を測定するように構成される。
[Means for solving the problem] The airtightness test method for a semiconductor device of the present invention is configured to irradiate a semiconductor device having a cavity inside with light from the outside and measure the amount of light that has entered the cavity. be done.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を説明するための気密性
試験器の要部断面図である。
FIG. 1 is a sectional view of a main part of an airtightness tester for explaining a first embodiment of the present invention.

第1図に示すように、気密性を試験される半導体装置2
の周囲に複数の光源1を配置している。
As shown in FIG. 1, a semiconductor device 2 to be tested for airtightness
A plurality of light sources 1 are arranged around the.

又、半導体装置2は光量検出素子4を有する半導体チッ
プ5を封止ガラス9を介してパッケージ8で封止した構
造であり、パッケージ8内には空洞3を有する。光量検
出素子4の電極はワイヤ6により外部リード7に接続さ
れていて、光量検出素子4からの光量検出信号は外部リ
ード7から図示しない検出器に供給される。
The semiconductor device 2 has a structure in which a semiconductor chip 5 having a light amount detection element 4 is sealed in a package 8 via a sealing glass 9, and the package 8 has a cavity 3. The electrode of the light amount detection element 4 is connected to an external lead 7 by a wire 6, and the light amount detection signal from the light amount detection element 4 is supplied from the external lead 7 to a detector (not shown).

いま、半導体装置2の封止ガラス9に気密性の不完全な
気密不良箇所10があるとする。
Now, assume that there is a defective airtight area 10 in the sealing glass 9 of the semiconductor device 2 where the airtightness is incomplete.

第1図において、水銀ランプの光源1から発射された光
は気密不良箇所10を通って半導体装置2の空洞3に入
り、空洞3の内壁面で乱反射し、乱反射した光の一部が
光量検出素子4を照射して、光量検出信号に変換される
In FIG. 1, light emitted from a light source 1 of a mercury lamp enters a cavity 3 of a semiconductor device 2 through an airtight area 10, is diffusely reflected on the inner wall surface of the cavity 3, and a portion of the diffusely reflected light is detected by the light amount detection. The element 4 is irradiated with light and converted into a light amount detection signal.

光量検出素子4としてはPN接合ダイオードを用いるが
、PN接合ダイオードは多くの場合この目的のなめに特
別に設置する必要はなく、元来、半導体装置2内に存在
しているものを利用できる。又、半導体装置の緒特性の
内、光に敏感な特性も利用することができる。
A PN junction diode is used as the light amount detection element 4, but in many cases there is no need to specifically install a PN junction diode for this purpose, and one that originally exists in the semiconductor device 2 can be used. Furthermore, among the fundamental characteristics of semiconductor devices, the light-sensitive characteristics can also be utilized.

第2図は本発明の第2の実施例を説明するための気密性
試験器の要部断面図である。
FIG. 2 is a sectional view of a main part of an airtightness tester for explaining a second embodiment of the present invention.

第2図に示すように、光源1.から発射された光は遮光
板13に設けられた細孔14を透過してビーム状のスポ
ット光となり、試験される半導体装置23を照射する。
As shown in FIG. 2, light source 1. The light emitted from the light shielding plate 13 passes through the pores 14 provided in the light shielding plate 13, becomes a beam-shaped spot light, and irradiates the semiconductor device 23 to be tested.

半導体装置2aは支持部15に固定され、支持部15に
より前後左右への移動及び回転の操作を受けるため、半
導体装置2aの表面をスポット光がくまなく走査する。
The semiconductor device 2a is fixed to the support portion 15, and is moved back and forth, left and right, and rotated by the support portion 15, so that the spot light thoroughly scans the surface of the semiconductor device 2a.

いま、封止リング12を介してパッケージ8aの上面の
開口を封止するキャップ11に気密不良箇所10.があ
るとする。ビーム状のスポット光が気密不良箇所10.
上を照射しなとき半導体装置2aの空洞3.内に光が入
り、半導体チップ5a上に形成された光量検出素子4a
がその光を検出して、光量検出信号がワイヤ6を介して
外部リード7aから出力される。
Now, the cap 11 that seals the opening on the top surface of the package 8a through the sealing ring 12 has a defective airtight spot 10. Suppose there is. Beam-shaped spot light indicates poor airtightness 10.
When the top of the cavity 3 of the semiconductor device 2a is not irradiated. Light enters the light amount detection element 4a formed on the semiconductor chip 5a.
detects the light, and a light amount detection signal is output from the external lead 7a via the wire 6.

光源1aとしては、パルス状の窒素ガスレーザを使用し
ている。
A pulsed nitrogen gas laser is used as the light source 1a.

光量検出素子4aが光を検知したときの照射位置から、
気密不良箇所10.を認識できる。又、窒素ガスレーザ
のパルスに同期して光量検出信号を検知することにより
、連続光では雑音に埋もれてしまうような微弱な信号を
検出でき、微小な気密不良箇所の検知ができる利点があ
る。
From the irradiation position when the light amount detection element 4a detects the light,
Poor airtightness 10. can be recognized. Furthermore, by detecting the light amount detection signal in synchronization with the pulse of the nitrogen gas laser, it is possible to detect weak signals that would be buried in noise with continuous light, and there is an advantage that minute airtight defects can be detected.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、光を照射することによっ
て内部に空洞を有する半導体装置の気密性試験を実施で
きるので、加圧作業のような前準備が不要であり、迅速
に試験を実施することができる効果がある。
As explained above, the present invention can perform an airtightness test on a semiconductor device having an internal cavity by irradiating it with light, so there is no need for preparations such as pressurization work, and the test can be performed quickly. There is an effect that can be done.

又、ビーム状の光を照射することによって容易に気密性
の不完全な箇所を知ることができる効果がある。
Furthermore, by irradiating the beam-shaped light, it is possible to easily identify areas where airtightness is incomplete.

又、放射能を有するような物質を使用しないので安全上
の管理を要しない効果がある。
Furthermore, since no radioactive substances are used, there is no need for safety management.

更に、空洞内に入った光を電気信号として検知するので
判定結果に客観性を有する効果がある。
Furthermore, since the light that has entered the cavity is detected as an electrical signal, there is an effect that the determination results are objective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を説明するための気密試
験器の要部断面図、第2図は本発明の第2の実施例を説
明するための気密試験器の要部断面図である。 1.18・・・光源、2,2a・・・半導体装置、3゜
3a・・・空洞、4,4a・・・光量検出素子、5,5
゜・・・半導体チップ、6・・・ワイヤ、7.7a・・
・外部リード、8.8a・・・パッケージ、9・・・封
止ガラス、10.10.・・・気密不良箇所、11・・
・キャップ、12・・・封止リング、13・・・遮光板
、14・・・細孔、15・・・支持部。
FIG. 1 is a sectional view of the main part of an airtightness tester for explaining the first embodiment of the present invention, and FIG. 2 is a sectional view of the main part of the airtightness tester for explaining the second embodiment of the invention. It is a diagram. 1.18...Light source, 2,2a...Semiconductor device, 3°3a...Cavity, 4,4a...Light amount detection element, 5,5
゜...Semiconductor chip, 6...Wire, 7.7a...
- External lead, 8.8a... Package, 9... Sealing glass, 10.10. ...Poor airtight areas, 11...
- Cap, 12... Sealing ring, 13... Light shielding plate, 14... Pore, 15... Support part.

Claims (1)

【特許請求の範囲】[Claims]  内部に空洞を有する半導体装置に外部から光を照射し
、前記空洞内に侵入した光量を測定することを特徴とす
る半導体装置の気密性試験方法。
1. A method for testing the airtightness of a semiconductor device, comprising irradiating light from the outside onto a semiconductor device having a cavity inside and measuring the amount of light that has entered the cavity.
JP63013014A 1988-01-22 1988-01-22 Airtightness testing method for semiconductor device Pending JPH01187431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63013014A JPH01187431A (en) 1988-01-22 1988-01-22 Airtightness testing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63013014A JPH01187431A (en) 1988-01-22 1988-01-22 Airtightness testing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPH01187431A true JPH01187431A (en) 1989-07-26

Family

ID=11821303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63013014A Pending JPH01187431A (en) 1988-01-22 1988-01-22 Airtightness testing method for semiconductor device

Country Status (1)

Country Link
JP (1) JPH01187431A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008032658A (en) * 2006-07-31 2008-02-14 Kyocera Kinseki Corp Method and device for inspecting airtightness of package
JP2015203569A (en) * 2014-04-10 2015-11-16 ファナック株式会社 Electronic equipment with airtightness detection means

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008032658A (en) * 2006-07-31 2008-02-14 Kyocera Kinseki Corp Method and device for inspecting airtightness of package
JP2015203569A (en) * 2014-04-10 2015-11-16 ファナック株式会社 Electronic equipment with airtightness detection means

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