JPH01186697A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH01186697A JPH01186697A JP668688A JP668688A JPH01186697A JP H01186697 A JPH01186697 A JP H01186697A JP 668688 A JP668688 A JP 668688A JP 668688 A JP668688 A JP 668688A JP H01186697 A JPH01186697 A JP H01186697A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- bonding
- layer
- metal
- eutectic alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052737 gold Inorganic materials 0.000 claims abstract description 26
- 239000010931 gold Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000006023 eutectic alloy Substances 0.000 claims abstract description 18
- 238000002844 melting Methods 0.000 claims abstract description 10
- 230000008018 melting Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 35
- 239000004020 conductor Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 20
- 238000000465 moulding Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 abstract description 20
- UCHOFYCGAZVYGZ-UHFFFAOYSA-N gold lead Chemical compound [Au].[Pb] UCHOFYCGAZVYGZ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract 2
- 229910045601 alloy Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 40
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011342 resin composition Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、印刷配線板の製法に関し、特に、導体回路
を一旦仮基板上に形成した後、この仮基板上の導体回路
を、配線基板となる絶縁基体側に転写接合して、印刷配
線板を製造する、いわゆる転写式の印刷配線板の製法に
関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a printed wiring board, and in particular, after a conductor circuit is once formed on a temporary substrate, the conductor circuit on the temporary substrate is transferred to a wiring board. The present invention relates to a so-called transfer type printed wiring board manufacturing method in which a printed wiring board is manufactured by transfer bonding to an insulating substrate side.
転写式の印刷配線板の製法を詳しく説明すると、まずス
テンレス板等からなる仮基板上に、レジスト層を形成し
、このレジスト層を回路パターンの丁度裏返しになるパ
ターン形状に除去し、この除去部分に電気めっき等の手
段で導体回路を形成する。つぎに、導体回路にＦＲＰ樹
脂板等からなる絶縁基体を接合した後、仮基板を剥離す
ることによって、導体回路が絶縁基体側に残って、所望
の印刷配線板が製造されるものであり、高密度の微細な
回路パターンが形成できる点で優れた方法である。上記
転写法による印刷配線板は、ｔＣチップを直接印刷配線
板に接続する、チップオン・ボード用の印刷配線板とし
て、有用なものである。なお、上記の転写法の製造工程
で、仮基板を導体回路や絶縁基体から剥離し易くするた
めに、仮基板の表面に予め、銅やニッケル被膜からなる
剥Ｍ層を形成しておくことも、一般的に行われている。To explain in detail the manufacturing method of transfer-type printed wiring boards, first, a resist layer is formed on a temporary substrate made of a stainless steel plate, etc., and this resist layer is removed in a pattern shape that is exactly the reverse of the circuit pattern. A conductor circuit is formed by electroplating or other means. Next, after bonding an insulating substrate made of an FRP resin board or the like to the conductor circuit, the temporary substrate is peeled off, so that the conductor circuit remains on the insulating substrate side, and the desired printed wiring board is manufactured. This method is excellent in that it can form fine circuit patterns with high density. The printed wiring board produced by the above transfer method is useful as a printed wiring board for a chip-on-board in which a tC chip is directly connected to the printed wiring board. In addition, in the manufacturing process of the above-mentioned transfer method, in order to make it easier to peel off the temporary substrate from the conductive circuit or insulating substrate, a peeling M layer made of copper or nickel coating may be formed on the surface of the temporary substrate in advance. , is commonly practiced.
また、印刷配線板において、絶縁基体上に形成された導
体回路の表面に金めつき部分を形成し、金線のワイヤー
ボンディングや金バンブボンディングの際のボンディン
グ性能を良好にすることが行われている。特に、前記チ
ップオン・ボード用印刷配線板では、ＩＣチップ等のイ
ンナー・リード接続を容易に行うために、上記ボンディ
ング性が重要になってくる。金めつき部分を導体回路の
表面に形成するためには、最終工程で、絶縁基体上の導
体回路に、金めつきを施すことが行われており、このと
き９９．９９％純度の金めつきを形成することによって
、ボンディング性能を非常に良好にすることができる。In addition, in printed wiring boards, a gold-plated portion is formed on the surface of a conductor circuit formed on an insulating substrate to improve bonding performance during wire bonding of gold wire and gold bump bonding. There is. In particular, in the chip-on-board printed wiring board, the bonding properties are important in order to easily connect inner leads of IC chips and the like. In order to form a gold-plated part on the surface of a conductor circuit, gold plating is applied to the conductor circuit on an insulating substrate in the final process. By forming a bond, very good bonding performance can be achieved.
しかし、上記最終工程での、所要部分のみへの金めつき
作業は、大変に面倒で技術的にも困難である。そこで、
通常は、仮基板上のレジスト層の除去部分に、まず金め
つき部分を形成した後、その上に導体金属層を形成して
導体回路を構成する方法が採用されている。However, gold plating only on the required parts in the final step is extremely troublesome and technically difficult. Therefore,
Usually, a method is adopted in which a gold-plated part is first formed on the removed part of the resist layer on the temporary substrate, and then a conductive metal layer is formed thereon to form a conductive circuit.
ところが、上記仮基板上へ金めつきを行うと、仮基板金
属または剥離層の金属被膜との界面で、この仮基板金属
または被膜金属を構成する異種金属が、めっきされた金
のなかへ拡散してしまって、金の表層に不純物が含まれ
ることになり、前記したボンディング性能を著しく低下
させる問題がある。特に、剥離層の表面は通常、粗面に
形成して、金めつきの付着性を高めているため、界面に
おける接触面積が大きく、異種金属の拡散が起こり易く
なっている。また、導体回路を絶縁基体へ転写接合する
際には、加熱接合するので、この加熱によっても、異種
金属の拡散は一層促進されることになる。However, when gold plating is performed on the temporary substrate, dissimilar metals constituting the temporary substrate metal or coating metal diffuse into the plated gold at the interface with the temporary substrate metal or the metal coating of the release layer. If this happens, impurities will be included in the gold surface layer, which will significantly reduce the bonding performance described above. In particular, the surface of the release layer is usually formed to be rough to improve adhesion of gold plating, so the contact area at the interface is large and dissimilar metals are likely to diffuse. Further, when the conductor circuit is transferred and bonded to the insulating substrate, the bonding is carried out by heating, so that the diffusion of dissimilar metals is further promoted by this heating.
そこで、この発明の課題は、上記金めっき層に剥離層の
金属が拡散しても、ボンディング性能を低下させること
のない、印刷配線板の製法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a printed wiring board that does not reduce bonding performance even if the metal of the release layer diffuses into the gold plating layer.
上記課題を解決するため、この発明は、前記した転写式
の印刷配線板の製法において、前記剥離層の材料として
、金と共晶合金を作り、その共晶合金の熔融温度がボン
ディング温度よりも低い金属を用いるようにしている。In order to solve the above-mentioned problems, the present invention creates a eutectic alloy with gold as a material for the release layer in the above-described method for manufacturing a transfer type printed wiring board, and the melting temperature of the eutectic alloy is lower than the bonding temperature. I try to use low quality metals.
上記のような製法によれば、剥離層の金属が導体回路の
金めつき層側に拡散しても、この剥離層の金属は金との
共晶合金を作り、その共晶合金の溶融温度がボンディン
グ温度よりも低いものなので、ボンディング時の加熱に
よって、ボンディングする金線やＩＣチップの金リード
等と導体回路の金めつき層との間に、接合力に優れた共
晶合金屑が形成されることになり、両者を極めて良好に
接合することができる。According to the above manufacturing method, even if the metal in the release layer diffuses into the gold-plated layer side of the conductor circuit, the metal in the release layer forms a eutectic alloy with gold, and the melting temperature of the eutectic alloy increases. Since the temperature is lower than the bonding temperature, the heating during bonding forms eutectic alloy debris with excellent bonding strength between the gold wire to be bonded, the gold lead of an IC chip, etc., and the gold plating layer of the conductor circuit. Therefore, the two can be bonded extremely well.
つぎに、この発明の製法を、その一実施例を示す図面を
参照しながら、以下に詳しく説明する。Next, the manufacturing method of the present invention will be explained in detail below with reference to the drawings showing one embodiment thereof.
第１図には、この発明にかかる印刷配線板の製法を、そ
の工程順に模式的に示している。FIG. 1 schematically shows the method for manufacturing a printed wiring board according to the present invention in the order of its steps.
まず、導体回路が形成された仮基板の製造工程について
説明すると、仮基板１ｏの表面に剥離層４０を形成する
〔工程（ａ）〕。仮基板１ｏとｔては、ステンレス坂、
チタン板等の導電性材料からなるものが、後述するめっ
き作業の際に、電極として作用するので好ましい、剥離
層４０としては、後述する絶縁基体に対する剥離性が良
いとともに、金と共晶合金を作り、その共晶合金の溶融
温度が、ボンディング温度よりも低い金属からなるもの
を用いる。First, the manufacturing process of a temporary substrate on which a conductive circuit is formed will be described. A release layer 40 is formed on the surface of the temporary substrate 1o [step (a)]. The temporary substrates 1o and t are stainless steel slopes,
The release layer 40 is preferably made of a conductive material such as a titanium plate because it acts as an electrode during the plating process described below.The release layer 40 is preferably made of a conductive material such as a titanium plate, since it acts as an electrode during the plating process described below. A eutectic alloy made of a metal whose melting temperature is lower than the bonding temperature is used.
ボンディング温度は印刷配線板に装着するＩＣチップ等
の種類や、ボンディング方法あるいは装置等の条件によ
って異なるが、通常のボンディング方法におけるボンデ
ィング温度は４００〜４５０℃程度に設定されるので、
上記共晶合金の溶融温度として、一般的には４００℃以
下のものを使用すればよい。このような条件を満たす金
属としては、Ｓｉ（金との共晶合金の溶融温度＝３７０
℃、以下の金属についても同温度を示す）、Ｇｅ（３５
６℃）、Ｓｎ （２８０℃）等が挙げられるつぎに、仮
基板１０の剥離層４０の上に、所望の回路パターンの、
丁度裏返しになるパターンを有するレジストｊｉｉｆ２
０を形成する〔工程山）〕。レジスト層２０としては、
通常の印刷配線板製造用のフォトレジストその他のレジ
スト材が使用される。The bonding temperature varies depending on the type of IC chip etc. to be attached to the printed wiring board, the bonding method, the conditions of the device, etc., but the bonding temperature in a normal bonding method is set at about 400 to 450 degrees Celsius.
The melting temperature of the eutectic alloy may generally be 400° C. or lower. Metals that meet these conditions include Si (melting temperature of eutectic alloy with gold = 370
℃, the same temperature is also shown for the following metals), Ge (35
Next, on the release layer 40 of the temporary substrate 10, a desired circuit pattern is formed.
Resist jiif2 with a pattern that is exactly reversed
Form 0 [process pile]. As the resist layer 20,
Photoresists and other resist materials commonly used in printed wiring board manufacturing are used.
つぎに、レジストＪＷ２０のない部分２１の仮基板１０
上、すなわち剥離１’１ｉ４０の上に、電気めっき、あ
るいは化学めっき等の手段で、ボンディング層となる金
めつき屓３１を形成する。°さらに、金めつき層３１の
上に、ニッケル！３２および銅Ｍ３３を、順次めっき形
成してレジスト層のない部分２１を埋め、金めっきＮ３
１．ニッケルＮ３２および銅Ｊｉｆ３３で、導体回路３
０を構成する〔工程（Ｃ）〕。Next, the temporary substrate 10 of the part 21 where there is no resist JW 20
On top, that is, on the peeled portion 1'1i40, a gold plating layer 31, which will become a bonding layer, is formed by electroplating, chemical plating, or the like. °Furthermore, on the gold plating layer 31, nickel! 32 and copper M33 are sequentially plated to fill the part 21 where there is no resist layer, and then gold plated N3
1. Conductor circuit 3 with nickel N32 and copper Jif33
0 [Step (C)].
導体回路３０のうち、ニッケル層３２は、金めつき層３
１と銅層３３の間に介在して、金と銅が拡散混合するの
を防止するために有効であるが、ニッケルＪ’１ｆ３２
を形成しない場合もある。銅Ｎ３３は、導体回路３０の
主体となって、電流を流す作用を果たすが、銅Ｍ３３を
ニッケル層やその他の導電材料に置き換えることもでき
る。In the conductor circuit 30, the nickel layer 32 is the gold plating layer 3.
Nickel J'1f32 is interposed between nickel J'1f32 and copper layer 33 and is effective for preventing diffusion and mixing of gold and copper.
may not be formed. Copper N33 serves as the main component of the conductor circuit 30 and functions to conduct current, but copper M33 can also be replaced with a nickel layer or other conductive material.
このようにして導体回路３０が形成された仮基板１０を
用いて、印刷配線板を製造する。まず、導体回路３０の
周囲のレジス）Ｊｔｉｉ２０を完全に除去する。そして
、軟化状態のプリプレグ５０′を適当枚数、導体回路３
０および剥離Ｊ′１ｉ４０の上から仮基板１０上に押し
当て、加熱および加圧することによって、プリプレグ５
０’を導体回路３０および剥ＷＬＭ４０の表面に密着す
るよう変形させた状態で硬化させ、導体回路３０を埋没
させた状態で絶縁基体５０を成形する〔工程（ｄ）、
（ｅ））。絶縁基体５０としては、通常の印刷配線板基
板用材料で形成する。例えば、エポキシ樹脂、フェノー
ル樹脂等を、ガラス繊維布１紙等に含浸させたものなど
、適宜樹脂組成物が、無機および／または有機の楊維質
基材に含浸されたプリプレグ５０′を用いて成形するほ
か、樹脂組成物シートまたはフィルムを用いて成形した
りする。金型を用いた樹脂成形によってもよい。前記樹
脂組成物は、１種類の樹脂のみからなるもののほか、複
数種類の樹脂からなるものでもよい、樹脂には、硬化剤
、その他適宜の添加剤を配合しておくことができ、充虜
材を配合することもできる。A printed wiring board is manufactured using the temporary substrate 10 on which the conductive circuit 30 is formed in this manner. First, the resistor Jtii 20 around the conductor circuit 30 is completely removed. Then, an appropriate number of prepregs 50' in a softened state are attached to the conductor circuit 3.
The prepreg 5
0' is deformed and hardened so as to be in close contact with the surface of the conductor circuit 30 and the peeled WLM 40, and the insulating substrate 50 is formed with the conductor circuit 30 buried therein [step (d),
(e)). The insulating base 50 is made of a common printed wiring board material. For example, a prepreg 50' in which an inorganic and/or organic fiber base material is impregnated with an appropriate resin composition, such as one in which a piece of glass fiber cloth is impregnated with an epoxy resin, a phenol resin, etc., is used to form the material. In addition, it may be molded using a resin composition sheet or film. It may also be formed by resin molding using a mold. The resin composition may be composed of only one type of resin or may be composed of multiple types of resin.The resin may be blended with a curing agent and other appropriate additives, can also be blended.
つぎに、導体回路３０および剥離Ｎ４０が一体化された
絶縁基体５０から、仮基板１０を剥離除去する〔工程（
ｆ）〕。このとき、剥離Ｎ４０は、仮基板１０よりも絶
縁基体５０側への接合力が大きいので、仮基板１０が容
易に剥離できる。最後に、剥離Ｈ４０をエツチング処理
によって除去する〔工程（司〕。Next, the temporary substrate 10 is peeled off and removed from the insulating base 50 in which the conductor circuit 30 and the peeling N40 are integrated [step (
f)]. At this time, in the peeling N40, the bonding force to the insulating base 50 side is greater than that to the temporary substrate 10, so the temporary substrate 10 can be peeled off easily. Finally, the peeling H40 is removed by etching process (step).
以上のような工程を経て、第２図に示すような印刷配線
板が製造される。すなわち、絶縁基体５０に導体回路３
０が埋没形成されていると共に、導体回路３０の表面に
はボンディング層となる金めつき部分３１が形成されて
いるのである。なお、このような製造工程の過程で、剥
ＮＭ４０を構成する金属が隣接する金めつき層３１側に
拡散してもかまわない。Through the steps described above, a printed wiring board as shown in FIG. 2 is manufactured. That is, the conductor circuit 3 is placed on the insulating base 50.
0 is embedded therein, and a gold-plated portion 31 that serves as a bonding layer is formed on the surface of the conductive circuit 30. In addition, during the course of such a manufacturing process, the metal constituting the peeled NM 40 may be diffused to the adjacent gold plating layer 31 side.
上記実施例では、導体回路３０が絶縁基体５０に埋没形
成された、いわゆるフラッシュ・サーキット構造の印刷
配線板の製法について説明したが、導体回路３０全体が
平坦な絶縁基体５０の上に突出形成された構造の、印刷
配線板の製法にも通用できる。その場合、例えば、第１
図（Ｃ）に示す導体回路３０の形成工程の後、レジスト
層２０を剥離除去せずに、絶縁基体５０を接合し、さら
に最終工程で、剥ＭＭ４０を剥離除去した後にレジスト
Ｍ２０を除去するようにすればよい。その他、剥離層４
０の上に導体回路３０の金めっき層３１を形成すること
が必要な方法であれば、既知の各種転写式による印刷配
線板の製法にも通用できるものである。In the above embodiment, a method for manufacturing a printed wiring board having a so-called flash circuit structure in which the conductive circuit 30 is formed embedded in the insulating substrate 50 has been described. It can also be applied to the manufacturing method of printed wiring boards with a similar structure. In that case, for example, the first
After the step of forming the conductor circuit 30 shown in FIG. Just do it. Others, release layer 4
As long as the method requires forming the gold plating layer 31 of the conductor circuit 30 on top of the gold plated layer 31 of the conductor circuit 30, it can be applied to various known transfer methods for producing printed wiring boards.
以上に説明した、この発明は、ボンディング層となる金
めつき部分に接する剥離層の材料として、金と共晶合金
を作り、その共晶合金の溶融温度がボンディング温度よ
りも低い金属からなるものを用いることによって、製造
工程で剥離層の金属が金めつき層側に拡散しても、ボン
ディング状態では、接合力の高い共晶合金層を構成する
ことになり、良好なボンディング性能を発揮できるので
ある。As explained above, this invention is a material for a release layer in contact with a gold-plated part that becomes a bonding layer, in which a eutectic alloy is made with gold, and the eutectic alloy is made of a metal whose melting temperature is lower than the bonding temperature. By using this method, even if the metal in the release layer diffuses into the gold-plated layer during the manufacturing process, it forms a eutectic alloy layer with high bonding strength in the bonding state, achieving good bonding performance. It is.
したがって、従来の製法のように、拡散層の形成による
ボンディング性能の低下はまったく生じず、ボンディン
グ不良の発生を少なくできるとともに、ボンディング作
業の能率向上にも、大きく貢献できることになる。Therefore, unlike conventional manufacturing methods, there is no deterioration in bonding performance due to the formation of a diffusion layer, and it is possible to reduce the occurrence of bonding defects and to greatly contribute to improving the efficiency of bonding work.
第１図はこの発明の製法を工程順に示す断面図、第２図
は製造された印刷配線板の部分拡大断面図である。
１０・・・仮基板 ２０・・・レジストＭ ２１・・
・レジスト層のない部分 ３０・・・導体回路 ３１・
・・金めつき層 ４０・・・剥離Ｆｉ５０・・・絶縁基
体代理人 弁理士 松 本 武 彦FIG. 1 is a cross-sectional view showing the manufacturing method of the present invention in the order of steps, and FIG. 2 is a partially enlarged cross-sectional view of the manufactured printed wiring board. 10... Temporary substrate 20... Resist M 21...
・Part without resist layer 30...Conductor circuit 31・
...Gold plating layer 40...Peeling Fi50...Insulating base agent Patent attorney Takehiko Matsumoto
Claims (1)
層が形成され、同ボンディング層の上に導体金属層から
なる導体回路が形成されている仮基板を用いて、前記導
体回路を埋没させる状態で前記仮基板上に絶縁基体を接
合成形した後、導体回路を一体化した絶縁基体から仮基
板および剥離層を除去することにより、絶縁基体内に埋
没形成された導体回路表面に金めっきによるボンディン
グ層を有する印刷配線板を製造する方法において、前記
剥離層の材料として、金と共晶合金を作り、その共晶合
金の溶融温度がボンディング温度よりも低い金属を用い
ることを特徴とする印刷配線板の製法。1 Using a temporary substrate on which a gold-plated bonding layer is formed via a release layer, and a conductor circuit made of a conductive metal layer is formed on the bonding layer, the conductor circuit is buried. After bonding and molding the insulating substrate onto the temporary substrate, the temporary substrate and release layer are removed from the insulating substrate integrated with the conductor circuit, thereby forming a gold-plated bonding layer on the surface of the conductor circuit embedded in the insulating substrate. A method for manufacturing a printed wiring board comprising: as a material for the release layer, a eutectic alloy is made with gold, and the melting temperature of the eutectic alloy is lower than the bonding temperature. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP668688A JP2514218B2 (en) | 1988-01-14 | 1988-01-14 | Printed wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP668688A JP2514218B2 (en) | 1988-01-14 | 1988-01-14 | Printed wiring board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01186697A true JPH01186697A (en) | 1989-07-26 |
| JP2514218B2 JP2514218B2 (en) | 1996-07-10 |
Family
ID=11645239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP668688A Expired - Lifetime JP2514218B2 (en) | 1988-01-14 | 1988-01-14 | Printed wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2514218B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002050519A (en) * | 2000-08-04 | 2002-02-15 | Sony Corp | High-frequency coil device and its manufacturing method |
| WO2004014114A1 (en) * | 2002-07-31 | 2004-02-12 | Sony Corporation | Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board |
| JP2013538015A (en) * | 2010-09-25 | 2013-10-07 | インテル・コーポレーション | Electrolytic surface finishing with gold or gold palladium in coreless substrate processing |
-
1988
- 1988-01-14 JP JP668688A patent/JP2514218B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002050519A (en) * | 2000-08-04 | 2002-02-15 | Sony Corp | High-frequency coil device and its manufacturing method |
| WO2004014114A1 (en) * | 2002-07-31 | 2004-02-12 | Sony Corporation | Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board |
| CN100452342C (en) * | 2002-07-31 | 2009-01-14 | 索尼株式会社 | Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board |
| US7874066B2 (en) | 2002-07-31 | 2011-01-25 | Sony Corporation | Method of manufacturing a device-incorporated substrate |
| US8146243B2 (en) | 2002-07-31 | 2012-04-03 | Sony Corporation | Method of manufacturing a device incorporated substrate and method of manufacturing a printed circuit board |
| JP2013538015A (en) * | 2010-09-25 | 2013-10-07 | インテル・コーポレーション | Electrolytic surface finishing with gold or gold palladium in coreless substrate processing |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2514218B2 (en) | 1996-07-10 |
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