JPH01186658A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01186658A JPH01186658A JP591488A JP591488A JPH01186658A JP H01186658 A JPH01186658 A JP H01186658A JP 591488 A JP591488 A JP 591488A JP 591488 A JP591488 A JP 591488A JP H01186658 A JPH01186658 A JP H01186658A
- Authority
- JP
- Japan
- Prior art keywords
- silicide
- hydrofluoric acid
- polycrystalline
- semiconductor device
- resistant metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 34
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000005406 washing Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000004811 fluoropolymer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置の構造に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to the structure of a semiconductor device.
（従来の技術） 近年、半導体素子の微細化に伴い、拡散層。(Conventional technology) In recent years, with the miniaturization of semiconductor devices, the diffusion layer.
ゲート電極の低抵抗化を目的としたいわゆるサリサイド
構造のデバイスが用いられてきつつある。Devices with a so-called salicide structure are being used for the purpose of reducing the resistance of gate electrodes.
ここで−例としてサリサイド構造のＳＲＡＭの断面図を
第２図に示す、同図において、ｌはＰ型Ｓｉ基板、２は
素子分離用酸化膜、３はゲート酸化膜、４は多結晶Ｓｉ
ゲート電極、５は低濃度不純物拡散層、６は絶縁膜サイ
ドウオール、７は高濃度Ｎ型不純物拡散層（リース・ト
レイン）、８はＴｉシリサイド、９は層間絶縁膜、１０
はコンタクトホール、１２は高抵抗多結晶Ｓｉである。Here, as an example, a cross-sectional view of an SRAM with a salicide structure is shown in FIG.
Gate electrode, 5 is a low concentration impurity diffusion layer, 6 is an insulating film sidewall, 7 is a high concentration N type impurity diffusion layer (lease train), 8 is Ti silicide, 9 is an interlayer insulation film, 10
1 is a contact hole, and 12 is a high-resistance polycrystalline Si.
しかし、前述の従来技術では、低抵抗シリサイドとして
最も有望なＴｉシリサイドがフッ酸に対して溶解性が高
く、高抵抗多結晶シリコン成長前にフッ酸による前洗浄
が行えず、コンタクトホール形成時にＴｉシリサイド表
面に付着したフッ素系ポリマーあるいは自然酸化膜等の
絶縁膜の除去か困難であり、これがＴｉシリサイドと高
抵抗多結晶Ｓｉの接触不良を引き起こすという問題かあ
った。However, in the above-mentioned conventional technology, Ti silicide, which is most promising as a low-resistance silicide, is highly soluble in hydrofluoric acid, and pre-cleaning with hydrofluoric acid cannot be performed before growing high-resistance polycrystalline silicon. It is difficult to remove insulating films such as fluorine-based polymers or natural oxide films adhering to the silicide surface, and this causes a problem of poor contact between Ti silicide and high-resistance polycrystalline Si.
そこて木発す１は、このような問題点を解決するもので
、その目的はＴｉシリサイドで代表される金属シリサイ
ドと多結晶Ｓｉとの間で良好な接触か得られる半導体装
置を提供することにある。Therefore, Kihata's 1 is intended to solve these problems, and its purpose is to provide a semiconductor device that can obtain good contact between metal silicide, typified by Ti silicide, and polycrystalline Si. be.
（課題を解決するための手段）
本発明はＴｉシリサイド層と多結晶Ｓｔ層が耐フッ酸性
金属あるいは、そのシリサイドを介して接続されている
ことを特徴とする。(Means for Solving the Problems) The present invention is characterized in that the Ti silicide layer and the polycrystalline St layer are connected via a hydrofluoric acid-resistant metal or its silicide.
以下図面により本発明の実施例を詳細に説明する。第１
図は本発明の半導体装置を表わす断面図てあり、同図に
おいてｌはＰ型Ｓｉ基板、２は素子分離用酸化膜、３は
ゲート酸化膜、４は多結晶Ｓｉゲート電極、５は低濃度
Ｎ型不純物拡散層（ＬＤＤ）、６は絶縁膜サイドウオー
ル、７は高濃度Ｎ型不純物拡散層（ソース・ドレイン）
である。Embodiments of the present invention will be described in detail below with reference to the drawings. 1st
The figure is a cross-sectional view showing the semiconductor device of the present invention, in which l is a P-type Si substrate, 2 is an oxide film for element isolation, 3 is a gate oxide film, 4 is a polycrystalline Si gate electrode, and 5 is a low concentration silicon substrate. N-type impurity diffusion layer (LDD), 6 is an insulating film sidewall, 7 is a high concentration N-type impurity diffusion layer (source/drain)
It is.
前記ゲート電極４及びソース・ドレイン７の表面にはＴ
ｉシリサイド８が形成されている０層間絶縁膜９の一部
に設けられたコンタクトホール１０内部にはＭｏシリサ
イド１１が形成され、これ°が前記Ｔｉシリサイド８と
高抵抗多結晶５ｉ１２を接続する役目を果たす。T is formed on the surfaces of the gate electrode 4 and source/drain 7.
Mo silicide 11 is formed inside a contact hole 10 provided in a part of the interlayer insulating film 9 where the i-silicide 8 is formed, and this serves to connect the Ti silicide 8 and the high-resistance polycrystal 5i12. fulfill.
次の本発明の半導体装置の製造方法を簡単に説明する。The following method for manufacturing a semiconductor device according to the present invention will be briefly described.
前記１〜７までは従来の技術を用いて容易に形成される
０次に全面にＴｆをスパッタ法で２００〜８００Ａ形成
した後に６００〜７００℃の温度でハロゲンランプによ
り処理することて前記ゲート電極４及びソース・ドレイ
ン７上のＴｉはＳｉと反応しＴｉシリサイド８が形成さ
れる。In steps 1 to 7 above, the gate electrode is formed by forming Tf of 200 to 800 A on the entire surface of the zero order by sputtering, which can be easily formed using conventional techniques, and then treating it with a halogen lamp at a temperature of 600 to 700°C. 4 and on the source/drain 7 reacts with Si to form Ti silicide 8.
未反応Ｔｉは選択エッチ液により除去し、さらに８００
℃前後の温度でハロゲンランプによりアニールを行う。Unreacted Ti was removed using a selective etchant, and
Annealing is performed using a halogen lamp at a temperature around ℃.
化学的気相成長法により層間絶縁膜９を２０００人前後
形成し、フォトレジストパターンを用い一部エッチング
除去しコンタクトホールｌＯを形成する。Approximately 2,000 interlayer insulating films 9 are formed by chemical vapor deposition, and a portion of the interlayer insulating film 9 is removed by etching using a photoresist pattern to form contact holes 1O.
フォトレジストパターンを除去した後、前記コンタクト
ホールｌＯ形成時に生したフッ素系ポリマーあるいは自
然酸化膜をＡｒスパッタエッチにより取り除きＭｏシリ
サイド１１をスパッタ法にて２００〜８００Ａ堆積させ
る。After removing the photoresist pattern, the fluorine-based polymer or natural oxide film produced when forming the contact hole IO is removed by Ar sputter etching, and Mo silicide 11 is deposited at a thickness of 200 to 800 Å by sputtering.
フォトレジストパターンを用い前記ＭＯシリサイド１１
をコンタクトホール部のみを残すようにエツチングした
後に、高抵抗用多結晶Ｓｉ １２を化学的気相成長法に
より１０００〜２０００Ａ形成し１本発明の半導体装置
の構造が完成する。The MO silicide 11 is formed using a photoresist pattern.
After etching to leave only the contact hole portion, a high-resistance polycrystalline Si film 12 of 1000 to 2000 A is formed by chemical vapor deposition to complete the structure of the semiconductor device of the present invention.
以上述べたように発明によればＴｉシリサイド表面に形
成された自然酸化膜あるいはコンタクトホールドライエ
ッチによるフッ素ポリマーはＡｒスパッタエッチにより
容易に除去され、高抵抗多結晶Ｓｉ形成時にはコンタク
トホール部には、耐フッ酸性に富むＭＯシリサイドが形
成されているため、フッ酸による前洗浄が十分行える。As described above, according to the invention, the natural oxide film formed on the Ti silicide surface or the fluoropolymer formed by contact hole dry etching is easily removed by Ar sputter etching, and when high resistance polycrystalline Si is formed, the contact hole portion is Since MO silicide is formed which is highly resistant to hydrofluoric acid, pre-cleaning with hydrofluoric acid can be performed sufficiently.
これによりＴｉシリサイド、多結晶ＳｉはＭＯシリサイ
ドを介し良好な接触が得られるという効。This has the effect that good contact can be obtained between Ti silicide and polycrystalline Si via MO silicide.
果を有する。have fruit.
以上実施例に基すき具体的に説明したが１本発明は上記
実施例に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもない。Although the present invention has been specifically described above based on the embodiments, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof.
たとえば、耐フッ酸性物質はＭｏシリサイド以外ても、
Ｍｏ、Ｃｏ、Ｎ ｔ、ｗ、ｐｔ等の高融点金属、あるい
はそのシリサイドであフてもよい。For example, hydrofluoric acid-resistant substances other than Mo silicide include
It may be a high melting point metal such as Mo, Co, Nt, w, or pt, or a silicide thereof.
第１図は本発明の半導体装置の実施例を示すＳＲＡＭの
主要断面図、第２図は従来の半導体装置の実施例を示す
ＳＲＡＭの主要断面図。
ｌφ・・Ｐ型Ｓｉ基板
２・・・素子分離用酸化膜
３・・・ゲート酸化膜
４・・・（多結晶Ｓｉ）ゲート電極
５・・・低濃度Ｎ型不純物拡散層（ＬＤＤ）６・・・絶
縁膜サイドウオール
７・・・高濃度Ｎ型不純物拡散層
（ソース・ドレイン）
８・・・Ｔｉシリサイド
９・・・層間絶縁膜
１０・・・コンタクトホール
１１・・・ＭＯシリサイド
１２・・・高抵抗多結晶Ｓｉ
以上
第２図FIG. 1 is a main sectional view of an SRAM showing an embodiment of a semiconductor device of the present invention, and FIG. 2 is a main sectional view of an SRAM showing an embodiment of a conventional semiconductor device. lφ...P-type Si substrate 2...Element isolation oxide film 3...Gate oxide film 4...(Polycrystalline Si) gate electrode 5...Low concentration N-type impurity diffusion layer (LDD) 6... ...Insulating film sidewall 7...High concentration N-type impurity diffusion layer (source/drain) 8...Ti silicide 9...Interlayer insulating film 10...Contact hole 11...MO silicide 12...・High resistance polycrystalline Si Above Figure 2
Claims (3)
属あるいは、該耐フッ酸性金属のシリサイドを介して接
続されていることを特徴とする半導体装置。(1) A semiconductor device characterized in that a Ti silicide layer and a polycrystalline Si layer are connected via a hydrofluoric acid-resistant metal or a silicide of the hydrofluoric acid-resistant metal.
ｔから選ばれてなる第１項記載の半導体装置。(2) The hydrofluoric acid-resistant metal is Mo, Ni, W, Co, P.
2. The semiconductor device according to claim 1, wherein the semiconductor device is selected from t.
たはゲート電極上に形成されていて、前記耐フッ酸性金
属あるいは該耐フッ酸性金属のシリサイドは、層間絶縁
膜に設けられたコンタクトホール内部に形成されている
ことを特徴とする第１項記載の半導体装置。(3) The Ti silicide layer is formed on the source/drain region or the gate electrode, and the hydrofluoric acid-resistant metal or the silicide of the hydrofluoric acid-resistant metal is formed inside the contact hole provided in the interlayer insulating film. 2. The semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP591488A JPH01186658A (en) | 1988-01-14 | 1988-01-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP591488A JPH01186658A (en) | 1988-01-14 | 1988-01-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01186658A true JPH01186658A (en) | 1989-07-26 |
Family
ID=11624164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP591488A Pending JPH01186658A (en) | 1988-01-14 | 1988-01-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01186658A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585308A (en) * | 1993-12-23 | 1996-12-17 | Sgs-Thomson Microelectronics, Inc. | Method for improved pre-metal planarization |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166075A (en) * | 1985-01-17 | 1986-07-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1988
- 1988-01-14 JP JP591488A patent/JPH01186658A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166075A (en) * | 1985-01-17 | 1986-07-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585308A (en) * | 1993-12-23 | 1996-12-17 | Sgs-Thomson Microelectronics, Inc. | Method for improved pre-metal planarization |
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