JP2010272785A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which an insulation defect is avoided by suppressing an insulating film from corroding under the high temperature environment, and to provide a method of manufacturing the same. <P>SOLUTION: On a semiconductor substrate 11, a first insulating film 12 is layered and formed by epitaxial growth and on the first insulating film 12, a thermo-resistant electrode 13 is selectively formed. On an upper part of the electrode 13, an interlayer dielectric 14 is formed with silica glass as a main component and on a surface of the interlayer dielectric 14, an insulating barrier film 15 is formed. On the insulating barrier film 15, a wiring 16 of Al is formed and the insulating barrier film 15 is comprised of a single-layer film, a multilayer film or a mixed film of insulated nitride, carbide and carbide nitride. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device suitable for use at high temperatures and a method for manufacturing the same.

  Since silicon carbide (SiC) semiconductors have a wider forbidden band than other semiconductors such as silicon and gallium arsenide, one of the on-resistance and reverse breakdown voltage of the pn junction is remarkably enhanced, or both characteristics are improved. This is useful for devices that have been raised to some extent compared to conventional devices.

  Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). This document describes a technology of a vertical MOSFET of a power device using a silicon carbide semiconductor. In this semiconductor device, a drift layer is laminated on the surface of a silicon carbide semiconductor substrate by epitaxial growth, a base region is formed in a surface layer portion in the draft layer, and a pair of source regions are formed in the base region. A heat-resistant gate electrode made of polysilicon is formed on each source region through a gate insulating film, and interlayer insulation made of quartz glass (silica glass) with no addition or addition of phosphorus or boron is formed on the gate electrode. An Al (aluminum) wiring electrode is formed through the film.

Japanese Patent No. 4078391

  If such a conventional silicon carbide semiconductor device is placed in a high-temperature environment of about 200 ° C. or higher, there is a risk that a short-circuit will occur in a short time with the wiring electrode formed on the gate electrode. there were. Analyzing these problems in detail, the Al wiring electrode penetrates the interlayer insulating film of the underlying silica glass while corroding severely, penetrates the interlayer insulating film, and reaches the gate electrode. It turned out to be. In other words, the insulation failure at high temperature was caused by the fact that the Al wiring electrode corroded the silica glass interlayer insulating film.

  Such a corrosion phenomenon is not limited to the silicon carbide semiconductor device described above, and an Al wiring electrode and a lower electrode or a conductive region formed on the semiconductor substrate with an interlayer insulating film of silica glass interposed therebetween. It can be said that this is a universal problem that can occur in all semiconductor devices having an opposing three-layer structure.

  Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which prevent the insulation failure by suppressing the corrosion of the insulating film in a high temperature environment. There is to do.

  In order to achieve the above object, the means for solving the problems of the present invention includes an insulating film and a metal wiring through a barrier film composed of a single layer film or a multilayer film of insulating nitride, carbide, nitride carbide. Are arranged and formed.

  According to the present invention, since the insulating film and the metal wiring are separated by the barrier film made of insulating nitride, carbide, single-layer film or multilayer film of nitrided carbide, the corrosion of the insulating film by the metal wiring. Can be suppressed, and poor insulation can be avoided.

It is sectional drawing which shows the principal part structure of the semiconductor device which concerns on Example 1 of this invention. It is a figure which shows the defect characteristic under the high temperature of the semiconductor device which concerns on Example 1 of this invention, and the conventional semiconductor device. It is sectional drawing which shows the principal part structure of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing which shows the principal part structure of the semiconductor device which concerns on Example 3 of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing which shows the principal part structure of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 5 of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 5 of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 5 of this invention.

  Embodiments for carrying out the present invention will be described below with reference to the drawings. The drawings referred to in the description of the following embodiments are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from those of the actual apparatus. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings. Furthermore, in each figure shown below, the thing of the same code | symbol has the same function, and in order to avoid redundancy after describing once, in principle, description is abbreviate | omitted or simplified.

  The technical idea of the present invention is that the silica glass interlayer insulating film in contact with the Al wiring is corroded at a high temperature of about 200 ° C. or more to short-circuit with other wirings, electrodes, or conductive layers formed in the vicinity of the wiring. Therefore, when the present invention is described using an actual semiconductor device (device) that includes a large number of parts that are not related to the basis of the technical idea of the present invention, it becomes redundant. In order to avoid this, in Examples 1 to 4 described below, the semiconductor device of the present invention will be described with a simplified structure, and the actual device of the present invention will be described. Application will be described in Example 5.

  FIG. 1 is a cross-sectional view showing the main configuration of a semiconductor device according to Embodiment 1 of the present invention. In the semiconductor device of Example 1 shown in FIG. 1, a first insulating film 12 is laminated on a semiconductor substrate 11 such as silicon or silicon carbide by epitaxial growth. The first insulating film 12 corresponds to a gate insulating film or a field insulating film in an actual device. A heat-resistant electrode 13 is selectively formed on the first insulating film 12. The electrode 13 includes a gate electrode such as a MOS device in connection with the prior art described above, but the present invention is not limited to this. That is, a conductive material that does not react with silica glass described later is selected for the electrode 13. For example, poly Si (silicon) to which impurities are added, polycide obtained by siliciding a part or all of poly Si, or a refractory metal such as Mo or W.

  Above the electrode 13, an Al (aluminum) wiring 16 that is not connected to the electrode 13 through an interlayer insulating film 14 and an insulating barrier film 15 described later is formed. The wiring 16 may be pure Al or Al to which Si or Cu is added. A barrier metal such as Ti, TiN, or TaN is provided below the wiring 16 to suppress Al spike phenomenon in a contact region (bonding surface) where the wiring 16 and another region are bonded. Also good. Hereinafter, those including the barrier metal are referred to as Al wiring.

An interlayer insulating film 14 mainly composed of silica glass is sandwiched between the wiring 16 and the electrode 13. This interlayer insulating film 14 is a pure (no additive) silica glass (USG) film, a PSG film in which phosphorus P is added to an additiveless silica glass, a BSG film in which boron B is added, and an FSG in which fluorine F is added. It is formed of a film, a CSG film to which C is added, a mixed film or a laminated film thereof. Note that the interlayer insulating film 14 is generally formed by thermal oxidation (with a thickness of several hundreds of nanometers or more) when a function of insulating the electrode 13 and the wiring 16 not only electrically but also electrostatically is required. It is formed of a much sparse film (in order to lower the dielectric constant) compared to a SiO ₂ ) film or the like.

  The insulating barrier film 15 is a characteristic component of the present invention, and is formed on the interlayer insulating film 14. The insulating barrier film 15 is formed of an insulator thicker than about 20 nm and thinner than the interlayer insulating film 14, and a constituent material is selected so as to have at least the following functions.

(Function 1) Blocks the diffusion of Al constituting the wiring 16 (to the interlayer insulating film 14 side).

(Function 2) Preventing outward diffusion (to the wiring 16 side) of Si constituting the electrode 13.

(Function 3) Simultaneously inhibits the chemical reaction with Al constituting the wiring 16 in contact with the insulating barrier film 15 and the silica glass constituting the interlayer insulating film 14.

(Function 4) It has a strong (at least sufficient to ensure reliability as a device) bonding strength to both Al constituting the wiring 16 and silica glass constituting the interlayer insulating film 14.

  When the barrier metal is formed under the wiring 16 as described above, the insulating barrier film 15 functions to prevent inward diffusion of elements constituting the barrier metal, and the barrier metal and the interlayer insulating film 14. It also has a function of preventing a chemical reaction between the two.

  Examples of suitable materials for the insulating barrier film 15 include insulating nitride, carbide, nitrided carbide single-layer film, multilayer film, and mixed film. Examples of such a material include a SiC film, a SiN film, a GeC film, a GeN film, and an AlN film. In addition, if oxygen is contained in a component constituting the insulating barrier film 15, corrosion is likely to occur rapidly, so it is necessary to prevent oxygen from being contained.

  Next, a manufacturing method for obtaining the structure shown in FIG. 1 will be described.

First, the first insulating film 12 is grown on the surface of the semiconductor substrate 11 sufficiently cleaned with a known cleaning solution by a predetermined method, for example, thermal oxidation. Subsequently, after forming a heat resistant electrode film on the entire surface of the first insulating film 12, the electrode film is patterned by known photolithography and etching to form the heat resistant electrode 13. For example, when the low resistance poly-Si is an electrode film, the poly-Si growth is performed by a low pressure CVD method, the doping is performed by solid thermal diffusion using POCl ₃ as a raw material, and the etching (patterning) is performed by a reactive ion etching method.

  Thereafter, an interlayer insulating film 14 mainly composed of silica glass is formed on the entire surface of the semiconductor substrate 11 by an atmospheric pressure CVD (chemical vapor deposition) method or a plasma CVD method.

  Next, an amorphous, dense and low-stress insulating barrier film 15 is grown on the upper surface of the interlayer insulating film 14. As this growth method, for example, a plasma CVD method capable of growing at a temperature of about 600 ° C. or lower, an MO (organic metal) CVD method, an ALD (atomic layer deposition) method, or a photoexcited CVD method is desirable.

  On the other hand, the insulating barrier film 15 grown at about 600 ° C. or more becomes a highly stressed film, which causes the interlayer insulating film 14 to crack or peels off from the Al wiring 16 or the interlayer insulating film 14. It is hard to say that it is suitable for the purpose of the present invention. Therefore, specific methods for growing several insulating barrier film materials are described. In the case of SiN, plasma CVD using silane and nitrogen or ammonia as source gases, and in the case of SiC, trimethylsilane or tetramethylsilane It can be formed by a plasma CVD method using He as a source gas.

  Finally, an Al wiring film is sputter-deposited on the entire surface of the substrate, and then patterned by well-known photolithography and reactive ion etching to form an Al wiring 16, thereby completing the semiconductor device having the configuration shown in FIG.

  Next, functions and effects of the semiconductor device having the above-described configuration will be described.

  First, by providing an insulating barrier film 15 having a function of preventing a chemical reaction between Al and silica glass (the above function 3) between the wiring 16 and the interlayer insulating film 14, the Al wiring 16 and the interlayer insulation are provided. A situation in which the film 14 reacts violently at high temperatures can be avoided. Therefore, the reaction between the wiring 16 and the interlayer insulating film 14 is caused by the reaction between Al atoms diffused inward from the wiring 16 through the insulating barrier film 15 and the interlayer insulating film 14 or Si atoms diffused outward from the interlayer insulating film 14. The reaction with the wiring 16 is limited.

  On the other hand, as described above, the insulating barrier film 15 has both the function of preventing the inward diffusion of Al (the function 1) and the function of preventing the outward diffusion of Si (the function 2). The diffusion reaction can be extremely suppressed in terms of reaction rate. As a result, the wiring 16 is prevented from corroding the interlayer insulating film 14 in a short time, and a short circuit between the wiring 16 and the electrode 13 can be prevented. Furthermore, since the insulating barrier film 15 has strong bonding properties to both the wiring 16 and the interlayer insulating film 14, a new peeling defect occurs when the insulating barrier film 15 is interposed between the wiring 16 and the interlayer insulating film 14. Fear can also be avoided. Further, since the insulating barrier film 15 can be generated as a low stress film by optimizing the film forming method, it is possible to avoid the possibility of causing damage such as cracks in the lower interlayer insulating film 14.

  Hereinafter, specific characteristic effects of the semiconductor device having the above-described configuration will be described based on experimental results.

  First, the semiconductor device having the configuration shown in FIG. 1 was actually manufactured and stored in an inert atmosphere at about 500 ° C., and the occurrence of a short circuit between the wiring 16 and the electrode 13 was observed. The specifications of the manufactured device are as follows.

Electrode 13: n ⁺ type poly-Si electrode interlayer insulating film 14: laminated film of PSG and USG insulating barrier film 15: plasma SiN film or plasma SiC film (thickness 150 nm)
Wiring 16: Sputtered Al film (Si 1% added, with barrier metal)
The total thickness of the interlayer insulating film 14 and the insulating barrier film 15 is 1 μm. For comparison, a conventional semiconductor device without the insulating barrier film 15 and the barrier metal and a conventional semiconductor device without the insulating barrier film and only the barrier metal were also manufactured.

  FIG. 2 shows the result of the reliability test, and shows the relationship between the storage time (horizontal axis) at about 500 ° C. and the cumulative short-circuit failure rate (vertical axis). The time axis on the horizontal axis is expressed logarithmically. As apparent from FIG. 2, the insulating barrier film 15 of the plasma SiN film (denoted as “p-SiN” in FIG. 2) and the plasma SiC film (“p-SiC” in FIG. 2) employed in this reliability test. It can be seen that the insulating barrier film 15 (denoted as “)” has achieved a long life of more than three and a half digits and over 1000 hours compared to the prior art (denoted as “none” in FIG. 2).

  Further, FIG. 2 shows that when the barrier metal is provided on the wiring 16 (indicated as “BM” in FIG. 2), there is a certain effect compared to the case where no barrier metal is provided. However, it can be seen that the effect is only an improvement that extends the lifetime to several tens of hours, and is far inferior to the case where the insulating barrier film 15 is provided.

  Furthermore, the SiC film has a cumulative failure rate of about 4200 hours at about 50%, whereas the SiN film has a storage time of about half (1/2) that of the SiC film, and the insulating barrier film 15 It can be seen that the SiC film is relatively superior to the SiN film.

  FIG. 3 is a cross-sectional view showing the main configuration of a semiconductor device according to Embodiment 2 of the present invention. In the semiconductor device of Example 2 shown in FIG. 3, a p-type or n-type conductive region 31 is selectively formed in a surface layer portion in a semiconductor substrate 11 such as silicon or silicon carbide. An interlayer insulating film 14 similar to that of the first embodiment is formed on the semiconductor substrate 11 on which the conductive region 31 is formed, and an insulating barrier film 15 similar to that of the first embodiment is formed on the interlayer insulating film 14. A wiring 16 of Al similar to that of the first embodiment is laminated through the above.

  As a manufacturing method having such a configuration, first, a p-type or n-type impurity is selectively ion-implanted into the semiconductor substrate 11 and the implanted ions are activated to form the conductive region 31. Thereafter, by applying the same process as in the first embodiment, the semiconductor device having the configuration shown in FIG. 3 can be obtained.

  In such a configuration, the insulating barrier film 15 having the same function as that of the first embodiment is provided between the wiring 16 and the interlayer insulating film 14 as in the first embodiment. 16 is prevented from corroding the interlayer insulating film 14 made of silica glass in a short time, and a short circuit between the wiring 16 and the lower conductive region 31 can be avoided.

  FIG. 4 is a diagram showing the main configuration of a semiconductor device according to Embodiment 3 of the present invention. The third embodiment is a configuration frequently used for power transistors and the like. In the configuration including both the configurations of the first embodiment and the second embodiment, the electrode 13 and the wiring 16 are the same as those of the first embodiment. In addition to avoiding this short circuit, the same conductive region 31 and Al wiring 16 as in the second embodiment are electrically connected through the contact hole 41.

  In such a configuration, the interlayer insulating film 14 facing the side wall of the contact hole 41 in order to block the contact between the wiring 16 and the interlayer insulating film 14 by the insulating barrier film 15, which is a characteristic technical idea of the present invention. An insulating barrier film 15 is also disposed on the side surface of the first electrode. Thereby, corrosion from the side surface side of the interlayer insulating film 14 of the Al wiring 16 can also be suppressed.

  Therefore, the insulating barrier film 15 is formed on the side wall of the contact hole 41. However, when the contact hole 41 has a sufficiently large area, the insulating barrier film 15 is formed after the contact hole 41 is formed in the interlayer insulating film. Is formed on the entire surface, and the insulating barrier film 15 at the bottom of the contact hole 41 is removed by well-known photolithography and etching to obtain a desired covering structure. However, in an ordinary semiconductor device, the opening area of the contact hole is generally fine, and it is difficult to form an insulating barrier film on the side wall of the contact hole by the above process.

  Therefore, in Example 3, the manufacturing method described with reference to the process cross-sectional views shown in FIGS. 5A to 5D below is adopted, so that the opening area is formed on the side wall of the contact hole having a fine opening area. It is possible to easily form a coating on the insulating barrier film.

  First, after the conductive region 31 is selectively formed in the surface layer portion in the semiconductor substrate 11 as described in the second embodiment, the first insulating film 12 is processed in the same manner as described in the first embodiment. Then, the heat-resistant electrode 13 and the interlayer insulating film 14 mainly composed of silica glass are sequentially formed (FIG. 5A).

  Subsequently, a primary insulating barrier film 15a is formed on the entire surface of the device, and then a temporary silica glass film 51 is laminated on the primary insulating barrier film 15a. The specification and film formation method of the primary insulating barrier film 15a are the same as those of the insulating barrier film 15 described in the first embodiment. The temporary silica glass film 51 may be omitted (FIG. 5B).

  Next, by using well-known photolithography and reactive ion etching (RIE) or electromagnetic inductively coupled plasma etching (ICP)), the primary insulating barrier film 15a on the conductive region 31 and the temporary silica glass film 51 are formed. The interlayer insulating film 14 is selectively removed to form a contact hole 41. Thereafter, a secondary insulating barrier film 15b is formed on the entire surface of the device, thereby forming the secondary insulating barrier film 15b on the side wall and bottom of the contact hole 41. The specifications and deposition method of the secondary insulating barrier film 15b are the same as those of the insulating barrier film 15 described in the first embodiment, but the primary insulating barrier film 15a and the secondary insulating barrier film 15b are not necessarily the same. It does not have to be a material (FIG. 5C).

  Subsequently, the secondary insulating barrier film 15b is etched back by anisotropic etching such as RIE or ICP, and the etching is terminated when the silica glass film 51 is exposed. Thereafter, the semiconductor substrate 11 is immersed in a buffered hydrofluoric acid solution. Then, the silica glass film 51 is removed. By performing this etch back, the primary insulating barrier film 15a remains on the upper surface of the interlayer insulating film 14, the secondary insulating barrier film 15b remains on the side wall of the contact hole 41, and both insulating barrier films are integrated. An insulating barrier film 15 is formed (FIG. 5D).

  In the above process, when the etch back process reaches the transient silica glass film 51 and the silica glass film 51 is exposed, oxygen is contained in the etching exhaust gas. By monitoring the oxygen in the etching exhaust gas, The end point of etch back can be detected.

  Finally, after Al is sputter-deposited on the entire surface, the Al 16 is patterned by well-known photolithography and RIE to selectively form the wiring 16, thereby completing the semiconductor device shown in FIG.

  As described above, in Example 3 described above, even in the device having a structure in which the interlayer insulating film 14 and the Al wiring face each other on the side wall of the contact hole 41, the contact hole 41 having a relatively small opening area is used. The insulating barrier film 15 can be formed on the side wall, and the same effect as in the first and second embodiments can be obtained.

  FIG. 6 is a sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. A feature of the fourth embodiment resides in that the technical idea of the present invention described in the first and second embodiments is applied to a device having an Al multilayer wiring.

  6, similarly to the configuration shown in FIG. 1, a first insulating film 12, a heat-resistant electrode 13, a first interlayer insulating film (corresponding to the interlayer insulating film 14 in FIG. 1) 61, A first insulating barrier film (corresponding to the insulating barrier film 15 in FIG. 1) 62 and a first Al wiring (corresponding to the wiring 16 in FIG. 1) 63 are formed by the same method as in the first embodiment.

  Further, in the fourth embodiment, a second insulating barrier film 64 is laminated on the first insulating barrier film 62 and the Al first wiring 63, and a second interlayer insulating film 65 is laminated on the second insulating barrier film 64. A third insulating barrier film 66 is formed on the second interlayer insulating film 65; an Al second wiring 67 is selectively stacked on the third insulating barrier film 66; and an Al two-layer wiring structure is formed. It has.

  That is, the first insulating barrier film 62 is interposed between the first interlayer insulating film 61 and the first wiring 63, and the second insulating barrier film 64 is interposed between the first wiring 63 and the second interlayer insulating film 65. The third insulating barrier film 66 is interposed between the second interlayer insulating film 65 and the second wiring 67.

  The first interlayer insulating film 61 and the second interlayer insulating film 65 are configured in the same manner as the interlayer insulating film 14 of the first embodiment and have the same functions. The first insulating barrier film 62 and the second insulating barrier film 64 and the third insulating barrier film 66 are configured in the same manner as the insulating barrier film 15 of the first embodiment and have the same functions.

  Next, a method for manufacturing the apparatus shown in FIG. 6 will be described.

  First, the same configuration as that shown in FIG. 1 is formed by the same method as described in the first embodiment. Thus, the process until the first Al wiring 63 is formed on the first insulating barrier film 62 is completed.

  Subsequently, a second insulating barrier film 64, a second interlayer insulating film 65, and a third insulating barrier film 66 are sequentially formed on the entire surface of the device. The formation method and specifications of the second interlayer insulating film 65 are the same as those of the first interlayer insulating film 61.

  Finally, Al is sputter-deposited on the entire surface of the device, and then patterned by standard photolithography and reactive ion etching to selectively form the second Al wiring 67, thereby completing the device having the structure shown in FIG.

  As a growth method of the second insulating barrier film 64 and the third insulating barrier film 66, a plasma CVD method, an MO (organometallic) CVD method, which can be grown at a temperature of at least about 500 ° C., preferably about 400 ° C., ALD (atomic layer deposition) method or photoexcited CVD method is preferable. Further, since the melting point temperature of Al (containing 1% Si) is around 560 ° C., the Al first wiring 63 is melted, softened or deteriorated at a process temperature of about 500 ° C. or higher. There is a risk of Therefore, a specific method for growing several insulating barrier film materials will be described. The SiN film can be formed by plasma CVD using silane and nitrogen or ammonia as source gases, and the SiC film can be formed by trimethylsilane or tetramethyl. It can be formed by a plasma CVD method using silane and He as source gases. These deposition methods can form a film at a growth temperature of about 400 ° C. or less.

  As described above, even in a semiconductor device having a structure in which the Al wiring and the interlayer insulating film are multi-layered and each of the multi-layered wirings is insulated and separated by the interlayer insulating film, the interlayer wiring is provided between the interlayer insulating film and the Al wiring. By interposing the insulating barrier film employed in the present invention, it is possible to suppress defects such as Al corroding the interlayer insulating film and short-circuiting between opposing Al wirings via the corroded interlayer insulating film. It is possible to obtain the same effect as in the first and second embodiments.

  FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to Example 5 of the present invention. In the fifth embodiment, the technical idea of the present invention described in the first to fourth embodiments described above is formed on a silicon carbide semiconductor substrate by paying attention to the constituent elements of the Al wiring and the interlayer insulating film mainly composed of silica glass. This is an embodiment applied to a power semiconductor device (vertical MOSFET (metal-oxide-semiconductor structure field effect transistor)).

  FIG. 7 shows a main configuration of a MOSFET unit cell 700. The unit cell represents the minimum unit of the element region. In the power element, a large number of unit cells in the element region are arranged in parallel in the vertical and horizontal directions to increase the current. In the following description, reference numeral 700 is used to mean both an element region and a unit cell.

A silicon carbide semiconductor substrate (SiC substrate) 701 is an n ⁺ type (0001) Si-plane single crystal 4H—SiC substrate to which impurity nitrogen is added at about 1 × 10 ¹⁹ / cm ³ . As the SiC substrate 701, in addition to 4H, any crystal system such as 6H, 3C, and 15R (H is hexagonal, C is cubic, and R is rhombohedral) can be used. On one main surface (upper surface side in the drawing) of SiC substrate 701, an n ⁻ type epitaxial layer 702 having a thickness of about 10 μm and doped with about 1 × 10 ¹⁶ / cm ^{3 of} impurity nitrogen is formed by homoepitaxial growth. .

  On the surface layer of the epitaxial layer 702, p-type base regions 703a and 703b to which p-type impurities are added higher than the impurity concentration of the epitaxial layer 702 are selectively formed with a predetermined distance therebetween.

On the surface layers of the base regions 703a and 703b, n ⁺ -type source regions (high-concentration impurity regions) 704a and 704b, which are shallower than the base regions 703a and 703b and doped with high-concentration impurities, are formed. P ⁺ -type base regions 705a and 705b, which are part of the base regions 703a and 703b and in which the p-type impurities are added to the external surface layer of the source regions 704a and 704b at a higher concentration than the base regions 703a and 703b. Is formed. The impurity concentrations of the n ⁻ type epitaxial layer 702, the p type base regions 703a and 703b, and the n ⁺ type source regions 704a and 704b are set to increase in this order.

  A gate electrode 707 (corresponding to the heat-resistant electrode 13 in FIG. 1) made of conductive polycrystalline silicon is provided on one main surface side of the SiC substrate 701 on which each of the impurity regions is formed via a gate insulating film 706. Selectively formed. A polycrystalline silicon oxide film 708 is formed on the side and top surfaces of the gate electrode 707, and the gate electrode 707 is covered with the polycrystalline silicon oxide film 708. On the gate insulating film 706 and the polycrystalline silicon oxide film 708, an interlayer insulating film 709 (corresponding to the interlayer insulating film 14 in FIG. 1) mainly composed of silica glass is formed.

Further, on one main surface side of the SiC substrate 701, source windows 710a and 710b (contact holes 41 in FIG. 4) penetrating the n ⁺ type source regions 704a and 704b and the p ⁺ type base regions 705a and 705b are formed. Is equivalent). Source electrodes 711a and 711b made of Ni ₂ Si are formed on the bottoms of the source windows 710a and 710b. Each of the source electrodes 711a and 711b has a function of simultaneously providing ohmic contact to different polar regions of the n ⁺ type source regions 704a and 704b and the p ⁺ type base regions 705a and 705b.

Further, n ⁺ -type source regions 704a and 704b and p ⁺ -type base regions 705a and 705b are provided on one main surface side of the device via source electrodes 711a and 711b on an external circuit or the same substrate. An Al (containing 1% Si) wiring 712 (corresponding to the Al wiring 16 in FIGS. 1, 3 and 4) for connection to other circuit elements is formed. Although not shown in the drawing, a part of the wiring 712 has a lower portion of the wiring, such as Ta / TaN, in order to prevent alloying of Al of the wiring 712 and Ni ₂ Si of the source electrodes 711a and 711b. An appropriate barrier metal may be formed.

  In addition, an insulating barrier film is formed on the surface of the interlayer insulating film 709 where the wiring 712 and the interlayer insulating film 709 / gate insulating film 706 are adjacent to each other and on the sidewalls of the interlayer insulating film 709 / gate insulating film 706 on the source window 710a, 710b side. 713 (corresponding to the insulating barrier film 15 in FIGS. 1, 3 and 4) is formed. That is, the insulating barrier film 713 is interposed between the interlayer insulating film 709 and the Al wiring 712, and the interlayer insulating film 709 and the wiring 712 are separated by the insulating barrier film 713.

On the other hand, a drain electrode 714 made of Ni ₂ Si for providing an ohmic contact to the drain of the MOSFET cell is laminated on the other main surface (lower surface in FIG. 7) of the SiC substrate 701. On the drain electrode 714, a mounting electrode 715 made of, for example, a Ti / Ni / Ag laminated film is laminated and formed for the purpose of smooth die bonding.

  With this configuration, the silicon carbide semiconductor device functions as a field effect transistor having a vertical metal-oxide-semiconductor structure.

  In such a MOSFET, since the interlayer insulating film 709 mainly composed of silica glass is completely isolated from the wiring 712 by the insulating barrier film 713, the same effects as those obtained in the first to fourth embodiments are obtained. Can be obtained by MOSFET. That is, the problem that the interlayer insulating film 709 corrodes the wiring 712 in a short time at a high temperature exceeding 200 ° C. and the wiring 712 and the gate electrode 707 are short-circuited can be avoided.

  Next, a method for manufacturing the device shown in FIG. 7 will be described with reference to the process cross-sectional views of FIGS. 8A and 8B.

First, an n ⁺ type 4H—SiC substrate 701 which is a silicon carbide substrate on which an n ⁻ type epitaxial layer 702 having a thickness of about 10 μm is homoepitaxially grown is prepared on one main surface side. A p-type impurity or an n-type impurity is selectively implanted into the epitaxial layer 702 by the described high-temperature selective ion implantation method, and p-type base regions 703a and 703b, n ⁺ -type source regions 704a and 704b, and p ⁺ -type. The precursor regions to be the base regions 705a and 705b are sequentially formed. An example of ion implantation conditions for each region is as follows.

Ion implantation conditions for p-type base region Impurities Al ⁺ ions Substrate temperature 750 ° C.
Acceleration voltage / dose amount 360 keV / 5 × 10 ¹³ / cm ²
Ion implantation conditions for p ⁺ type base region Ion species Al ⁺
Injection temperature 750 ° C
Acceleration voltage / Dose amount 30 KeV / 1.0 × 10 ¹⁵ / cm ²
50 KeV / 1.0 × 10 ¹⁵ / cm ²
70 KeV / 2.0 × 10 ¹⁵ / cm ²
100 KeV / 3.0 × 10 ¹⁵ / cm ²
I ⁺ implantation conditions for n ⁺ -type source region Ion species P ⁺ (phosphorus)
Injection temperature 500 ° C
Acceleration voltage / Dose amount 40 KeV / 5.0 × 10 ¹⁴ / cm ²
70 KeV / 6.0 × 10 ¹⁴ / cm ²
100 KeV / 1.0 × 10 ¹⁵ / cm ²
160 KeV / 2.0 × 10 ¹⁵ / cm ²
After the high temperature ion implantation is completed, the mask formed at the time of ion implantation is removed by immersion in a buffered hydrofluoric acid solution, and the SiC substrate 701 is sufficiently washed and dried. After that, the impurities in the respective precursor regions (impurity regions) formed by the previous ion implantation by activation annealing are activated at once, and p-type base regions 703a and 703b, n ⁺ -type source regions 704a and 704b, P ⁺ -type base regions 705a and 705b are respectively formed (FIG. 8-A (a)).

  The implanted ions are activated on a high-purity carbon susceptor so that one main surface side of the SiC substrate 701 faces upward (the other main surface side of the SiC substrate 701 is in contact with the carbon susceptor). For example, in a high-purity inert gas atmosphere such as Ar or a high-purity inert gas atmosphere slightly containing silane, the heat treatment is performed at a temperature of about 1600 ° C. or more for about 1 to several minutes. To do.

  Next, after the SiC substrate 701 after the activation of the implanted ions in the previous step is sufficiently washed and dried, sacrificial oxidation is performed in a dry oxygen atmosphere at about 1100 ° C., and a thermal oxide film is formed on the surface of the SiC substrate 701. Is then immersed in a buffered hydrofluoric acid solution to remove the thermal oxide film on the surface of the SiC substrate 701 (sacrificial oxidation treatment). The thickness of the thermal oxide film is less than 50 nm, preferably 5 nm to 20 nm. By this sacrificial oxidation treatment, a contaminated layer or irregular layer that causes a device failure is appropriately removed from the surface of the SiC substrate 701.

Subsequently, the SiC substrate 701 is sufficiently cleaned, and then thermally oxidized in a dry oxygen atmosphere at about 1100 ° C. to grow and form a thermal oxide film having a thickness of about 5 nm to 20 nm on the entire front and back main surfaces of the SiC substrate 701. To do. Further, by depositing a SiO ₂ film having a thickness of about 600 nm on one main surface on the surface side of the SiC substrate 701 by using atmospheric pressure chemical vapor deposition (APCVD) or the like, A field insulating film 802 having a two-layer structure made of an APCVD-SiO ₂ film is formed. By this thermal oxidation, a transient thermal oxide film 801 having a thickness of about 100 nm or more is also formed on the other main surface on the back surface side of the SiC substrate 701 (FIG. 8-A (b)). Note that the thermal oxide film under the field insulating film 802 has an effect of stabilizing the interface between the field insulating film 802 and the surface of the SiC substrate 701, improving the withstand voltage of the vertical device, and suppressing variations thereof.

  Next, the field insulating film 802 on the surface of the SiC substrate 701 is selectively etched and removed by using well-known photolithography and wet etching, or the above-described etching using both dry and wet, so that the field region and the field insulating film are removed. An element region 700 shown in FIG. 7 from which 802 has been removed is formed. The transient thermal oxide film 801 is removed by wet etching when the field insulating film 802 is removed. The structure of the element region 700 at this time is the same as that shown in FIG. 8A (a), but the field insulating film 802 is present in portions other than the element region 700, and the structure of the entire SiC substrate 701 is different.

Subsequently, the SiC substrate 701 is sufficiently cleaned again, and the SiC substrate 701 is made into a buffered hydrofluoric acid solution in order to remove the chemical oxide film (SiO ₂ ) generated on the surface of the element region 700 in the final stage of the cleaning. Immerse for about 10 seconds. Thereafter, the buffered hydrofluoric acid solution is completely rinsed off with ultrapure water, dried, and immediately thermally oxidized to grow and form a gate insulating film 706 having a thickness of, for example, about 40 nm on the surface of the SiC substrate 701 in the element region 700. During the formation of the gate insulating film, a temporary thermal oxide film 803 is grown again on the main surface on the back surface side of the SiC substrate 701. The conditions for gate oxidation are not limited to this, and may be dry oxidation at about 1160 ° C., for example. What is important here is that the thermal oxidation temperature is set higher than any heat treatment temperature of all subsequent processes below. Although a single-layer thermal oxide film is used here as the gate insulating film 706, a composite insulating film such as an ONO film described in FIG. 14 of Japanese Patent Application Laid-Open No. 2006-74024 is used. Also good.

Subsequently, a polycrystal having a thickness of about 300 nm to 400 nm is formed by a low pressure CVD method (growth temperature of about 600 ° C. to 700 ° C.) using a silane material on the entire main surface on the front side and the main surface on the back side of the SiC substrate 701. A silicon film 804 is formed. Thereafter, P (phosphorus) is added to the polycrystalline silicon film 804 by a known thermal diffusion method (processing temperature: about 900 ° C. to 950 ° C.) using phosphorus chlorate (POCl ₃ ) and oxygen to impart conductivity. Further Subsequently, the surface of the SiC substrate 701 is coated with a photoresist mask material, photolithography, and using a reactive ion etching (RIE) and an etchant of _C 2 _{F 6} and oxygen, the surface of the SiC substrate 701 The side polycrystalline silicon film 804 is selectively removed to form a gate electrode 707 (FIG. 8-A (c)).

  Next, after removing the mask at the time of forming the gate electrode and thoroughly cleaning the etched SiC substrate 701, it is thermally oxidized in a dry oxygen atmosphere at about 900 ° C., and the main electrode on the back side of the gate electrode 707 and the SiC substrate 701 A polycrystalline silicon oxide film 708 is formed on the surface of the surface polycrystalline silicon film 804.

Subsequently, an interlayer insulating film 709 mainly composed of silica glass is deposited on the entire main surface on the surface side of the SiC substrate 701. As the interlayer insulating film 709, approximately 1μm about thick SiO ₂ film (NSG film) silane and oxygen were formed by APCVD as a raw material, or phosphosilicate glass doped with phosphorus (PSG) film, further boron thereto A boron phosphosilicate glass (BPSG) film to which is added is suitable, but is not limited thereto.

  Subsequently, after protecting the surface of the SiC substrate 701 with a resist material, the polycrystalline silicon oxide film 708 on the back surface of the SiC substrate 701 is removed with a buffered hydrofluoric acid solution, and the polycrystalline silicon film 804 is removed by well-known dry etching. Thereafter, the resist material is removed (FIG. 8-B (d)).

  Next, the source window 710a, 710b and the gate window (outside the element region 700) are formed in the interlayer insulating film 709 and the gate insulating film 706 on the main surface of the SiC substrate 701 by well-known photolithography, RIE, and wet combined etching. (Not shown) is opened. At this time, the thermal oxide film 803 on the main surface on the back surface side of the SiC substrate 701 is also removed at the same time.

  Thereafter, the SiC substrate 701 is sufficiently washed with ultrapure water and dried, and immediately applied to both the main surface on the surface side and the main surface on the back surface side of the SiC substrate 701 by a film forming method such as electron beam evaporation or DC magnetron sputtering. A contact base material such as Ni or Co is deposited to a thickness of about 50 nm to 100 nm. Subsequently, after performing a heat treatment at about 600 ° C. for 1 hour, the SiC substrate 701 is immersed in a mixed solution of sulfuric acid and hydrogen peroxide water at about 110 ° C. to 130 ° C. to adhere to an insulating film such as the interlayer insulating film 709. Unreacted Ni that has been removed is removed. On the other hand, a precursor of Ni silicide remains on the bottoms of the source windows 710a and 710b, the bottom of the gate window, and the main surface on the back side of the SiC substrate 701.

Subsequently, the SiC substrate 701 is subjected to a rapid heat treatment for about 2 minutes in an inert atmosphere at about 1000 ° C. to form low-resistance source electrodes 711a and 711b, gate contacts (not shown), and a drain electrode 714. The formed source electrodes 711a and 711b and drain electrode 714 both have extremely low contact resistance on the order of 10 ⁻⁶ Ωcm ² or less. Thereafter, using the method described in FIG. 5, the insulating barrier film 713 is formed and covered on the surface of the interlayer insulating film 709, the side walls of the source windows 710a and 710b, and the side walls (not shown) of the gate window ( FIG. 8-B (e)).

  Next, after sufficiently washing and drying the SiC substrate 701, a wiring electrode material of the main surface on the surface side, for example, Al is formed on the entire main surface on the front surface side of the SiC substrate 701 by DC magnetron sputtering or the like. Al is patterned by lithography and dry etching (RIE or the like) to form an Al wiring 712. Thereafter, the photoresist material is peeled off, and SiC substrate 701 is washed and dried. When a barrier metal such as Ti, TiN, or TaN is inserted between the Al wiring 712 and the source electrodes 711a and 711b, the wiring 712 is formed after these materials are first formed. . When the wiring 712 is made of Al, the barrier metal constituent material can be continuously patterned with the same etchant gas as Al.

  Finally, a mounting electrode material used for die bonding mounting or the like is deposited on the entire surface of the drain electrode 714 on the main surface on the back surface side of the SiC substrate 701 by using DC magnetron sputtering or the like to form the mounting electrode 715. An example of the mounting electrode 715 is a Ti / Ni / Ag laminated film in which Ti (thickness of about 80 nm), Ni (thickness of about 300 nm), and Ag (thickness of about 700 nm) are laminated in this order. This is not the only one. Thus, the MOSFET semiconductor device shown in FIG. 7 is completed (FIG. 8-B (f)).

  As is apparent from the description of the manufacturing process described above, the above manufacturing method is reasonable for manufacturing a power MOSFET, which is a typical semiconductor device including an Al wiring and an interlayer insulating film mainly composed of silica glass. It can be easily introduced. Accordingly, similarly, other IGBTs (insulated gate bipolar transistors), JFETs (junction FETs), SITs (electrostatic induction transistors), and MESFETs having Al wiring and silica glass-based interlayer insulating films (MESFETs) The present invention can be easily applied to the manufacture of semiconductor devices such as metal semiconductor junction field effect transistors.

  The present invention is extremely useful for high-temperature use of semiconductor devices such as SiC and GaN, which are rapidly being put into practical use. However, the present invention is not limited to this, and is intended for use at high temperatures of about 200 ° C. or higher. The present invention is equally applicable to semiconductor devices made of all semiconductor materials such as diamond semiconductor devices and semiconductor devices formed on SOI substrates.

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... 1st insulating film 13 ... Electrode 14,709 ... Interlayer insulating film 15,713 ... Insulating barrier film 15a ... Primary insulating barrier film 15b ... Secondary insulating barrier film 16,712 ... Wiring 31 ... Conductive region DESCRIPTION OF SYMBOLS 41 ... Contact hole 51 ... Silica glass film 61 ... 1st interlayer insulation film 62 ... 1st insulation barrier film 63 ... 1st wiring 64 ... 2nd insulation barrier film 65 ... 2nd interlayer insulation film 66 ... 3rd insulation barrier film 67 ... Second wiring 700 ... Unit cell 701 ... SiC substrate 702 ... Epitaxial layers 703a, 703b, 705a, 705b ... Base region 704a, 704b ... Source region 706 ... Gate insulating film 707 ... Gate electrode 708 ... Polycrystalline silicon oxide film 710a, 710b ... Source window 711a, 711b ... Source electrode 714 ... Drain electrode 715 ... Mounting Pole 801, 803 ... thermal oxide film 802 ... field insulating film 804 ... polycrystalline silicon film

Claims (13)

A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A barrier film formed in contact with the insulating film and formed of insulating nitride, carbide, nitrided carbide single layer film, multilayer film or mixed film;
And a metal wiring formed in contact with the barrier film. The semiconductor device according to claim 1, further comprising a metal electrode formed on the semiconductor substrate and covered with the insulating film. The semiconductor device according to claim 1, further comprising a conductive region formed in the semiconductor substrate. Having an end surface of the insulating film as a side wall and a contact hole in which the metal wiring is embedded;
The semiconductor device according to claim 1, wherein the barrier film is formed on a sidewall of the contact hole. The semiconductor device according to claim 1, wherein the insulating film, the barrier film, and the metal wiring are multi-layered. The barrier film is composed of any one of an insulating SiC film, SiN film, GeC film, GeN film, and AlN film, a mixed film thereof, or a laminated film thereof. The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein the barrier film is formed to be thicker than about 20 nm and thinner than the insulating film. The insulating film is composed mainly of silica glass,
The semiconductor device according to claim 1, wherein the metal wiring is made of aluminum. The semiconductor device according to claim 1, wherein the metal wiring includes a barrier metal layer. A first step of forming an insulating film on a semiconductor substrate;
A second step of forming a first barrier film in contact with the insulating film;
A third step of selectively removing the insulating film and the first barrier film to open a contact hole having a sidewall including an end face of the insulating film;
A fourth step of forming a second barrier film on the side wall and bottom of the contact hole;
A fifth step of selectively removing the second barrier film formed on the bottom of the contact hole and leaving the second barrier film on the side wall of the contact hole;
A sixth step of forming a metal wiring in the contact hole,
The method of manufacturing a semiconductor device, wherein the first barrier film and the second barrier film are formed of a single layer film or a multilayer film of insulating nitride, carbide, nitride carbide. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming an oxide film in contact with the first barrier film between the second step and the third step. The method of manufacturing a semiconductor device according to claim 10, wherein the first barrier film and the second barrier film are formed at a temperature of about 600 ° C. or less. The first barrier film and the second barrier film may be formed by chemical vapor deposition of any one of plasma CVD, MO (organometallic) CVD, ALD (atomic layer deposition), and photoexcited CVD. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is grown by a method.

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