JPH01184975A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:Not only to improve the controllabvility of an active layer and a buried layer in width but also restrain a large stress from generating by a method wherein the side of the active layer is removed through a selective etching to make the central part of the active layer, which is protected against the etching by a pair of stripe-like regions, an active region which is contributory to the light emission. CONSTITUTION:An n-type InP buffer layer 11 (3mum or so in thickness) is laminated on an n-type InP substrate 10. Next, a GaInAs active layer 12 is laminated thereon and the active layer 12 is selectively etched to form a pair of stripes 20 which make the active layer 12 separate into a central active layer 12a and side active layers 12b. In this process, the shape of the stripes 20 is so formed as to make a buried region gradually larger in width near and toward the end face. And, a P-type InP clad layer 13 and a P<+>-type GaInAsP cap layer are laminated to form a mesa 19. In this process, buried layers 13a, which sandwich the active region 12a formed in one piece with the P-type InP clad layer 13 in between them, are formed at the pair of stripes 20. Next, the side active layers 12b are removed through an etching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor devices such as semiconductor lasers and light emitting diodes, and particularly relates to semiconductor devices that perform high-speed modulation.

(Prior Art) Semiconductor devices such as semiconductor lasers and light emitting diodes are used as light sources for optical communication and original information processing. In a semiconductor device that performs high-speed modulation, the modulation characteristics are limited by the R and C time constants, so there is a particular need to reduce the junction capacitance.

An example of conventional technology that relatively satisfies this requirement is Mass Transport.
There are mesa lasers using the method (hereinafter referred to as MT), which is applied to Ga1nAsP/InP semiconductor lasers (for example, Y, Hirayama et al.
,, LOWTemperature and rap
id mass transport technology
uefor Ga1nAsP/ InF DFB 1a
sers, Ins t, Phys, Conf.

Ser, N179:Chapt, 3Paper pre
sent at Int, Symp+GaAs a
nd Re1ated Compounds Karu
Japan.

1985 p, 175-186). As shown in FIG. 3, this MT buried laser has n
-InP buffer layer 11, GaInAsP active layer 12, p-InP cladding layer 13, p"-GaInAsP key, 7 layer 14 are crystal grown, then mesa 19 is formed by etching, and then active layer 12 is side-layered. The active region 12a with a width of 1 μm is removed by etching, and then the M
The MT embedding R3) is buried using the T method, and finally the Sing film 18, electrode 15, back electrode 17, and gold 16 are formed to complete the process.

In this MT buried laser, the junction of the buried layers is limited to only the mesa portion 19, which has a relatively small area. Furthermore, as shown in FIG. 4, by reducing the width of the KMT buried layer 3), it is possible to reduce the junction area of the Yoshiba layer buried layer. Therefore, it has the characteristics of small junction capacitance and excellent high-speed modulation characteristics.

However, in this MT buried laser, the active layer 12
This method has the problem that extremely difficult control is required to start etching from the width of the mesa 19 of about 15 μm and ultimately leave the active region 12a with a width of 1 μm. Also,
In particular, in order to obtain high-speed modulation characteristics, the MT buried layer 3)0
When the width is set to several μm or less, the high-speed modulation characteristics vary due to poor controllability of the width of the MT buried layer °3).
In addition, the mesa 19 with a width of about 15 μm is supported by the MT buried layer 3) with a width of several μm or less and the active region 12a, resulting in an unstable structure, which causes distortion and generates large stress in the active region. ing.

(Problems to be Solved by the Invention) This invention was made in consideration of the above circumstances, and improves the controllability of the width of the active layer and the width of the buried layer, suppresses the generation of large stress, and further improves the controllability of the width of the active layer and the width of the buried layer. It is an object of the present invention to provide a high-performance semiconductor device with excellent high-speed modulation characteristics and a method for manufacturing the same, which also has a good emission shape.

The gist of the invention is to separate the active layer into a central portion and side portions by a pair of striped regions that are etched selectively to the active layer. This pair of striped regions has a large width near the end face. Thereafter, the side active layer is removed by selective etching, and the central active layer whose etching is prevented by a pair of striped regions becomes an active region contributing to light emission.

(Function) According to this invention, since the active layer in the side 9 portion is removed, K
I) The area of the n-junction is limited to the active region and a pair of buried regions, and the width of the buried region can be made as narrow as PEP and etching techniques allow, making it possible to significantly reduce parasitic capacitance. It is. Furthermore, the width of the active layer at the center and the width of the buried region, which will become the active region, are defined by PEP, and the active layer at the sides is removed by selective etching. The reproducibility is extremely good.

Furthermore, since stress due to strain is concentrated near the end face, increasing the width of the embedded region near the end face alleviates stress concentration and improves reliability. In addition, when the width of the buried region is smaller than 1 μm, the confinement of the lateral light mode is too strong and the far-field image becomes large. By gradually increasing the distance, the far-field image can be made smaller.
For example, it is possible to increase coupling efficiency to optical fibers and the like.

(Example) An example of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 shows a cross section of each part of a semiconductor device of the present invention. FIG. 1(a) is a sectional view along the plane z-z' (shown in FIG. 1(b)) parallel to the main surface of the substrate including the active region 12a, FIGS. 1(b) and 1(C), and (d) is the first
FIG. 2 is a cross-sectional view of the vicinity of the end surface along the line X-XI (shown in FIG. 1(a)) perpendicular to the active region 12a of the second and third embodiments.

FIG. 2 is a process sectional view showing the method for manufacturing a semiconductor device of the present invention. First, as shown in FIG. 2(a), n-type In
On the P substrate 10, the n fil InP buffer 7-layer 11
(approximately 3 μm thick). Next, as shown in FIG. 2(b)K, a GaInAsP active layer 12 (thickness 0.12 μm
) are stacked, and the active layer is etched away in a pair of stripes 20 to form a central active layer 812a and a side active layer 12b separately. At this time, the striped shape 20 is shaped like 13 in FIG. 1(b) or C) or d) near the end face.
Form as shown in step 3. Next, as shown in FIG.
+ type GaInAsP #Yap layer 14 (thickness approximately 1 μm
) to form a mesa 19.

At this time, a buried region 13a is formed in the pair of stripes 20 described above, sandwiching the active region 12a integrally formed with the p-type InP cladding layer 13. Next, as shown in FIG. 2(d), the active layer 12b of the active part is etched away using a mixed solution of sulfuric acid, hydrogen peroxide, and water. This mixed solution acts on Ga I nAsP but not on InP. Therefore, etching of the central active layer 12a is prevented by the buried regions 13a sandwiching it. Next, as shown in FIG. 2(e), a SiO film 18 (thickness approximately 0.5 μm) is applied to the entire surface.
A
A p-side ohmic contact is formed by laminating u/Z n/A u films (thickness approximately 0.3 μm), and Au/
A Gr film 16 (about 0.5 μm thick) is laminated. On the back surface, an Au/Au-Ge film 17 (about 0.5 μm thick) is laminated to form an nfIIl electrode.

〔Effect of the invention〕

The semiconductor device of the present invention is capable of high-speed response, has high reliability because stress does not concentrate near the end face, and has a small far-field pattern of emitted light and high coupling efficiency. Further, according to the manufacturing method of the present invention, this semiconductor device can be obtained with good reproducibility and controllability, and therefore with high yield and low cost.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device of the present invention, FIG. 2 is a process sectional view showing a method of manufacturing a semiconductor device of this invention, FIG. 3 is a process sectional view of a conventional example, and FIG. 4 is a process sectional view of another conventional example. It is a sectional view showing an example. 10 InP substrate 11 n-InP buffer layer 12 GaInAsP active layer 13 p-InP cladding layer 14 -p+-GaInAsP layer 1
5 = -Au/Zn/Au electrode 16--・Au/Cr film 17--・-Au/Au-0e electrode 18...SiO,i Agent Patent attorney Yudo Noriyoshi Chika Mitsuyuki Matsuyama Figure 2

Claims (6)

[Claims] (1) A substrate having a first semiconductor layer with a first conductivity, a mesa portion having a second semiconductor layer of a second conductivity type provided above the first semiconductor layer, and the first semiconductor layer. an active region that is formed between the second semiconductor layer and the second semiconductor layer and contributes to light emission, and a pair of active regions that are in contact with the active region on both sides in the width direction of the active region and are formed of a different semiconductor than the active region. A semiconductor device comprising a buried region sandwiching an active region, and electrically insulating regions located between the first semiconductor layer and the second semiconductor layer and formed on both outer sides of the buried region. A semiconductor device characterized in that the buried region has a large width near an axial end face of the semiconductor device. (2) Claim 1 characterized in that the width of the buried region near the end face is gradually increased toward the end face.
The semiconductor device described. (3) The semiconductor device according to claim 1, wherein the buried region comprises a pair of protrusions integrally formed with the first semiconductor layer or the second semiconductor layer. (4) Forming an active layer separated into a central active layer and a side active layer on a substrate having a first semiconductor layer of a first conductivity type, and at least the central active layer and the side active layer. forming a mesa portion having a second semiconductor layer of a second conductivity type on the upper surface of the layer; and removing the side active layer by etching to remove the semiconductor between the central active layer and the side active layer. In the method of manufacturing a semiconductor device, the method includes the step of making the central active layer whose etching is prevented by a region into an active region that contributes to light emission, wherein the central active layer and the side regions are formed in the vicinity of an axial end surface of the active region. 1. A method of manufacturing a semiconductor device, comprising forming a semiconductor region with a large width between active layers. (5) The method of manufacturing a semiconductor device according to claim 4, wherein the width of the semiconductor region between the central active layer and the side active layer near the end face is gradually increased toward the end face. (6) The active layer is formed by stacking the active layer on the first semiconductor layer, and removing the active layer in a pair of stripes extending at a predetermined distance from each other by etching. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising forming the central active layer and the side active layer.