JPH01184836A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01184836A JPH01184836A JP63005519A JP551988A JPH01184836A JP H01184836 A JPH01184836 A JP H01184836A JP 63005519 A JP63005519 A JP 63005519A JP 551988 A JP551988 A JP 551988A JP H01184836 A JPH01184836 A JP H01184836A
- Authority
- JP
- Japan
- Prior art keywords
- thickness
- lead frame
- thin
- frame
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 14
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
廉果上座ガ月分！
本発明は、半導体装置、１特に、ホール素子等の半導体
素子をリードフレームに取り付けた半導体装置に関する
。[Detailed Description of the Invention] Benevolent Theraza Moon! The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor element such as a Hall element is attached to a lead frame.
従来の 術と解決課題
近年、半導体装置の小形化、薄形化の要求が強い。例え
ば、ホール素子ではそれが組み込まれるモータの小形化
、薄形化の要請に対応するため、半導体装置自体の小形
化、薄形化が要求されている。Conventional Techniques and Problems to be Solved In recent years, there has been a strong demand for smaller and thinner semiconductor devices. For example, in order to meet the demand for smaller and thinner motors in which Hall elements are incorporated, semiconductor devices themselves are required to be smaller and thinner.
従来、ホール素子は所定形状を有するリードフレーム上
に載置され、リードフレームとはワイヤボンディングに
て接続されていた。そこで、装置全体の薄形化を達成す
る一つの手段としてリードフレームを薄形化することが
考えられる。装置全体の厚さを要求されている０、５ｍ
ｍ以下とするためには、リードフレームの厚さを０．１
ｍｍ以下とすることが望ましい。しかしながら、リード
フレームの厚さを全体として０．１ｍｍ以下にすると剛
性９強度が低下し、モールド樹脂の外へ引き出される端
子部分の強度が不足し、取り扱いが困難になるという問
題点を有している。Conventionally, a Hall element has been placed on a lead frame having a predetermined shape, and connected to the lead frame by wire bonding. Therefore, one possible means for achieving a thinner overall device is to make the lead frame thinner. The required thickness of the entire device is 0.5m.
In order to make it less than m, the thickness of the lead frame should be 0.1
It is desirable that the thickness be less than mm. However, if the overall thickness of the lead frame is reduced to 0.1 mm or less, the rigidity and strength of the lead frame decreases, and there is a problem that the strength of the terminal portion that is pulled out of the molded resin is insufficient, making it difficult to handle. There is.
そこで、本発明は、ホール素子等の半導体装置において
、リードフレームの強度を損なうことなく、装置全体と
しての薄形化を達成することを課題とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the overall thickness of a semiconductor device such as a Hall element without impairing the strength of the lead frame.
課題を解決するための手段と作用
以上の課題を解決するため、本発明に係る半導体装置は
、リードフレームの一部表面に薄肉部を設け、この薄肉
部に半導体素子を載置０たことを特徴とする。Means and Effects for Solving the Problems In order to solve the above problems, the semiconductor device according to the present invention has a thin wall portion provided on a part of the surface of the lead frame, and a semiconductor element is placed on the thin wall portion. Features.
即ち、半導体素子がリードフレームの部分的な薄肉部に
載置されることにより、装置全体としての厚さが薄くな
る。そして、半導体素子の周囲は樹脂でモールドきれ、
リードフレームの薄肉部分の強度不足が補われる。一方
、モールド樹脂から引き出された部分は従来と同様の厚
さを有し、強度不足を来すおそれはない。That is, by placing the semiconductor element on a partially thin portion of the lead frame, the thickness of the entire device becomes thinner. Then, the area around the semiconductor element is molded with resin,
This compensates for the lack of strength in the thin parts of the lead frame. On the other hand, the part pulled out from the molded resin has the same thickness as the conventional one, and there is no risk of insufficient strength.
実施例
以下、本発明に係る半導体装置の一実施例を添付図面に
従って説明する。Embodiment Hereinafter, one embodiment of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
この実施例はホール素子に適用したものであり、第１図
中、ホール素子チップ１はリードフレーム５の薄肉部５
ａ上に載置され、金製のワイヤ４にて各リードフレーム
５，６，７．８と電気的に接続されている。This embodiment is applied to a Hall element, and in FIG.
a and is electrically connected to each lead frame 5, 6, 7.8 by a gold wire 4.
リードフレーム５，６，７．８は、りん青銅からなり、
第２図に示す平面形状に形成され、その一つのリードフ
レーム５は周囲にリブ状の突起５ｂを残して段差を有す
る薄肉部５ａとされている。The lead frames 5, 6, 7.8 are made of phosphor bronze,
One of the lead frames 5 is formed into the planar shape shown in FIG. 2, and has a thin portion 5a having a step except for a rib-like protrusion 5b around the periphery.
リードフレーム５，６，７．８の加工は上下面よりエツ
チングを施して行なった。詳しくは、第４Ａ図に示す様
に、リードフレーム材１０の上下面にフレームの形状と
して残すべき箇所に耐エツチングマスク１１を設け、厚
さ０．１ｍｍのリードフレーム材１０に対して上下面を
約０．０５ｍｍの深さにエツチングを行なった。これに
て第４Ｂ図に示す様に、マスク１１の設けられていない
部分が溶かし出されてリードフレーム５，６，７．８の
外形が形成され、前記薄肉部５ａは上面のみが溶かし出
されて０、０５ｍｍの厚さに形成されることとなる。Lead frames 5, 6, 7.8 were processed by etching from the top and bottom surfaces. Specifically, as shown in FIG. 4A, an etching-resistant mask 11 is provided on the upper and lower surfaces of the lead frame material 10 at the portions that should be left in the shape of the frame, and the upper and lower surfaces of the lead frame material 10 with a thickness of 0.1 mm are etched. Etching was performed to a depth of about 0.05 mm. As shown in FIG. 4B, the portions where the mask 11 is not provided are melted out to form the outer shapes of the lead frames 5, 6, 7.8, and only the upper surface of the thin wall portion 5a is melted out. Thus, it is formed to a thickness of 0.05 mm.
以上の如く形成されたリードフレーム５の薄肉部５ａ上
に前記ホール素子チップ１を載置し、ワイヤボンディン
グを行なった後、チップ１の周囲を樹脂２０にてモール
ドし、ホール素子として完成される。After placing the Hall element chip 1 on the thin wall portion 5a of the lead frame 5 formed as described above and performing wire bonding, the periphery of the chip 1 is molded with resin 20 to complete the Hall element. .
厚さに関して、−例として記述すると、リードフレーム
５，６，７．８の厚さＤａは０．１ｍｍ、薄肉部５ａの
厚さＤｂは０．０５ｍｍ、 リードフレーム５の底面
からチップ１の上面までの厚さＤＣは０．２５ｍｍ、ワ
イヤの高さＤｄは０．０５ｍｍ、チップ１の上面からモ
ールド樹脂２０の上面までの厚さＤｅは０．１ｍｍ、モ
ールド樹脂２０の下面からリードフレーム５の下面まで
の厚さＤｆは０．０５ｍｍ、モールド樹脂２０の全体厚
さＤｈは０．４ｍｍである。Regarding the thickness, as an example, the thickness Da of the lead frames 5, 6, 7.8 is 0.1 mm, the thickness Db of the thin part 5a is 0.05 mm, from the bottom surface of the lead frame 5 to the top surface of the chip 1. The wire height Dd is 0.05 mm, the thickness De from the top surface of the chip 1 to the top surface of the mold resin 20 is 0.1 mm, and the wire height Dd is 0.25 mm. The thickness Df to the bottom surface is 0.05 mm, and the total thickness Dh of the molded resin 20 is 0.4 mm.
以上の構成において、チップ１は薄肉部５ａ上に載置き
れることから装置全体としての厚さが薄くなる。そして
、薄肉部５ａの強度は突起５ｂによって補強されている
が、同時に、樹脂２０でモールドすることで十分なもの
とされている。一方、モールド樹脂２０から露出した端
子部分は０．１ｍｍの厚さを有し、剛性９強度の点で問
題はない。In the above configuration, since the chip 1 is placed on the thin wall portion 5a, the thickness of the device as a whole becomes thin. The strength of the thin portion 5a is reinforced by the projections 5b, but at the same time, molding with the resin 20 is sufficient. On the other hand, the terminal portion exposed from the molded resin 20 has a thickness of 0.1 mm, and there is no problem in terms of rigidity and strength.
なお、本発明に係る半導体装置は以上の実施例に限定さ
れるものではなく、その要旨の範囲内で種々に変形する
ことができる。Note that the semiconductor device according to the present invention is not limited to the above embodiments, and can be variously modified within the scope of the gist.
例えば、チップ１を載置する薄肉部５ａの強度に問題が
なければ、突起５ｂは必ずしも必要ではなく、載置部分
を全体的にフラットな薄肉部としても良い。また、リー
ドフレームの加工はエツチングの他にプレス加工等にて
行なうことも可能である。For example, if there is no problem with the strength of the thin wall portion 5a on which the chip 1 is placed, the protrusion 5b is not necessarily necessary, and the placement portion may be a flat thin portion as a whole. In addition to etching, the lead frame can also be processed by pressing, etc.
発明の効果
以上の説明で明らかな様に、本発明によれば、リードフ
レームの一部表面に設けた薄肉部に半導体素子を載置し
、該素子とリードフレームとを電気的に接続した後、該
素子を樹脂でモールドしたため、装置全体の厚さが小さ
くなり、小形化、薄形化の要求を満足させると同時に、
端子部分の強度も何ら損なうことがない。Effects of the Invention As is clear from the above explanation, according to the present invention, a semiconductor element is mounted on a thin wall portion provided on a part of the surface of a lead frame, and after electrically connecting the element and the lead frame. , Since the element is molded with resin, the thickness of the entire device is reduced, satisfying the demands for miniaturization and thinning.
There is no loss in the strength of the terminal portion.
図面は本発明に係る半導体装置の一実施例を示し、第１
図は装置の垂直断面図、第２図はリードフレームの平面
図、第３図は第２図のＡ−Ａ断面図、第４Ａ図、第４Ｂ
図はリードフレームの加工工程を示す断面図である。
１・・・ホール素子チップ、４・・・ワイヤ、５，６゜
７．８・・・リードフレーム、５ａ・・・？１ｊ肉部、
２０・・・モールド樹脂。The drawings show one embodiment of the semiconductor device according to the present invention, and the first
The figure is a vertical sectional view of the device, Figure 2 is a plan view of the lead frame, Figure 3 is a sectional view taken along line A-A in Figure 2, Figures 4A and 4B.
The figure is a cross-sectional view showing the processing steps of the lead frame. 1...Hall element chip, 4...Wire, 5,6°7.8...Lead frame, 5a...? 1j meat part,
20...Mold resin.
Claims (1)
を載置し、半導体素子とリードフレームとを電気的に接
続した後、半導体素子を樹脂でモールドした半導体装置
において、 前記リードフレームの一部表面に薄肉部を設け、この薄
肉部に前記半導体素子を載置したこと、を特徴とする半
導体装置。(1) In a semiconductor device in which a semiconductor element is mounted on a lead frame having a predetermined shape, the semiconductor element and the lead frame are electrically connected, and the semiconductor element is molded with resin, a part of the surface of the lead frame is provided. 1. A semiconductor device, characterized in that a thin wall portion is provided in the semiconductor device, and the semiconductor element is mounted on the thin wall portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63005519A JPH01184836A (en) | 1988-01-13 | 1988-01-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63005519A JPH01184836A (en) | 1988-01-13 | 1988-01-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01184836A true JPH01184836A (en) | 1989-07-24 |
Family
ID=11613437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63005519A Pending JPH01184836A (en) | 1988-01-13 | 1988-01-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01184836A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170584A (en) * | 1988-12-23 | 1990-07-02 | Asahi Chem Ind Co Ltd | Magnetoelectric conversion element |
| JPH0629149U (en) * | 1991-10-15 | 1994-04-15 | 新電元工業株式会社 | Resin-sealed semiconductor device |
-
1988
- 1988-01-13 JP JP63005519A patent/JPH01184836A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170584A (en) * | 1988-12-23 | 1990-07-02 | Asahi Chem Ind Co Ltd | Magnetoelectric conversion element |
| JPH0629149U (en) * | 1991-10-15 | 1994-04-15 | 新電元工業株式会社 | Resin-sealed semiconductor device |
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