JPH01184798A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To easily optimize a writing pulse and to speed up a writing cycle by executing writing by a writing pulse supplied directly from the outside to the inside in stead of an internal writing pulse to know writing characteristics and observing a monitoring output pin to know the width of a writing pulse generated from the inside. CONSTITUTION:The title device includes a signal switching means 2 capable of supplying a writing pulse obtained from an external input terminal directly to an internal memory array part 4 in stead of an internal writing pulse on the basis of an external control signal and a monitoring means consisting of a buffer 6 for outputting a writing pulse generated in its inside to the external without influencing an internal signal and its output terminal. Consequently, the optimization of a writing pulse can be easily checked, a writing cycle can be shortened and memory operation can be speeded up.

Description

[Detailed Description of the Invention] [Industrial Application gP] The present invention is a particularly effective technique when applied to semiconductor integrated circuit technology and also to circuits for monitoring internal signals and diagnosing internal circuits of semiconductor integrated circuits. The present invention relates to a technique that is effective for use in, for example, a RAM (Random Access Memory) with a built-in write pulse generation circuit.

[Prior Art] In a conventional static RAM, writing is generally performed by directly inputting a write pulse from the outside in the form of a write enable signal.

By the way, a RAM in which a write pulse is applied externally
If the skew of the address signal or data signal is large, there is a risk of erroneous writing unless the setup time and hold time are increased accordingly (Asakura Shobo, published June 30, 1981, "Integrated Circuit Application Handbook") (See page 331). As a result, a write pulse that is significantly longer than the time required for the actual write is required;
It has been difficult to speed up the write cycle.

Therefore, for example, by providing a circuit that detects changes in the address signal and automatically generates a write pulse internally,
A technique has been proposed that generates a relatively narrow pulse width write pulse regardless of the skew of the address signal or data signal, thereby increasing the speed of the write cycle without malfunction.

[Problem to be solved by the invention] However, a RAM with a built-in write pulse generation circuit
In this case, it is possible to shorten the write cycle by optimizing the write pulse through simulation. However, there is no function to monitor the write pulses generated inside the actually manufactured LSI or means to check the write characteristics (minimum write time) of the RAM. Therefore, there was a problem in that it was impossible to confirm whether the write pulse was actually set to the optimum value.

An object of the present invention is to easily check whether the write pulses are optimized in a memory with a built-in write pulse generation circuit, thereby shortening the write cycle and achieving faster memory speed. The purpose is to provide semiconductor memory technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a signal switching means is provided that can directly supply a write pulse from an external input terminal to an internal memory array section in place of an internal write pulse using an external control signal, and a signal switching means that allows an internally generated write pulse to affect an internal signal. This device incorporates monitor means consisting of a buffer and its output terminal for outputting data to the outside.

[Function] According to the above-mentioned means, the write characteristics can be determined by performing writing with a write pulse supplied directly from the outside to the inside instead of the internal write pulse, and the internal generation can be determined by observing the output pin for monitoring. The width of the written write pulse can be known, which facilitates the optimization of the write pulse and achieves the above-mentioned objective of speeding up the write cycle.

[Embodiment] FIG. 1 shows the present invention in a bipolar type static RAM.
An example in which the method is applied to is shown.

In the figure, reference numeral 1 denotes a write pulse generation circuit that generates an internal write pulse WP based on a write control signal such as a write enable signal W supplied from the outside. When the write control signal WE is set to a write level such as a low level, the signal is output at an appropriate timing and at a predetermined time based on an external clock signal in synchronization with a signal supplied from an address change detection circuit or an address signal. A write pulse WP having a pulse width is generated.

The write pulse Wp generated by the write pulse generation circuit 1 is supplied to a signal switching circuit 2 formed of an ECL type six series gate.

The signal switching circuit 2 includes an input transistor Q□ whose base terminal receives the write pulse, and a reference voltage V.
Reference transistor Q with an□ applied to the base terminal
A transistor Q,
It consisted of a so-called series gate in which the second stage current switches consisting of , Q, were stacked vertically.

The first stage current switch (Q, Q2) is connected to the reference potential VB applied to the base of the reference transistor Q2.
B1 is a logic threshold, and the differential outputs d and d are inverted depending on whether the level of the signal Wp input to the base terminal of the transistor Q1 is higher or lower than Vanl. In this case, the output d is in phase with the input signal WP, and the output d is in phase with the input signal WP. The above differential outputs d and J are emitter followers EF1. The impedance is converted through EF, and the pulse is supplied to the write pulse supply circuit 3 at the next stage.

Furthermore, among the transistors Q, Q, which constitute the second stage current switch, the transistor Q t tQ2
A transistor Q connected to the common emitter of.

A reference voltage VaB is input to the base terminal of the transistor Q2, and a signal applied to the external test pin TP is input via the input buffer 5 to the base terminal of the other transistor Q4 whose collector is commonly connected to the transistor Q2.

During normal operation, the signal applied to this external test pin Tp is fixed at a low level. Then.

Transistor Q4 is turned off, Q is turned on, current flows through the first stage current switch Q, tQz side, and the signal switching circuit 2 operates to switch only the first stage current switch, inputting it to the base of transistor Q□. Write pulse WP
The corresponding signal is supplied to the next stage circuit.

On the other hand, during testing, for example, the write control signal WE is set to high level, or other control signals are set to the write pulse generation circuit 1.
By inputting the signal to the test pin TP, a signal (pulse) is input from the outside to the test pin TP while the signal (Wp) supplied to the transistors 1 to Q4 is fixed at a high level. Then, the signal switching circuit 2 operates to switch only the second stage current switch, and operates to supply the pulse input to the test pin TP to the next stage circuit.

The write pulse supply circuit 3 in the next stage is composed of two general ECL gates Gl and G2 with emitter followers, and the differential output from the signal switching circuit 2 in the previous stage is commonly input to each ECL gate Gl and G2. as a buffer
Operate.

The output signal of one ECL gate G1 is supplied to the memory array section 4, and the output signal of the other ECL gate G2 is outputted to a monitor output pin MP (hereinafter referred to as a monitor pin) via an output buffer 6. It looks like this. The transistor constituting the output buffer 6 connected to the monitor pin MP is preferably a transistor with a so-called double base structure in order to increase the striking force of the buffer.

Although not particularly limited, the emitter terminal of the output transistor Q constituting the output buffer 6 is connected to the monitor pin MP, and an emitter follower can be configured by externally connecting a resistor between the monitor pin MP and the ground point. The output level is determined and the output signal can be observed externally.

Therefore, in the RAM of this embodiment, 1 ordinary RAM
If you want to operate in the same way as above, fix the external test pin TP to low level and operate.

Then, the write pulse WP generated by the write pulse generation circuit 1 is supplied to the memory array section 4 via the signal switching circuit 2 and the pulse supply circuit 3, and writing of data is executed. At this time, the write pulse Wp supplied to the memory array section 4 is branched by the pulse supply circuit 3, and exactly the same pulse is outputted from the output buffer 6 to the monitor pin MP. Therefore, by observing the signal on this pin MP, it is possible to monitor the internal write pulse WP and find out whether the write pulse Wp with the desired pulse width is being formed.

On the other hand, when measuring the performance of the RAM, that is, the write characteristics of the memory array section 4, with the signal supplied from the write pulse generation circuit 1 to the signal switching circuit 2 fixed at a high level, Input the write pulse WP formed by . The minimum write pulse width can be determined by reading whether or not writing has been performed correctly while varying the pulse width of the external write pulse WP. The write pulse can be optimized by resetting the constants of the elements in the write pulse generation circuit 1 so that the write pulse Wp matching the minimum write pulse width can be generated.

In addition, when simply monitoring the internal write pulse WP, the ECL gate G2 is omitted, and the output signals of the emitter followers EF1 to EF2 in the signal switching circuit 2 are transferred to the transistor circuit constituting the output buffer 6, and Q1
You can enter it directly into □.

However, in that case, emitter followers EF1゜EF2
Although there is a possibility that the load on the write pulse Wp becomes large and the original write pulse Wp is delayed, such an adverse effect can be prevented by providing the ECL gate G2 as in the embodiment.

The case where the above diagnostic function and internal write pulse monitoring function are used by a manufacturer for the purpose of optimizing write pulses has been described above. Therefore, from the original purpose, the test pin TP and monitor pin MP are
There is no need to provide external pins of the packaged RAM, and test probes may be provided as contactable pads. However, some users have RAM
Since some users may wish to monitor the internal write pulses to check the performance of the device, only the monitor pin may be provided as an external pin. Furthermore, in a system such as a computer using a RAM, when performing a logic diagnostic test of the system, the system may be operated slowly with a clock slower than during normal operation. In such a case, it would be convenient if a write pulse with a long pulse width could be input from the outside to operate the RAM with a long write pulse. Therefore, in consideration of such a case, pins 1 to TP in the above embodiment may be brought out of the RAM package as external pins.

As explained above, the above embodiment includes a signal switching means that can directly supply a write pulse from an external input terminal instead of an internal write pulse to the internal memory array section by an external control signal, and a write pulse generated internally. The built-in monitor means, which consists of a buffer and its output terminal, is built in to output the signal to the outside without affecting the internal signal, so instead of the internal write pulse, a write pulse directly supplied internally from the outside is used. By performing a write, it is possible to know the write characteristics, and by observing the monitor output pin, it is possible to know the width of the internally generated write pulse, which makes it easy to optimize the write pulse.
This has the effect of speeding up the write cycle.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

In the above description, the invention made by the present inventor was mainly applied to bipolar static RAM, which is the background field of application, but the invention is not limited thereto, and is applicable to MOS static RAM and other applications. General semiconductor memory that has a built-in write pulse generation circuit, as well as internal signal monitoring,
It can be used for logic LSIs that want to have the ability to externally input clocks with different cycles.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, it is possible to easily check whether the write pulses are optimized in a memory chip with a built-in write pulse generation circuit, thereby further shortening the write cycle and achieving higher speed memory.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a bipolar static RAM. DESCRIPTION OF SYMBOLS 1...Write pulse generation circuit, 2...Signal switching means, 3...Write pulse supply circuit, 4...Memory array section, TP...Test pin, MP...・
monitor pin.

Claims (1)

[Claims] 1. In a semiconductor memory device that has a built-in circuit that internally forms write control pulses, an external control signal causes a write pulse from an external input terminal to be directly applied to an internal memory array instead of an internal write pulse. It has a built-in monitor means consisting of a buffer and its output terminal for outputting the internally generated write pulse to the outside without affecting the internal signal. Semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein the output terminal is provided as an external pin of the package. 3. The semiconductor memory device according to claim 1 or 2, wherein the external input terminal is provided as an external pin of a package. 4. Claim 1, characterized in that the signal switching means is constituted by an ECL type series gate.
3. A semiconductor memory device according to item 2, item 2, or item 3.