JP2580224B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology, and more particularly to a technology particularly effective when applied to a circuit for monitoring an internal signal of a semiconductor integrated circuit or diagnosing an internal circuit. For example, the present invention relates to a technology that is effective when used for a RAM (random access memory) having a built-in write pulse generation circuit.

[Prior Art] In a conventional static RAN, writing is generally performed by directly inputting a write pulse in the form of a write enable signal from the outside.

By the way, RAM with a method of applying a write pulse from outside
In the case of, if the skew of the address signal and the data signal is large, erroneous writing may occur unless the setup time and the hold time are increased accordingly (Asakura Publishing, published on June 30, 1981, "Integrated Circuit Application Hadbook") See page 331). As a result, a write pulse much longer than the time required for actual writing is required, and it has been difficult to speed up the writing cycle.

Therefore, for example, by providing a circuit for automatically detecting a change in the address signal and automatically generating a write pulse internally, a write pulse having a relatively narrow pulse width is generated regardless of the skew of the address signal and the data signal. There has been proposed a technique capable of speeding up a write cycle without malfunction.

[Problems to be Solved by the Invention] However, a RAM having a built-in write pulse generation circuit
In this case, it is possible to shorten the write cycle by optimizing the write pulse by simulation. However, there is no function for monitoring a write pulse generated inside an actually manufactured LSI or a means for confirming a write characteristic (minimum write required time) of a RAM. For this reason, there is a problem that it cannot be confirmed whether the write pulse is actually set to the optimum value.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to easily confirm whether a write pulse is optimized in a memory having a built-in write pulse generation circuit, thereby shortening a write cycle and achieving a high-speed memory. It is to provide a semiconductor storage technology.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a signal switching means capable of directly supplying a write pulse from an external input terminal to an internal memory array portion in place of an internal write pulse by an external control signal, and an internally generated write pulse affecting an internal signal. Instead, a monitoring means comprising a buffer for outputting to the outside and an output terminal thereof is built in.

[Operation] According to the above-described means, write characteristics are generated by performing writing with a write pulse directly supplied from the outside to the inside in place of the internal write pulse, and the inside is generated by observing the output pin for monitoring. The width of the written write pulse can be known, whereby the write pulse can be easily optimized, and the above-mentioned object of achieving a high-speed write cycle can be achieved.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a bipolar static RAM.

In the figure, 1 is based on a write control signal such as a write enable signal ▲ ▼ supplied from the outside.
This write pulse generating circuit 1 generates an internal write pulse Wp. This write pulse generating circuit 1 is supplied from an address change detecting circuit or the like when a write control signal 書 込 み input from the outside is set to a write level such as a low level. A write pulse Wp having an appropriate timing and a predetermined pulse width is generated based on an external clock signal synchronized with the received signal or the address signal.

The write pulse Wp generated by the write pulse generating circuit 1 is supplied to a signal switching circuit 2 composed of an ECL type series gate.

Signal switching circuit 2 includes an input transistor Q ₁ which is adapted to receive the write pulse to the base terminal, the reference voltage V
_BB1 and a current switch in the first stage of the reference transistor Q ₂ to which is applied to the base terminal is formed by common-emitter connection, between the constant current source CC _1, 2 stage consisting of transistors Q _3, Q ₄ Are configured by a so-called series gate vertically stacked.

The first-stage current switch (Q ₁ , Q ₂ ) uses the reference voltage V _BB1 applied to the base of the reference transistor Q ₂ as a logic threshold, and outputs the signal Wp input to the base terminal of the transistor Q _1. Is inverted depending on whether the level is higher or lower than _VBB1 . In this case, the output d has the same phase as the input signal Wp, and the output has a phase opposite to that of the input signal Wp. The differential output d, is subjected to impedance conversion through the emitter followers EF ₁ and EF ₂ , and is supplied to the next-stage write pulse supply circuit 3.

The transistor Q ₃ and the transistor Q _1, Q ₂ of the common emitter connected to a reference voltage to the base terminal of the transistor Q ₃ of the Q ₄ constituting a current switch of the second stage
The signal applied to the external test pin TP is input via the input buffer 5 to V _{BB2 and} to the base terminal of the other transistor Q ₄ which is commonly connected to the transistor Q ₂ and the collector.

During normal operation, the signal applied to the external test pin Tp is fixed at a low level. Then, the transistor Q ₄
Is off, Q ₃ is on, and the first-stage current switches Q ₁ , Q
Current is applied to _two side, the signal switching circuit 2 supplies a signal corresponding to the write pulse Wp inputted to the base of the transistor Q ₁ and the switching operation only current switch of the first stage to the next stage circuit.

On the other hand, during testing, for example either to the write control signal ▲ ▼ high level, by inputting the other control signals to the write pulse generating circuit 1, signals (Wp) to the high level supplied to the transistor Q ₁ A signal (pulse) is externally applied to the test pin TP while it is fixed. Then, the signal switching circuit 2 switches only the second-stage current switch, and operates so as to supply the pulse input to the test pin TP to the next-stage circuit.

The next stage write pulse supply circuit 3 is composed of two general ECL gates G1 and G2 with an emitter follower.
The differential outputs from the preceding signal switching circuit 2 are commonly input to the ECL gates G1 and G2, and operate as buffers.

The output signal of one ECL gate G1 is supplied to the memory array unit 4, and the output signal of the other ECL gate G2 is output to a monitor output pin MP (hereinafter, referred to as a monitor pin) via an output buffer 6. It has become. As a transistor constituting the output buffer 6 connected to the monitor pin MP, a transistor having a so-called double base structure may be used in order to increase the driving power of the buffer.

Is not particularly limited, the output transistor Q ₁₃ constituting the output buffer 6 is connected to the emitter terminal monitor pin MP, and an emitter follower is constituted by using an external resistor between the ground point and the monitor pin MP The output level is determined, and the output signal can be externally observed.

Therefore, in the RAM of this embodiment, when it is desired to operate in the same manner as a normal RAM, the RAM is operated with the external test pin TP fixed at a low level. Then, the write pulse Wp generated by the write pulse generation circuit 1 is supplied to the memory array unit 4 via the signal switching circuit 2 and the pulse supply circuit 3, and the data is written. At this time, the write pulse Wp supplied to the memory array unit 4 is branched by the pulse supply circuit 3, and exactly the same pulse is output from the output buffer 6 to the monitor pin MP. Therefore, by observing the signal at the pin MP, it is possible to monitor the internal write pulse Wp and to know whether the write pulse Wp having a desired pulse width is formed.

On the other hand, when the capability of the RAM, that is, the write characteristic of the memory array section 4 is measured, the signal supplied from the write pulse generating circuit 1 to the signal switching circuit 2 is fixed at a high level, and an external signal is supplied from the test pin TP. The write pulse WP formed in the step is input. And this external write pulse WP
The minimum write pulse width can be known by reading whether or not the writing has been correctly performed while changing the pulse width of the pulse width in various ways. Then, the constants of the elements in the write pulse generation circuit 1 are reset so that a write pulse Wp that matches the minimum write pulse width can be generated.
The write pulse can be optimized.

In order to simply monitor the internal write pulse Wp, the ECL gate G2 is omitted and the signal switching circuit 2
The output signals of the emitter followers EF ₁ and EF ₂ may be directly input to the transistors Q ₁₁ and Q ₁₂ constituting the output buffer 6. However, in that case, the emitter follower EF ₁ ,
Load EF ₂ is increased, there is a risk that the original write pulse Wp delayed, by providing the ECL gate G ₂ as in Example, such an adverse effect can be prevented.

The case where the diagnostic function and the internal write pulse monitoring function are used by a manufacturer for the purpose of optimizing the write pulse has been described above. Therefore, from its original purpose, the test pin TP and the monitor pin MP need not be provided externally as external pins of a packaged RAM, but may be provided as pads to which a test probe can be contacted. However, some users may want to monitor the internal write pulse to check the capability of the RAM, so that only the monitor pin may be provided as an external pin. Further, in a system such as a computer using a RAM, when performing a logic diagnostic test of the system, the test may be performed by operating the system slowly at a clock slower than that in a normal operation. In such a case, it is convenient that the RAM can be operated with a long write cycle by inputting a write pulse having a long pulse width from the outside. Therefore, in consideration of such a case, the test pin TP in the above embodiment is used as an external pin.
You may put it out of the package of RAM.

As described above, in the above embodiment, the signal switching means capable of supplying the write pulse from the external input terminal directly to the internal memory array unit in place of the internal write pulse by the external control signal, and the internally generated write pulse And a monitor means comprising an output terminal for outputting a buffer to the outside without affecting the internal signal, so that a write pulse directly supplied from the outside to the inside instead of the internal write pulse is used. The write characteristics can be determined by performing the write operation, and the width of the internally generated write pulse can be determined by observing the output pin for monitoring, thereby facilitating the optimization of the write pulse and the write cycle. There is an effect that the speed can be increased.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

In the above description, the invention made by the present inventor was mainly applied to a bipolar static RAM, which is the field of application as the background. However, the present invention is not limited to this.
It can be used for AM or other semiconductor memories in which a write pulse generating circuit is desired to be built-in, and also for a logic LSI which needs to have a function of monitoring an internal signal or inputting a clock having a different cycle from the outside.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a memory having a built-in write pulse generating circuit, it is possible to easily confirm whether or not the write pulse is optimized, thereby further shortening the write cycle and achieving a higher speed of the memory.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment when the present invention is applied to a bipolar static RAM. 1 ... write pulse generation circuit, 2 ... signal switching means, 3
…… Write pulse supply circuit, 4 …… Memory array part, TP
…… Test pin, MP …… Monitor pin.

Claims (1)

(57) [Claims] An external input terminal capable of externally inputting a write control pulse in a semiconductor memory device incorporating a memory array section and a write pulse generating circuit for forming an internal write control pulse to be supplied to the memory array section. And a monitor means, the monitor means comprising: a signal switching means controlled to be switched by an external control signal so as to switch and select the internal write control pulse and the write control pulse from the external input terminal; A first gate circuit for supplying an output of the switching means to the memory array unit, an output buffer for outputting the internal write control pulse obtained through the signal switching means to the outside, and an output of the signal switching means And a second gate circuit for supplying the output buffer.