JPH0574174A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To restrain an influence by a power-supply noise, to prevent an error output and to achieve the high-speed operation of an output stage by a method wherein the output of a sense amplifier is cut for a definite period from a change in a data and an output data is latched. CONSTITUTION:A change in a read-out data from an output buffer circuit 60 is detected by using a data-output detection circuit 70; a timing signal is generated. A switching circuit is controlled by means of the signal; it is restrained that the output of a sense amplifier circuit 50 is transmitted to the output buffer circuit 60; the data-holding feedback circuit of an output buffer control circuit is controlled; a correct output data is fed back to the input side and held. Thereby, even when a power-supply noise at the inside of a circuit is generated in an output signal, it is possible to temperarily hold the output data of the output buffer circuit 60, to prevent an error output, to obtain a stable output characteristic and to achieve a high-speed readout operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of high speed reading.

[0002]

2. Description of the Related Art A block diagram of a conventional semiconductor memory device is shown in FIG. Memory cell data in a semiconductor memory device
When the data output changes during data reading, a rapid charging / discharging current flows through the load circuit through the data output driving circuit, and due to the influence, so-called power supply noise in which the voltage power supply and ground power supply inside the semiconductor memory device fluctuate Occurs. The potential fluctuations of the voltage power supply and the ground power supply occur when the output of the output buffer circuit switches from “H” to “L” or from “L” to “H”, and when the output switches from “H” to “L”. Causes an increase in the potential of the ground power supply, causing "L"
When switching from "H" to "H", the potential of the voltage power supply drops. When the power supply noise as described above occurs, the threshold value of the “H” or “L” level of the input signal in the input buffer circuit apparently changes, so that the correct logic level of the input signal supplied from the outside is input. The memory cells are not selected, and erroneous reading occurs at the sense amplifier output due to incorrect memory cell selection. Further, in the sense amplifier circuit, the output due to the malfunction of the sense amplifier circuit due to the power supply noise causes the erroneous output of the sense amplifier circuit. Conventionally, against the influence of such power supply noise, the power supply noise is suppressed by reducing the current drive capability of the data output driving transistor that constitutes the output buffer circuit, or between the input terminal of the input buffer circuit and the ground power supply. Connect a capacitor to dampen power supply noise and prevent spike noise from propagating inside the semiconductor memory device, or use coupling by this capacitor to change the potential of the input signal according to the potential fluctuation of the ground power supply. I was trying to do it.

[0003]

In the conventional semiconductor memory device described above, reducing the current driving capability of the data output driving transistor in the output buffer circuit delays the data reading speed. Therefore, access time is delayed. Further, even in the case of utilizing the coupling of the capacitance, if the capacitance is made large enough to completely prevent the malfunction, the input signal waveform becomes rounded and the access time is delayed. Therefore, it is not possible to set a sufficient capacity, and it is impossible to prevent malfunction depending on the magnitude of noise.

The present invention solves such a problem, and its purpose is to prevent malfunction due to the influence of power supply noise without delaying access time and to provide stable output characteristics against noise. An object of the present invention is to provide a semiconductor memory device which has a high-speed read operation.

[0005]

A semiconductor memory device according to the present invention comprises an address input buffer circuit, an address decoder circuit, a memory cell array, a sense amplifier circuit for reading memory cell data, and a selected memory. In a semiconductor memory device having a plurality of output buffer control circuits for reading data stored in cells to the outside and an output buffer circuit including a data output driving circuit, the plurality of output buffer circuits output the data. Means for detecting at least one logical change in data, means for generating an internal timing signal when a logical change occurs in at least one data output, and a switch for the internal timing signal. Controlled switch circuit provided between the sense amplifier circuit and the output buffer control circuit A data holding feedback circuit which is connected between an output end of the output buffer control circuit and an input end of the data output drive circuit and which is switch-controlled by the internal timing signal. To do.

[0006]

According to the above-mentioned means, when the data read from the output buffer circuit changes, the timing signal output from the data output change detecting means causes the output between the sense amplifier circuit and the output buffer circuit and the output. Controls the switch circuit of the data holding feedback circuit in the buffer control circuit,
Feedback control for data holding so that the switch circuit is switch-controlled so that the output of the sense amplifier circuit is not transmitted to the output buffer control circuit, and the correct output data of the output buffer control circuit is fed back to the input side and held. Switch control the circuit. Therefore, the output data of the output buffer control circuit is temporarily held even if the power supply noise in the circuit occurs in the input signal, so that the erroneous output from the output buffer is prevented and the power supply noise is stable. Output characteristics are obtained and high-speed reading is possible.

[0007]

EXAMPLES The present invention will be described below based on examples. FIG. 1 is a block diagram of a semiconductor memory device showing a first embodiment of the present invention. 10 is an address input terminal, 2
0 is an address input buffer circuit, 30 is an address decoder circuit, 40 is a memory cell array, 50 is a sense amplifier circuit for reading memory cell data, 60 is an output buffer circuit, 70 is a data output change detection circuit, and 80 is a data output terminal. Is.

FIG. 2 is an output buffer circuit diagram showing a first embodiment of the present invention. In the output buffer circuit 60, Q1 is a P-channel MOS transistor, Q2 is an N-channel MOS transistor, 101 and 102 are inverters for driving Q1 and Q2, 103 is an output control NOR,
Reference numeral 104 is an output control NAND, 105 is a data holding clocked inverter, and 106 is a sense amplifier output control clocked inverter. The clocked inverters 105 and 106 function as a switch circuit. The external address signal input to the address input terminal 10 is supplied to the address decoder circuit 30 via the address input buffer circuit 20, and the data from the specific cell in the memory cell array 40 selected by this is supplied to the sense amplifier circuit 50. To the sense amplifier output 3
01 is a sense amplifier output control clocked inverter 1
It is supplied to one input of the NOR 103 and the NAND 104 via 06, the other output of the NAND 104 is supplied with the internal output enable signal OE, and the other input of the NOR 103 is supplied via the OE inversion inverter 111. NOR
The output 113 of 103 is supplied to the gate of the transistor Q2 via the inverter 102, and the output 112 of the NAND 104 is supplied to the transistor Q2 via the inverter 101.
1 is supplied to the gate. NOR10 when OE is "H"
3 and NAND 104 are activated. OE is "L"
At some times, the output of the NOR 103 becomes "H", the output of the NAND 104 becomes "L", both the output driving transistors Q1 and Q2 are turned off, and the data output terminal 80 becomes a high impedance state. In the active state, the sense amplifier output data 301 from the sense amplifier circuit 50 is "H".
If so, the output of the NOR 103 and the output of the NAND 104 both become "H", the transistor Q1 turns on, the transistor Q2 turns off, and "H" is output to the output terminal. If the sense amplifier output 301 is at "L" level, the output of the NOR 103 and the output of the NAND 104 are both at "L" level, so that the transistor Q1 is turned off.
The transistor Q2 is turned on, and an "L" level signal is output to the output terminal.

FIG. 4 is a circuit diagram showing an output change detection circuit according to the present invention. In the output change detection circuit 70, 2
01 is a pulse control NAND, 202 is a pulse control NAND,
Reference numeral 204 is a NOR circuit for pulse synthesis, 203 and 205 are inverters, 206 is a logic inversion delay circuit of the pulse control NAND 201, and 207 is a logic inversion delay circuit of the pulse control NOR 202. The output 112 of the output control NAND 104 is connected to one input of the pulse control NAND 201.
Is directly supplied to the other input and the output control NAN
The output 112 of D104 is supplied through the logic inversion delay circuit 206, the output 113 of the output control NOR 103 is directly supplied to one input of the pulse control NOR 202, and the other input of the output control NOR 103 is supplied to the other input. The output 113 is supplied via the logic inversion delay circuit 207. Then, the output 302 of the pulse control NAND 201
The pulse synthesis NOR 204 through the inverter 203
The output 303 of the pulse control NOR 202 is supplied to the other input of the pulse synthesis NOR 204.
Is supplied, and the output of the pulse synthesizing NOR 204 is supplied to the inverter 205. The output 304 of the inverter 205 is supplied as an output change detection circuit output as a control signal of the clocked inverter 106 as a switch of the sense amplifier and the output buffer circuit and the clocked inverter 105 as an output latch circuit. The operation of the output change detection circuit 70 is performed by the output control NAND 104.
When the output of the signal changes from "L" to "H", the pulse signal 302 is output by the delay signal delayed by the logic inversion delay circuit 206 for a predetermined time, and the output control NOR1
When the output of 03 changes from "H" to "L" level,
The pulse signal 303 is output by the delay signal delayed by the logic inversion delay circuit 207 for a predetermined time, and 302 and 3
The combined pulse signal 304 of 03 is output from the output change detection circuit. The pulse signal 304 is supplied from the output change detection circuit 70 when the data output changes.
During the period of the pulse width, the output of the clocked inverter 106 becomes high impedance, and the output of 106 is not transmitted from the sense amplifier output 301 to the buffer circuit.
At the same time, the clocked inverter 105 is activated and operates as a latch circuit, which operates as a hold circuit for output data, and the output control NAND 104 or NOR1.
The correct output data of 03 is fed back from the output end of the output buffer control circuit to its input end and held, and this correct data is given to the output drive circuit, and the output data is latched. After the power supply noise disappears, that is, after the data change ends, the data holding clocked inverter 105 is again inactivated, the sense amplifier output control clocked inverter 106 is activated, and the data latch circuit is released. As a result, data is output from the sense amplifier circuit, and the output operation is performed normally. Therefore, since the data is held during the period in which the output data from the output buffer circuit 60 changes and the power supply noise is generated, the erroneous data is not output, and the data is output in the output state before the power supply noise is generated. The normal operation is continued.

FIG. 3 is an output buffer circuit diagram according to the second embodiment of the present invention. The sense amplifier output outputs a pair of complementary data, and the output buffer circuit data input is a complementary pair of data. In some cases.

[0011]

As described above, according to the present invention, since the output data of the output buffer circuit immediately before the occurrence of the power supply noise is temporarily held during the period when the power supply noise is generated, the erroneous output from the output buffer is prevented. Can be prevented. Therefore, the current driving capability of the output buffer circuit is not limited, and a high-speed semiconductor memory device is provided without limiting the operation speed in the output stage, that is, without deteriorating the access time or the like. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of an output buffer circuit in the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the output buffer circuit in the semiconductor memory device of the present invention.

FIG. 4 is a circuit diagram showing an output detection circuit in the semiconductor memory device of the present invention.

FIG. 5 is a block diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

10 ... Address input terminal. 20 ... Address buffer circuit. 30 ... Address decoder circuit. 40 ... Memory cell array. 50 ... Sense amplifier circuit. 60 ... Output buffer circuit. 70 ... Output detection circuit. 80 ... Data output terminal. 101, 102 ... Inverters for driving Q1, Q2. 103 ... NOR for output control. 104 ... NAND for output control. 105, 107, 108 ... Clocked inverter for holding data. 106, 109, 110 ... Clocked inverters for controlling sense amplifier output. 111 ... OE inversion inverter. 112 ... Output control NOR output 113 ... Output control NAND output 201 ... Pulse control NAND 202 ... NOR for pulse control. 203, 205 ... Inverter. 204 ... NOR for pulse synthesis. 206, 207 ... Logic inversion delay circuit. 301 ... Sense amplifier output. 302 ... NAND output for pulse control. 303 ... NOR output for pulse control. 304 ... Output detection circuit output. Q1 ... P-channel MOS transistor. Q2 ... N-channel MOS transistor. OE: Internal output enable signal.

Claims (1)

[Claims] 1. An address input buffer circuit, an address decoder circuit, a memory cell array, a sense amplifier circuit for reading memory cell data, and data stored in a selected memory cell to the outside. In a semiconductor memory device comprising a plurality of output buffer control circuits for reading and an output buffer circuit including a data output driving circuit, at least one or more logical changes are made to the data output from the plurality of output buffer circuits. Means for generating an internal timing signal when a logical change of at least one data output occurs, and switch control is performed by the internal timing signal,
A switch circuit provided between the sense amplifier circuit and the output buffer control circuit, connected between the output end of the output buffer control circuit and the data output drive circuit input end, and having the internal timing signal. And a feedback circuit for holding data, which is switch-controlled by the semiconductor memory device.