JPH01184546A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To realize the reduction of the holding time of a processing request by providing an interruption request counter and a control means to designate the priority order of an interruption request selectively based on the content of the counter. CONSTITUTION:A processing request generating source 4 is connected to a CPU 2 via an interruption request control part 1. The interruption request control part 1 is provided with the interruption request counter 9 of N bits and a priority order control part 102. The interruption request counter 9 counts the generating number of times of an interruption request signal from the processing request source 4, and the priority order control part 102 designates the priority order of the interruption request based on the content of the interruption request counter 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip microcomputer, and more particularly to an interrupt request control system for a single-chip microcomputer.

[Conventional technology]

In recent years, with advances in integrated circuit manufacturing technology, single-chip microcomputers (hereinafter referred to as SMCs), which integrate computer functions on a single semiconductor substrate, have become highly integrated, and the functions that can be integrated on a single semiconductor substrate have become more and more integrated. It is becoming more sophisticated.

For example, peripheral devices such as timer counters, A/D conversion circuits, serial transmission/reception circuits, and the like are provided with multiple channels and are becoming more sophisticated.

For this reason, it is necessary for the central processing unit (hereinafter referred to as CPU) to not only execute and control data processing based on command operations at high speed, but also to execute and control data processing efficiently and at high speed in response to processing requests from peripheral devices, etc. is occurring.

Conventionally, a method called an interrupt has been widely used as a means for a CPU to start and control execution of data processing at high speed in response to a processing request from a peripheral device or the like.

When the CPU detects a processing request that is generated asynchronously from a processing request source such as a peripheral device, an interrupt interrupts the currently executing program and transfers control to the interrupt service program routine that processes data corresponding to the processing request. It is.

In interrupt processing, registers, program counters (hereinafter referred to as PC), status words (hereinafter referred to as PSW), etc. are saved in a memory section called a stack so that the original program processing can be resumed normally. When the routine of the interrupt service program ends, information such as registers, pc, psw, etc. saved in the stack by instruction processing is recovered and the original program execution is resumed.

Additionally, by providing multiple peripheral hardware, multiple processing requests occur simultaneously, often resulting in a competitive situation. For this reason, in an SMC equipped with an interrupt processing system,
The configuration is such that a priority is set for each geographic request, and the interrupt request control unit judges the conflicting state based on this priority, selects only one processing request with the highest priority, and transmits it to the CPU as an interrupt request. Take.

On the other hand, depending on the content of the program, you may want to prohibit acceptance of interrupt processing6.For example, if another interrupt service program is already being executed, the interrupt service program processing that is already being executed has the highest level of urgency. This may be the case when it is desired to avoid the stack becoming deeper than accepting new interrupts due to time constraints or stack capacity constraints.

For this reason, an SMC equipped with an interrupt processing system is equipped with an interrupt enable flag (EI) to control execution of interrupt processing requests. Prohibiting and enabling execution control using interrupts is performed to configure a system suitable for the target application equipment.

Note that in order to distinguish between an interrupt request from a peripheral device or the like to the interrupt request control section and an interrupt request from the interrupt request control section to the CPU, an interrupt request from a peripheral device or the like will be simply referred to as a processing request.

Next, an interrupt processing system in a conventional SMO will be explained using a specific example.

FIG. 4 is a block diagram showing the main parts of an interrupt processing system in a conventional SMC, which consists of the following components.

The interrupt request control unit l includes an interrupt request flag register IFR that includes an interrupt request flag 11 that stores the occurrence of processing requests 80 from various peripheral devices.
(hereinafter referred to as IFR) 101, a priority control unit 102 that performs priority control based on the flag contents of IFRIOI corresponding to each processing request, a vector code constant unit 103 containing vector information corresponding to each processing request, Interrupt request INTRQ6 (hereinafter INT
RQ6) is generated to prompt the start of interrupt processing, and
Interrupt acknowledge signal INTACK7 from CPU2
(hereinafter referred to as INTACK7), various control logics control the operation of outputting predetermined vector information to the bus 5 and the operation of clearing the request flag in the IFRIOI that has accepted the processing request. Each register is read/write controlled by the CPU 2 via the bus 5.

CPU2 is Internal PC, PSW, ALU, instruction decoder.

Execution control of various instructions and interrupt processing control, including various control registers, interrupt enable flag EI (hereinafter referred to as EI), etc., and including the operation of detecting INTRQ6 of interrupt request control unit 1 and controlling interrupt request control unit 1. SM required for execution
Controls the entire operation of C.

The memory unit 3 includes a program memory, a data storage area for instruction execution results by the CPU 2, and pc, psw,
CP includes a stack used for saving registers.
Data is input/output via bus 5 under the control of U2.

FIG. 5 shows the IFR 101 of the interrupt request control unit 1 in FIG.
2 is a block diagram showing an outline of the configuration of a priority control unit 102. FIG.

Here, for simplicity, the processing requests are 3 sources (8a.

8b and 8c) are shown.

IPRIOI are interrupt request flags lla and llb.

11c, and each interrupt request flag corresponds to each processing request 8a, 8b from a processing request generation source such as a peripheral device.
, 8c from the h1 priority control unit 102 and the flag selection signals 10a, 10b, 10c from the CPU and INTAC! 7.

If multiple processing requests occur simultaneously, the priority control unit 102 selects only one processing request with the highest priority among them, and sends a flag selection signal 10a to IFRIOI and the vector code constant unit 103 in FIG. , 10b, 10c, and transmits the selection signal for the processing request selected first from among them, and at the same time sends INTRQ6 to the CPU2.
It is composed of various control p-switches for performing operations such as prompting the activation of interrupt processing.

Here, the priority order of processing requests is fixed by hardware in the order of processing request 8a>processing request sb>processing request 8c, and when processing requests 8a, 8b, and 8c occur simultaneously, the processing request with a higher priority is always requested. 8a is selected.

The flag selection signals 10a, 10b, and 10c are held until INTACK7 is transmitted from the CPU 2 in FIG. 4.

Next, the interrupt processing operation will be explained using FIGS. 4 and 5.

First, a case will be described in which the EI EFF flag is set in advance by instruction processing in the CPU 2, interrupt request reception is enabled, and predetermined program processing is executed while checking the occurrence of INTRQ6.

When an interrupt request occurs in each processing request generation source due to a timer counter overflow operation or a serial data transmission/reception operation, each processing request generation source generates a processing request 8 and interrupts the interrupt included in the IPRIOI in the interrupt request control unit 1. Set the request flag.

The priority control unit 102 in the interrupt request control unit 1 performs priority control based on the contents of each interrupt request flag, and
Set NTRQ6 to 7 tapes and send interrupt processing requests to the CPU.
Tell 2.

Since the CPU 2 has the EI flag set and is enabled to accept interrupt requests, when INTRQ6 becomes active, it interrupts the program processing in progress and stores the contents of the pc, psw, and various registers in the memory section via the bus 5. 3 and sends an INTAC to the interrupt request control unit l.
IFRIOI that transmits K7, outputs vector code information of the interrupt service program, and responds to processing requests.
Clear the interrupt flag.

Next, the CPU 2 branches to the interrupt service program based on the obtained vector code information, sets the EI E-flag interrupt disabled state, and performs predetermined execution control corresponding to the processing request through program processing. While the interrupt service program is being executed, the EI flag is normally set to the interrupt disabled state, so other processing requests are held pending with the interrupt request flag set until the interrupt service program ends.

When the interrupt service program ends, the p saved in the stack of the memory unit 3 by executing a dedicated return instruction (RETI instruction, etc.) from the interrupt service program.
The contents of the c, pws, and registers are restored, and the E-flag is returned to the interrupt enabled state again to return to the program processing where execution was interrupted.

[Problem that the invention seeks to solve]

In the conventional SMC described above, the priority order of processing requests is fixed.

Furthermore, there is no hardware-based means for counting the number of times a processing request has occurred.

Therefore, if there is a conflict between a processing request with a higher priority and a processing request with a lower priority, the processing request with a lower priority will always be interrupted by the interrupt service program of the processing request with a higher priority. Execution of interrupt processing is suspended until it is completed.

For example, considering the waiting time from when a processing request with the lowest priority is generated until the corresponding interrupt service program starts processing, as the number of SMC peripheral hardware and processing request generation sources increases, other Since the possibility that processing requests will occur simultaneously increases, there is also a high possibility that the start and execution of the processing of the interrupt service program corresponding to the processing request set with the lowest priority will be suspended for a longer period of time. In addition, there is a high possibility that a new processing request with a higher priority setting will occur until the interrupt service program for a certain processing request is finished, resulting in a longer hold time and the necessary processing control. , there was a problem that the execution would not be carried out forever.

In addition, as described above, if a processing request is suspended for a long time, a processing request may be generated again from the same processing request source, but the interrupt request flag in the conventional SMC is Since the function is only to store the occurrence of a processing request and it is not possible to store the occurrence of a plurality of processing requests, it is not possible to detect the occurrence of a new processing request. Therefore, in the case of a system in which the increment process of a software timer (counter) is executed by an interrupt service program, there is a drawback that a counting error occurs.

In order to avoid such problems, conventionally, data processing efficiency has been sacrificed to some extent to create a system with enough margin between the occurrence of one processing request and the next processing request, or It was necessary to strictly calculate the maximum pending time until starting an interrupt process for all possible cases, and to design an appropriate application system to prevent the same processing request from occurring again during the pending period.

However, as SMCs have become more multi-functional and faster in response to the demands for realizing advanced application systems, it has become difficult to design them in consideration of appropriate processing request hold times.

Furthermore, in order to optimize the hold time from the generation of a processing request to the execution of interrupt service program processing according to the execution status of the program processing, an interrupt control system is adopted that allows the priority of processing requests to be arbitrarily set using software means. There are also SMCs that have done so. ,However, there is always a processing burden to monitor the execution status of the program.
- During the period from when the priority of a processing request is set by software means until the next time the priority of a processing request is set or changed, the priority of the processing request set to the lowest priority is This has the same drawbacks as the SMO with a hardware-fixed interrupt control system, and is no longer effective in reducing the pending time of processing requests.

[Contents of Differences between the Invention and the Prior Art] The SMO according to the present invention includes, in an interrupt control unit, an N-bit interrupt request counter that counts the number of times an interrupt request signal is generated from an interrupt request source; control means for selectively specifying the priority of the interrupt request based on the content of the interrupt request.Compared to conventional SMC, the same processing request does not occur again during the period in which the processing request is suspended. In addition, even if the processing request is set to a low priority, if the same processing request occurs multiple times, the priority of the processing request is automatically raised by hardware means. The difference is that it prompts startup and enables necessary data processing.

[Means for solving problems]

The single-chip microcomputer according to the present invention includes an N-bit interrupt request counter that corresponds to a plurality of interrupt request generation sources and stores the number of times an interrupt request signal has been generated from the interrupt request generation sources, and a and control means for selectively specifying the priority of the interrupt request.

[Example-1] Next, a first example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of the SMC interrupt control system according to the present invention, and is composed of the following components.

The interrupt request control unit 1 includes an interrupt request register IFR 201 (hereinafter referred to as IF'R 201) including an interrupt request counter 9 that stores the generation of processing requests 8 from processing request sources 4 such as various peripheral devices, and an interrupt request register IFR 201 (hereinafter referred to as IF'R 201). A priority control unit 102 that determines the priority order based on the contents of the corresponding interrupt request counter, a vector code constant unit 103 that includes vector information corresponding to each processing request, and an interrupt request INTRQ6 (hereinafter IN
TRQ6) is generated to prompt the start of interrupt processing, and an interrupt acknowledge signal INTACK from CPU2 is generated.
7 (hereinafter referred to as INTACK), various control logics that control the operation of outputting predetermined vector information to the bus 5 and the operation of clearing the interrupt request counter in the IFR 201 that has accepted or accepted the processing request. including.

The IFR20 register can be read/written by the CPU 2 via the bus 5.

The CPU 2 internally includes a PC, a PSW, an ALU, an instruction decoder, various control registers, an EI flag, etc., and detects INTRQ6 of the interrupt request controller 1 and outputs the interrupt request controller 1.
The SMC controls the entire operation of the SMC, which is necessary for controlling the execution of various instructions and controlling interrupt processing.

The memory unit 3 includes a program memory, a data storage area for instruction execution results by the CPU 2, and a stack used for saving PC, psw, and registers when starting an interrupt process, and uses the bus 5 under the control of the CPU 2. Data input/output is performed through.

Figure 2 shows the IFR 201 and priority control unit 102 in Figure 1.
FIG. 2 is a block diagram showing the configuration of.

Here, three processing requests 8a and 8b are used for explanation.

2-bit interrupt request counter 9a corresponding to 8c.
, 9b, and 9c will be described.

Note that the interrupt request counters 9a, 9b, and 9c are constructed of the same hardware and have equivalent functions, so only the interrupt request counter 9a will be described here. Also, signals necessary for read/write control by CPTJ2 in FIG. 1 are omitted.

The interrupt request counter 9a counts up every time the processing request 8a becomes active, and is decremented by a counter decrement signal 120a.

Two types of request signals are generated depending on the counter value of the interrupt request counter 9a.

The first is a lower level request signal 122a from the interrupt request counter 9a, which becomes active when the normal processing request 8a is input once, and is transmitted to the priority control circuit 102.

The second is an upper level request signal 121a from bit 1 of the interrupt request counter 9a, which becomes active when the processing request 8a is input two or more times, and is activated by the priority control circuit 1 of FIG.
This will be communicated to 02.

The priority processing in the priority control unit 102 is as follows: upper level request signal 121a>upper level request signal 12l
b>upper level request signal 121c>lower level request signal 122a>lower level request signal 122b>lower level request signal 122c, which is uniquely determined.

Further, the counter designation lines 10a, 10b, and 10c are configured such that one of them becomes active exclusively, so that when either the upper level request signal 121a or the lower level request signal 122a corresponding to the priority control circuit 8a becomes active, the counter designation lines 10a, 10b, and 10c are activated. 10a becomes active. Similarly, the upper level request signal 121b or the lower level request signal 122b
When becomes active, the counter designation line 10b becomes active, and the counter designation line 10c becomes active even if either the upper level request signal 121c or the lower level request signal 122C becomes 7 times.

Counter designation lines 10a, 10b, 10c and INTACK
7, the write interrupt request counter 9a corresponds to the processing request.
, 9b, 9c counter decrement signals 120a, 1
20b and 120c are designated.

Next, the operation will be explained using FIGS. 1 and 2.

First, all interrupt request counters are in the initial state “0”.
A case where the CPU is set to the EI EFFRAG interrupt enabled state and a plurality of processing requests, processing request 8a and processing request 8b, are generated at this time will be described.

At this time, IFR201 corresponding to processing requests 8a and 8b
The interrupt request counters 9a and 9b are both incremented by 1, and the lower level request signals 122a and 122b become active and are transmitted to the priority control unit 102. Here, the priority order for accepting processing requests is processing request 8&> processing request 8b, that is, lower level request signal 122a>lower level request signal 1
22b, the processing request 8a is selected and the counter designation line 10a is activated, and the IN
Activate TRQ6 and inform CPU2.

The priority control unit 102 receives the INTACK from the CPU 2.
The level of the counter designation line is held until 7 is transmitted.

When INTRQ6 becomes active, the CPU 2 interrupts the program processing being executed and sends pc and psw.

The contents of various registers are saved to the stack of the memory section 3 via the bus 5, and the INTA is sent to the interrupt request control section 1.
It transmits CK7 and outputs the vector code information of the interrupt service program corresponding to processing request 8a,
The counter decrement signal 120a is activated and the interrupt request counter 9a in the IFR 201 is decremented by one.

The value of the interrupt request counter 9b remains 1 and does not change.

Next, the CPU 2 branches to the interrupt service program based on the obtained vector code information, and after setting the E-flag to an interrupt disabled state, the CPU 2 issues a processing request 8a through program processing.
When the 0-interrupt service program that performs predetermined execution control corresponding to the interrupt service program ends, the pc, psw,
At the same time as restoring the contents of the registers, the EI ef flag is returned to the interrupt enabled state and the program processing where execution was interrupted is resumed.

Second, when the processing request 8b has already occurred once and the interrupt request counter 9b is "1", that is, when the lower level request signal 122b is already active but is pending, multiple processing requests A case where 8a and 8b occur again will be explained.

At this time, the interrupt request counters 9a and 9b are incremented by 1 due to the processing requests 8a and 8b, and the lower level request signal 122a is active and the upper level! ' Request (No. 1
21b becomes active and is communicated to the priority control 102.

Here, the priority for accepting processing requests is processing request sb>
Since the priority order is processing request 8a, that is, upper level request signal 12lb>lower level request signal 122a, processing request 8b is selected and counter designation line 10b becomes active.

Next, INTRQ6 becomes active and prompts the CPU2 to start interrupt processing. Since the CPU2 is in the EI EFFRAG interrupt enabled state, when INTRQ6 becomes active, it interrupts the program processing being executed and transfers the contents of the PC, PSW, and registers to the bus 5. is saved to the stack of memory unit 3 via INTACK to interrupt request control unit l.
7, outputs the vector code information of the interrupt service program corresponding to the processing request 8b, and activates the counter decrement signal 120b.
The interrupt request counter 9b in R201 is decremented by 1. The value of the interrupt request counter 9a remains unchanged at "1" and is held pending.

In the interrupt service program, the CPU 2 reads the contents of the interrupt request counter 9b, and since the value is not "0", it is possible to detect that the processing request 8b has occurred again while the processing request 8b is pending.

The subsequent interrupt service program processing, return processing to the interrupted program processing, and interrupt processing for the suspended processing request 8a are the same as in the first explanation.

- As mentioned above, depending on the count of the interrupt request counter,
In order to automatically raise the priority of the corresponding processing request, even if it is possible to solve the problem of the conventional SMC where processing requests are held on hold and processing due to interrupts is not executed forever, processing requests may be issued multiple times. When a processing request occurs, the priority is raised and the priority control unit performs processing control in the same way as when a high-level processing request occurs, thereby shortening the pending time of the processing request.

Furthermore, by counting the number of times a processing request has occurred using an interrupt request counter, it is possible to detect that a processing request has occurred multiple times and the number of times that a processing request has occurred.

Therefore, for example, in the case of a system in which the increment process of a software timer (counter) is executed by an interrupt service program, a normal count value can be obtained by correcting the count number from the value of the interrupt request counter 9b.

The above is the first embodiment of the present invention.

[Embodiment 2] Next, a second embodiment of the SMO according to the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing the main parts of the interrupt request control unit l in the second embodiment of the SMC according to the present invention. Flags 202a, 202b, 20
The present invention is applied to an SMC having a priority order designation register 202 including 2c.

That is, the difference from the first embodiment is that, as is clear from FIG. 3, the interrupt request control section 1 has a priority order designation register 202 in addition to the components in the first embodiment. Since the other components are the same, their explanation will be omitted here.

For the sake of explanation, interrupt request counters 9a, 9b, 9c corresponding to three processing requests 8a, 8b, 8c, respectively, and priority designation flags 202a, 202b in the priority designation register 202, as in the first embodiment. , 202c will be described.

It should be noted that the interrupt request counters 9a, 9b, 9c and the priority order designation unit 102 are constructed of the same hardware as in the first embodiment, and their functions and operations are equivalent, so the priority order designation flag will be explained here. Also, signals necessary for read/write control of each register designation section by the CPU are omitted.

Priority designation flags 202a, 202b, and 202C are C
Read/write is possible from the PU 2 via the bus 5, and the content of the flag corresponding to the processing request is specified in advance by software processing as "1" = upper level request or "0" = lower level request.

By selectively specifying the priority of the corresponding processing request as an upper-level request or a lower-level request through the above processing, interrupt processing can be executed more flexibly in accordance with the operation contents of the SMC.

In the second embodiment, as in the first embodiment, the priority of the processing request is automatically designated as a higher level request by hardware means according to the number of occurrences of the processing request based on the contents of the interrupt request counter. In addition, in the interrupt service program, the CPU 2 can read the contents of the interrupt request counter and detect whether the same processing request has occurred again while the processing request is pending and the number of times the same processing request has occurred. Therefore, the same effects as the first embodiment can be obtained.

In addition, since the hardware of the priority control unit 102 required for control using conventional priority designation flags can be used as is, the amount of additional hardware is limited to the interrupt request counter and the upper level requests from the interrupt request counter. Only a simple gate circuit is required to create the logical sum of the signal and the higher level request signal from the priority designation flag.

The above is the second embodiment of the present invention.

Note that although the detailed explanation of the present invention has been made assuming that there are three sources of processing requests, that the number of bits of the interrupt request counter is 2 bits, and that the priority level is controlled at two levels: upper level and lower level, The source can be any source,
Furthermore, it goes without saying that the number of bits of the interrupt request counter and the number of priority control levels are not limited to the numbers in Example-1 and Example-2.

〔Effect of the invention〕

As mentioned above, the SMC of the present invention automatically raises the priority of the corresponding processing request based on the count number of the interrupt request counter. Because the priority was set low, the processing request was put on hold.
Sakaki has resolved the drawback that interrupt processing is not executed forever.

Further, by counting the number of times a processing request has been generated using an interrupt request counter, it is possible to detect that a plurality of processing requests have been generated and the number of times that a processing request has been generated.

Therefore, like SMe with a conventional interrupt control system, it is possible to sacrifice some data processing efficiency to create a system that has enough margin between the occurrence of one processing request and the next processing request, or There is no need to strictly calculate the maximum pending time until starting interrupt processing in response to a request for all possible cases, which reduces the burden on application system design. For example, it becomes possible to perform a process of incrementing a software timer (counter) and correcting it from the interrupt request counter value to obtain a normal count value.

Furthermore, when applying the present invention to an SMO that has conventional priority control processing hardware, the hardware for priority control can be used with almost no changes, and the minimum necessary circuit can be used. Since it is only necessary to add an SMC, it is possible to provide an SMC with good cost performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of the SMO interrupt control system in the first embodiment of the present invention, and FIG. 2 shows the IFR 201, priority control unit 102, and
FIG. 3 is a detailed block diagram of the SM'C IFR201 in the second embodiment.
, priority control unit 102, priority specification register 202
FIG. 4 is a block diagram showing main parts of an interrupt processing system in a conventional SMC. FIG. 5 shows the IPR of the interrupt request control unit 1 shown in FIG. 201 and a detailed block diagram showing the configurations of the priority control unit 102. FIG. 1...Interrupt request control unit, 2...Group/CPU,
3...Memory unit, 4...Processing request source, 5...Bus, 6...-INTRQ, 7
- Old...INTACK, 8.8a. 8b, 8c...processing request, J9a,
9 b, 9 c...Interrupt request counter, 1
0a, 10b, 10C...Counter designation line, 1
1. lla, llb. 11c...Interrupt request flag, 101, 201
...IFR%102...Priority control unit, 120a. 120b, 120c... Counter decrement signal, 121a, 121b, 121cm upper level request signal line, 122a, 122b, 122c...
lower level request signal lines, 202a, 202b; 202c...Priority designation flag, 202...
...Priority specification register. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Scope of Claims] An N-bit interrupt request counter that stores the number of times an interrupt request signal is generated from an interrupt request source in a single-chip microcomputer that has a central processing unit, a memory section containing programs and data, and an interrupt control circuit. A single-chip microcomputer comprising: a control means for selectively specifying a priority order of interrupt requests based on the contents of the interrupt request counter.