JPH01183267A - Picture processor - Google Patents

Abstract

PURPOSE:To dispense with the re-editing of attribute data even if a read scale factor is changed by changing the generating timing of an address signal for reading the attribute data correspondingly to a set scale factor. CONSTITUTION:Respective data held in picture data memories 15, 17, 19 is outputted as responding to a first address signal, and is supplied to a color processing part 47. On the other hand, an attribute memory 51 holds previously the attribute data respectively in plural addressable storage areas corresponding to each of plural scanning sections obtained by dividing the scanning range of a picture data generating part, and the attribute data is outputted as responding to a second address signal, and is supplied to the color processing part 47. Because at the time of picture generation by the variable scale factor, the second address signal to be supplied to the attribute memory 51 is changed correspondingly to the scale factor, the attribute data too is read out, for instance, intermittently or repeatedly. Consequently, the attribute data corresponds to a picture part even at the time of the variable scale factor, and the attribute data set at the time of an equal scale factor can be used at the time of the variable scale factor as well without rewriting it.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image processing device, and in particular to an image processing device that can perform various editing operations based on data held in an attribute memory, such as a digital color copying device. Regarding machines.

[Prior Art] Conventionally, digital copying machines have been equipped with methods such as prohibiting the output of a portion of digital image data obtained by scanning an image and prohibiting reproduction of that portion of the image on paper, or controlling the brightness of an image on a document. It is possible to reproduce a so-called white image on paper by reversing the image.

Such editing work is performed on an image memory that stores one page of manuscript images.

[Problems to be Solved by the Invention] With conventional image processing devices equipped with such editing functions, it is not possible to edit on one page of image memory, or the memory for one page of a manuscript is large in capacity and expensive. be.

Therefore, instead of having an image memory for one page, it may be possible to store the attributes of image data in an attribute memory, edit the image data in real time according to the attribute data, and output the image data. However, the problem is that the attribute data in the attribute memory is edited based on the original image data at the specified reading magnification, and even if the original is the same, the attribute data must be re-edited when the reading magnification is changed. There was a point.

Therefore, an object of the present invention is to provide an image processing apparatus that does not require re-editing attribute data even when the reading magnification is changed.

[Means for Solving the Problems] The present invention focuses on the fact that attribute data set at a predetermined magnification can be used as is when changing the magnification by making the image data read address signal and the attribute data read address signal correspond to each other. The gist of this is that it includes an image data forming section that scans a document line by line and sequentially outputs image data representing each part of the image on the document, and the ability to rewrite each of the above image data line by line. and a plurality of addressable image data memory corresponding to each of a plurality of scanning areas obtained by dividing the scanning range of the image data forming section. an attribute memory having a storage area, each of which stores attribute data in the plurality of storage areas, and outputs the attribute data in response to a second address signal; and an attribute memory that is represented by image data read from the image data memory. a processing unit for changing the attributes of the portion of the image that has been changed according to the attribute data; a means for setting a magnification; That's what I did.

[Operation of the Invention] When an image drawn on a document is created at the same magnification using the image processing apparatus according to the above configuration, the image data forming section scans the document and generates an image representing each part of the image on the document. Data is sequentially output, and each image data supplied from the image data forming section is made rewritable in the image data memory. Each image data stored in the image data memory is outputted in response to the first address signal and supplied to the processing section.

On the other hand, the attribute memory stores attribute data in a plurality of addressable storage areas corresponding to each of a plurality of scanning areas obtained by dividing the scanning range of the image data forming section, and the attribute data is stored in a plurality of addressable storage areas. 2 is output in response to the address signal and supplied to the processing section. At the same magnification, the second address signal advances in response to the second address signal, so the processing section changes the attributes of the image portion represented by the image take read from the image data memory according to the attribute data. Change it and submit it for image creation. As mentioned above, since the second address signal advances in response to the first Adsinos signal, the attribute data supplied to the processing section corresponds to the instruction for the attribute of the image portion on the document. You can change the attributes of each part of the image on the document to any desired attribute.

On the other hand, when reducing or enlarging an image represented by image data supplied from the image forming section, for example, the image data from the image data memory may be read out intermittently,
It is necessary to control the image formation by performing redundant reading, and therefore it is necessary to change the generation of the first address signal. When forming an image at such a variable magnification, the second address signal supplied to the attribute memory is changed in accordance with the magnification, so that the attribute data is also read out, for example, intermittently or in duplicate. As a result, the attribute data corresponds to the image portion even when the magnification is changed, and the attribute data set when the magnification is constant can be used even when the magnification is changed without being rewritten.

[Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention. In the figure, reference numeral 1 denotes an image sensor composed of three rows of CCD elements, and the three rows of CCD elements constituting the image sensor 1 are respectively covered with red, green, and blue filters. In the following description, the column direction of the CCD elements will be referred to as the main scanning direction, and the direction perpendicular to the main scanning direction, that is, the scanning direction of the original (not shown) will be referred to as the sub-scanning direction.

As described above, the image sensor 1 receives the reflected light from the fluorescent lamp 2 through the red, green, and blue filters that illuminates an original (not shown) on which a color image is drawn, and receives the reflected light from the fluorescent lamp 2 through the red, green, and blue filters. Anacog color signals R, G with voltages corresponding to the respective intensities of the red component, green component, and blue component in the reflected light,
Output B.

These analog color signals R, G, and B are respectively supplied to the A/D converter 3.5.7, and the A/D converter 3.5.7 periodically converts the analog color signals R, G, and B. Digital color signals DR, DG consisting of multiple bits of values corresponding to sampled voltage values,
Form a DB. A/D converter 3, 5. 7 receives the reference voltage ■r e f R, V r from the central processing unit 39.
e f G and V r e f B, and the central processing unit 39 supplies reference voltages VrefR and V'refG so that the maximum value is constant for each color.

Set VrefB. These digital color signals DR, DG, DB are sent to the shading circuit 9.11.
．． 13, the shading circuit 9.11.13
is a digital color signal D corrected by correcting errors caused by uneven light emission of the fluorescent lamp 2 and variations in characteristics of the CCD element.
R, DG, and DB are supplied in parallel to the variable power line ram 15, 17, and 19. Therefore, in this embodiment, the image sensor 1, the fluorescent lamp 2, the A/D converter 3. 5. 7
The shading circuits 9, 11, and 13 as a whole constitute an image data forming section. Further, the zooming line rams 15, 17, and 19 as a whole constitute an image data memory.

Line ram 15.17.19 for variable magnification is addressable 2
two memory circuits 1, i.e. the first memory circuit 21.23.2
5 and the second memory circuit 27. 29. 31, respectively, and each memory circuit 21, 23, 25, 27, 29 .
31 is a digital color signal DR, DC consisting of multiple bits.
, has a storage capacity that can store multiple DBs. The line rams 15, 17, and 19 for variable magnification have digital addresses (
Holds the words DR, DG, and DB. The write address generator 33 forms a write address signal A D W based on the clock signal CKA supplied from the clock generator 35, and the write address signal A
DW advances in synchronization with the clock signal CKA while the first memory circuit 21. 23. 25 is a digital color signal D
R, DG, and DB are sequentially written, and then, in response to the main scanning synchronization signal (syncC), the first memory circuit 21.
23. Switch the 25 to read mode and now read the second
Write address signal A to memory circuits 27, 29, and 31
Since it supplies DW, the shading circuit 9.11.1
3 to line rams 13, 15, and 17 for magnification; digital color signals DR and DG are supplied in parallel here.

DB is hereinafter referred to as the second storage circuit 27. 29. 314 entries are written. On the other hand, line ram 15.
17.19 first memory circuit 21. 23. Digital color signals DR, DG, DB written in 25;
In response to the read address signal ADR generated by the read address generator 37, the second memory circuit 2
Digital color signals DR, DG, DB to 7.29.31
is read in parallel with writing. Second memory circuit 27
．． When the writing of digital color signals DR, DG, DB to 29.31 is completed, the second storage circuit 27.29.31
is in read mode, and the first storage circuit 21.23.2
5 is in the write mode again, so the digital color signals DR, DC, DB are now stored in the first storage circuit 21.23.2.
At this point, the digital color signals DRS DG, DB written in the DRS 5 and held in the second storage circuit 27, 29, 31 are read out.

As shown in 2, the first memory circuits 21, 23, 25 and the second memory circuit 2 constitute the variable power line rams 15, 17, 19.
7, 29.31 are alternately switched between the write mode and the read mode in response to the main scanning synchronization signal Hsync, so the first storage circuit 21.23.25 and the second storage circuit 27. Digital color signal DR on either side of 29°31.

The digital color signals DR, DG, DB preceding the digital color signals DR, DC, DB being written are stored in the first storage circuit 21.23.25 and the second storage circuit 27.25. 29. 31.

The read address generator 37 generates the read address signal ADR as described above, and the read address signal ADR is a clock signal at the time of enlargement based on the instruction indicated by the variable magnification signal VR supplied from the central processing unit 39. It is also possible to walk on the sidewalk at a timing when the CKA is thinned out at a predetermined ratio. The read address generator 37 further generates a latch timing clock CKB that instructs a latch circuit, which will be described later, to latch, and the period of this latch timing clock CKB is lengthened based on the variable magnification signal VR when the magnification is reduced.

That is, the read address generator 37
It is equipped with a latch timing generation circuit as shown in detail in the figure, and this latch timing generation circuit is connected to the adder 3.
7-1 and the output of this adder 37-1 as a clock signal CK.
The adder 37-1 has a latch circuit 37-2 that latches in synchronization with A, and a set value based on the variable magnification 1 word VR is supplied to one input A of the adder 37-1, and the input B of the other input is supplied with the output of the latch circuit 37-2. The latch timing clock CKB is obtained from the carry output C of the adder. For example, the magnification ratio signal V R is a reduction of 1/n of the original image.
When N/n (for example, 5) J (Nun) is supplied to one input A based on this variable magnification signal VR, the first clock signal CKA causes the latch circuit 3 to
7-2 latches "5" and supplies it to the other input B of adder 37-1. As a result, the adder 37-1 receives "5" supplied to one input of A and "5" supplied to the other input.
", and "10" appears in the output. This output “10” is the second clock signal CKA and the latch circuit 3
7-2. Thereafter, the adder 37-1 calculates the sum as "
5'', and when a carry occurs, this is used as the latch timing clock CKB by the latch circuit 41. Supplied at 43°45. However, if N/n' (for example, "2") is supplied to one input A of the adder 37-1 based on the variable magnification signal VR, the sum of the adder 37-1 increases by "2". Therefore, the generation cycle of the latch timing clock CKB becomes longer.

Therefore, if the number of increases in the sum at the time of equal magnification is appropriately selected, the latch timing clock CKB at the time of reduction can be generated based on the variable magnification signal VR. These latch timing clock CKB and read address signal AD
The relationship with H will be detailed later.

Returning again to FIG. 1, the description of one embodiment will be continued.

The line rams 15, 17, and 19 for variable magnification are latch circuits 41.
43 and 45, and these latch circuits 41 and 43+40 are connected in parallel to the scaling line rams 15 and 17 in response to the above-mentioned latch timing clock CKB supplied from the reading address generator 37.
．． Digital color signals DR, DG, D output from 19
The digital color signals DR, DG, and DB latched by the latch circuits 41, 43, and 45 are sent to the color processing circuit 4.
7 in parallel.

Based on the readout address signal ADR generated by the readout address generator 37, the digital color signals DR, DG, and DB read out from the scaling line rams 15, 17, and 19 are actually supplied to the color processing circuit 47. The correspondence relationship between the digital color signals DR, DC, and DB will be explained in detail with reference to FIG. 3. Figure 3 shows the variable magnification signal V
Read address 1 word ADR and latch timing clock CK when specifying 0° 5x, 1x, 2x with R
It is a graph showing the change from B. When the main scanning synchronization signal Hsync is supplied from the clock generator 35,
The write address generator 33 and the read address generator 37 are reset, and thereafter the clock signal CKA supplied from the clock generator 35
In response to this, the write address is sequentially incremented, and as a result, a write address signal A D W representing the sequentially incremented write address is also output in synchronization with the clock signal CKA. On the other hand, the read address signal ADR increments the address based on the instruction indicated by the variable magnification signal VR. That is, the read address advances in synchronization with the clock signal CKA during the same magnification and reduction, and during enlargement, it advances in time in response to the enlargement factor (for example, 2x) indicated by the variable magnification signal VR. Step forward at the timing of the pull. On the other hand, the latch timing clock CKB is output in synchronization with the clock signal C (Clock signal C) (A) during the same magnification and enlargement, or the variable magnification signal V during the reduction (for example, 0.5 times).
It is output in a long cycle based on the instruction shown in R.

Therefore, at the same magnification, the line ram for variable magnification is 15.17
．． Digital color signals DR, DG, held in 19
DB is read out at the same timing as the clock signal CKA, and all digital color signals DR, DG, and DB read out from the variable magnification line ram 15°17.19 are sent to the latch circuit 41. The color processing circuit 47 is latched at 43°45.
Supplied here.

However, at the time of reduction, the readout address advances in synchronization with the clock signal CKA, so the digital color signals DR, DG, and DB held in the scaling line RAMs 15, 17, and 19 are output at the same timing as when the magnification is the same. The latch timing clock CKB is read out at 1/2 of the clock signal CKA (0,
The line ram 15 for variable magnification is thinned out at 5x).
, 17. Digital color signal DR output from 19.

DG and DB are intermittently connected to the latch circuit 41. 43. 45
latched to. Therefore, in the case of 1/2 reduction, the color image drawn on the document is sent to the color processing circuit 47 every other pixel in the main scanning direction, and the image reproduced on the paper is reduced to 1/2 of the original image. Ru.

On the other hand, when the original image is enlarged to 2 times, for example, the read address advances at 1/2 the speed of the original image, so the read address signal ADR increases by 2 clocks of the clock signal CKA. It will show the same address for a period of . On the other hand, since the latch timing clock CKB is output at the same period as the clock signal CKA, the same digital color signals DR, DG, and DB are latched twice in succession by the latch circuit 41°43.45. , the original image will be enlarged twice in the main scanning direction.

Note that reduction or enlargement in the sub-scanning direction when changing the magnification is performed by changing the relative scanning speed between the original and the image sensor 1. That is, when reducing the original, the relative movement speed between the original and the image sensor 1 is increased. Since the synchronization signal Hs yn c in the main scanning direction is generated at regular intervals, the distance that the image sensor 1 moves during one main scan is large, and on the other hand, the distance that the printing device moves during image formation increases. Since is constant, the image will be reduced. On the other hand, when enlarging a document, the document and image sensor 1
Decrease the relative movement speed with. As mentioned above, the main scanning synchronization signal Hsync is generated at regular intervals, so 1
The distance that the image sensor 1 moves during each main scan is reduced, and if the image is created by a printing device whose moving distance is constant, an enlarged image will be obtained.

Again, in FIG. 1, the color processing circuit 47 converts the digital color codes DR, DG, and DB according to a predetermined procedure by performing masking processing in accordance with the ink characteristics of the output printing device (not shown). A monochrome image obtained by averaging the color density or weighted average of the color mode signal CL representing the ink amounts of ink Y, macenta ink M, and cyan ink C, and the data regarding the ink amounts of the above three colors expressed as the color mode signal C. A mode signal MN is formed. These color mode signal CL and monochrome mode signal MN are supplied to the selector 49, and the selector 49 selects the color mode signal CL and monochrome mode based on the fourth bit of the attribute control signal AT output from the attribute memory 51, which will be described in detail later. Signal M
Either one of N and N is sent to the comparison circuit 53. This attribute control signal AT is an 8-bit signal representing attribute data to be described later, and the attribute data is held at each address of the attribute memory 51.

To be more specific, the attribute memory 51 has addresses corresponding to minute ranges obtained by dividing the scanning range of the document into units of, for example, 1 square millimeter, and 8-bit attribute data is written in each address by the central processing unit 39. ing. Further, in response to the read address signal ADX supplied from the selector 56, the attribute data held at the address represented by the read address signal ADX is output. The selector 56 is the central processing unit 3
Write address signals AD to V based on instructions from
Alternatively, the read address signal ADH is selectively passed through and is supplied to the attribute memory 51 as the read X address signal ADX. The attribute control signal AT output from the attribute memory 51 is latched into the latch circuit 54 by the latch timing clock CKB.

Latch circuit 4L As previously explained in connection with 43.45, when reducing, the read digital color signal D
R, DG, and DB are intermittently latched, and during enlargement, the read address ADH holds the same value for a long period of time, so the digital color signal DR.

DG and DB are latched redundantly. Similarly, the attribute control signal AT is also intermittently latched by the latch circuit 54 during reduction, while the same X address is held for the duration of a plurality of clock signals during expansion, so the attribute control signal AT represents the same attribute data. The AT can be read out redundantly, and the attribute data can be used as is without being rewritten even when copying the original image at variable magnification. In this embodiment, since the attribute data is set for each square millimeter, the number of attribute data is smaller than the number of digital color signals DR, DC, and DB obtained for the same image portion. Therefore, the X address signal ADX uses only the upper hit of the read address signal ADH.

On the other hand, the Y address signal ADY is output from the address generator 5.
2 to the attribute memory 51. As shown in detail in FIG. 4, this address generator 52 includes an initial value setting circuit 52-1, and a counter δ2-1 that increases the initial value supplied from the initial value setting circuit 52-1 using a clock signal CKA. 2, and a counter 52-3 that sequentially increases the value held by the counter 52-2 and the value held by the counter 52-2.
and counter 5 in response to main scanning synchronization signal T (sync).
A latch circuit 52 that latches the value held in 2-3.
-4. Y address signal ADY is obtained as the output of this latch circuit 52-4.

In the address generator 52 having such a configuration, the counter 52-2 increases the initial value set by the initial value setting circuit 52-1 using the clock signal CKA, and when a carry C occurs, the counter 52-2 increases the initial value set by the initial value setting circuit 52-1 again. From counter 52-
Since the initial value is set to 2, the timing at which the counter 52-3 is incremented can be adjusted by changing the initial value. As a result, the X address represented by the Y address signal ADY supplied to the attribute memory 51 is the fifth
As shown in the figure, when zooming out, steps are taken for each multiple addresses, and when expanding, multiple main scanning synchronization signals) (sync
Retains the same address value for a period of .

To explain in detail with reference to FIG. 5, during reduction (in FIG. 5, 5x), an initial value larger than the value set when the magnification is 1x is set in the initial value setting circuit 52-1. , the counter 52-3 increases in value faster than when it is the same size, and the latch circuit 5
2-4 latches every other X address in synchronization with the main scanning synchronization signal Hsync (in Fig. 5, "0", "2"
”, “4” is latched). Therefore, the attribute data held at every other X address is read from the attribute memory 51, and it is possible to correspond to the reduction of the original image. On the other hand, when enlarged (double times in FIG. 5), the initial value setting circuit 52-1 has a smaller initial value than when it is at the same size.
Therefore, the counter 52-3 holds the same value over the generation period of a plurality of main scanning synchronization signals Hsync. Therefore, the latch circuit 52 is connected to the latch circuit 52 over the generation period (two periods in FIG. 5) of a plurality of main scanning synchronization signals Hsync.
-4 can latch the same Y address and read the same attribute data redundantly. As a result, the attribute memory 51 can output redundant attribute data in response to enlargement of the original image, and can cope with variable-size copying without rewriting the attribute data.

The attribute data held in the attribute memory 51 will now be explained. As mentioned above, attribute data is 8 bits
-d7 data, and each bit dO to d7 indicates the following attribute information.

That is, the eighth bit d7 is the color mode signal CL or monochrome mode signal MN output from the selector 49.
This is information that enables or disables the 8th bit, and when this 8th bit is supplied, it becomes possible to fill with a single color. The 7th bit) d6 represents attribute information that instructs to invert the information expressed by the color mode signal CL or the monochrome mode signal MN. formation becomes possible. 6th bit) d5
is a bit to select binary processing or dither processing,
When dither processing is selected, image formation in halftones becomes possible. The fifth bit) d4 is a bit indicating whether to select color mode or monochrome mode, and the selector 49 outputs a color mode signal C based on this fifth bit) d4.
Selection between L and monochrome mode signal MN is executed. Fourth
Bit to second bit) d3 to d1 represent a color coat that specifies the color during image formation, and the first bit d1 indicates whether to inhibit output of the color mode signal CL or monochrome mode signal NIN. There is. The above color coat is defined as shown in Table 1 below.

011 Red 1 0 0 Cyan The attribute data made up of 8 bits explained above can be set for each minute part that makes up the scanning range of the image, so
By manipulating bits of image data, editing such as masking, trimming, specified color single color mode, full color halftone mode, etc. can be performed. For example, part of the image drawn on the manuscript may be a color image and the rest may be a monochrome image, or the image may be printed in a constant color regardless of the color of the image drawn on the manuscript. You can also erase part of the image.

Returning again to FIG. 1, the explanation of the configuration of one embodiment will be continued. 55
indicates a dither ROM, and this dither ROM 55 supplies a threshold value based on the dither method to a selector 57, and the selector 57 responds to the sixth bit (d5) of the attribute data output from the attribute memory 51 to output a dither ROM. The threshold value or binary threshold value outputted from 55 is supplied to comparison circuit 53 . Since this comparison circuit 53 is supplied with the second to fourth bits d1 to d5 of the attribute data and the eighth pit d7, if the normal color is selected based on the fifth bit d4, the selector 49 Color mode signal C supplied from
The color represented by the L or monochrome mode signal MN is output as is from the comparison circuit 53, and if a fixed color is selected by the fifth bit d4, the color represented by the second to fourth bits d1 to d3 is output as is. Replaced with code. Further, if the eighth hit d7 indicates validity, the information regarding shading contained in the signal supplied from the selector 49 is transferred to the selector 5.
It is controlled according to the threshold value supplied from 7.

One word output from the comparison circuit 53 is directly sent to the selection output circuit 59.
At the same time, an inverted signal inverted via the inverter 61 is supplied to the other input of the selection output circuit 59. In response to the first bit dO of the attribute data, the selection output circuit 59 inhibits the output of both the output signal of the comparison circuit 53 and its inverted signal, or inhibits the output of both the output signal of the comparison circuit 53 and its inverted signal, or inhibits the output of both the output signal and its inverted signal in response to the first bit dO of the attribute data.
6, one of them is supplied to a printing device (not shown). Therefore, in this embodiment, the color processing circuit 47, selectors 49, 57, dither ROM 55, comparison circuit 53, and selection output circuit 59 collectively constitute a processing section.

A selection switch 161 is used to instruct variable magnification image formation based on output paper.

Next, the operation of this embodiment will be described using as examples when copying the original shown in FIG. 6 at the same size and when copying at variable magnification.

FIG. 6 is a plan view showing a document on which image [A] is drawn, and in the figure, 61 is an area for specifying full color coloring, and 63 is an area for specifying white color. The attribute designation of such an image is set based on the original. That is, the seventh
As shown in the figure, here is an area 61 of the attribute memory 51.
The address space 71 corresponding to (1111xxx
l) Attribute data expressed as is written in area 6.
The address space corresponding to 3 is (01xxooo 1)
Attribute data represented by is written.

When the same-size copying of the original is started after setting the attribute data, the image sensor 1 moves in the sub-scanning direction and converts the red, green, and blue components of the light reflected from the original into different colors. Analog color signals R, G representing intensity,
A/D converter 3. 5. After the analog color signals are converted into digital color signals DR, DG, and DB at step 7, they are corrected at shading circuits 9, 11, and 13. Therefore, as the document is scanned in the sub-scanning direction, the shading circuits 9, 11.13 supply digital color signals DR, DG, DB for one column in the main-scanning direction to the line rams 15, 17.19 for scaling.

Line rams 15, 17, and 19 for variable magnification are main scanning synchronization signals H
In synchronization with sync, the first memory circuit 21°23.25 and the second memory circuit 27, 29.31 alternate in the main scanning direction 1.
Digital color signal DR for columns.

Memorize DG and DB.

Here, in response to a certain main scanning synchronization signal Hsync, digital color signals DR for one column in the main scanning direction are generated.

DG and DB are written to the first memory circuits 21, 23.25, and the first memory circuits 21, 23.25 read them in synchronization with the next main scanning synchronization signal) (sync), and the second memory circuit 27, 29, and 31 are switched to the write mode.Since the copying is performed at the same magnification, the central processing unit 39 sends the read address signal ADR to the read address generator 37 in synchronization with the write address generator 33. The first memory circuit 21.23.2
The selector 56 sends the write address signal A based on the instruction from the central processing unit 39.
Attribute memory 51 as DW as X address signal AD
is supplied to. Further, the address generator 52 for the Y address is connected to the initial value setting circuit 52 from the central processing unit 39.
Based on the initial value supplied to -1, the Y address at the same magnification can be supplied to the attribute memory 51.

Therefore, the read address signal ADH is supplied to the first circuit portions 21, 23.25, and the X address signal AD
When the X and Y address signals ADY are supplied to the attribute memory 51, an image identical to the image on the document is formed on a sheet (not shown) according to the attribute data. That is,
The image portion within area 61 is formed in full color on the paper at a position corresponding to area 61, and the remaining portion on the paper is white.

Next, the operation when creating an image by reducing the image drawn in FIG. 6 to 1/2 will be described. In case of reduction, the scaling factor is 5.
Select switch 161 to select 0% from central processing unit 3.
You can instruct 9. The attribute data in the attribute memory 51 may remain at the same size as shown in FIG. 7, and there is no need to rewrite it.

When the magnification ratio of 50% is instructed as described above, the central processing unit 39 switches the selection switch 6 as shown in FIG.
1 is on (step Sl),
When the manuscript is standard, the judgment result in step S1 is yes (Y)
Therefore, select the read address generator 37 by switching the selector 56 (step S2), and adjust the latch timing clock CKB so that the read address generator 37 has a variable magnification of 50% using the variable magnification signal R. instruct what to do. As a result, the read address generator 37 receives the clock signal CK.
A latch timing clock CKB having a longer period than A is generated (see the latch timing clock at 0.5 times the period in FIG. 3). Further, the selector 56 is switched and supplies the read address signal ADH to the attribute memory 51 as the X address signal ADX. On the other hand,
The address generator 52 is configured to hold a larger initial value in the initial value setting circuit 52-1 than when the notification corresponding to the magnification change rate of 50% is supplied from the central processing unit 39.Step S3
), an intermittent address is generated as shown in the X address at 0.5 times in FIG. As mentioned above, the relative speed between the image sensor 1 and the document is twice as high as when the image sensor 1 and the document are at the same time, and the latch circuits 41, 43, and 45 latch every other digital color signal DR, DG, and DB. The original image is reduced to 1/2 in both the main scanning direction and the sub-scanning direction. On the other hand, the attribute data read from the attribute memory 51 is also latched by the latch circuit 54 at every other address in the X address direction and supplied to the selector 49, etc., and since every other X address is specified, the area 61 on the document is the main scanning direction,
Even if the size is reduced to 1/2 in both the sub-scanning direction, the attribute data in the address space 71 is applied to the image part in the area 61, and the attribute data in the address space 73 is applied to the image part in the area 63. The image portion of the reduced area 61 to be imaged will be in full color, and the other image portions will be white.

Furthermore, when enlarging an image on a document to 2 times, if you instruct the central processing unit 39 to enlarge the image to 200% using a switch (not shown), the central processing unit 39 uses the variable magnification signal VR to generate a reading address generator. 37 to delay the readout address, and the initial value setting circuit 52-1 of the address generator 52 is made to hold a smaller initial value than that at the time of equal notification, so even if the image on the document is enlarged twice. , an image portion corresponding to the enlarged area 61 is imaged according to the attribute data of the address space 71, and the other image portions are imaged according to the attribute data of the address space 73. In this way, the present embodiment has the advantage that the attribute data set at the time of notification does not need to be reset when setting at variable magnification, and editing work at variable magnification becomes extremely easy.

Further, when the operator operates the selection switch 161 and desires to set attributes based on the output summary, the color processing circuit 47 receives digital color signals DR, DG in accordance with the magnification ratio, as described above. , DB is supplied, but since the judgment result in step S1 is NO (N), the 56 selects the address generator 33 for writing.
4) The initial value at the time of notification is supplied to the address generator 52 (step S5). Therefore, the attribute data is read from the attribute memory 51 in the same way as when the notification is made.

For example, if the manuscript in FIG. 6 is reduced to 1/2 based on the upper left edge, the attribute data of the address space 71 is applied to the upper and left edges of the area 61, so they become white.
Others are imaged in full color on the output paper.

In the above embodiment, the read address and the
Although the addresses are supplied to each other, dedicated address generators may be provided for each of the scaling line ram and attribute ram.

Further, in the above embodiment, the data in the attribute memory is shown as the data at the time of notification, but this may be set based on data read at an arbitrary magnification.

[Effects of the Invention] As explained above, in the present invention, since the generation of the second address signal for reading attribute data corresponds to the generation of the first address signal for reading image data, it is possible to use a large-capacity image memory. In addition, the attribute data set at a predetermined magnification can be used as is even when changing the magnification without having to read the image at a variable magnification, and the editing work when reading the magnification is changed can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of a read address generator of one embodiment, and FIG. 3 is a read address signal of one embodiment. 4 is a block diagram showing the detailed configuration of the Y address generator of one embodiment; FIG. 5 is a timing chart showing the generation timing of the Y address; and 6. 7 is a plan view showing an example of a manuscript for explaining the operation of one embodiment; FIG. 7 is an address map diagram showing an address space of an attribute memory in which attribute data is set for the manuscript of FIG. 6;
- FIG. 8 is a flowchart at the time of variable magnification image formation in one embodiment. 1... Image sensor, 2... Fluorescent lamp, 3-7... A/D converter, 9-13... Shading circuit, 15-19.・
・Line ram for scaling, 33...Address generator for writing, 35...Clock generator, 37...
...Reading address generator, 39...Central processing unit, 41-45...Latch circuit, 47...Color processing circuit, 49...Selector, 51... ...Attribute memory, 52...Y address generator, 53...
・・・Comparison circuit, 55・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
- Selector, 59... Selection output circuit, 161... Selection switch. Patent applicant Minolta Camera Co., Ltd. Agent Patent attorney Kiyoshi Kuwai - (1 other person) CVl: I

Claims (1)

[Scope of Claims] An image data forming section that scans a document and sequentially outputs image data representing each part of an image on the document line by line; It has an image data memory that outputs line by line in response to one address signal, and a plurality of addressable storage areas corresponding to each of a plurality of scanning areas obtained by dividing the scanning range of the image data forming section. , an attribute memory that stores attribute data in each of the plurality of storage areas and outputs the attribute data in response to a second address signal; and a portion of the image represented by the image data read from the image data memory. In the image processing device, the image processing device is equipped with a processing unit that changes the attribute of the image according to the attribute data, the means for setting the magnification, and the generation timing of the second address signal being changed in accordance with the set magnification. An image processing device characterized by: