JP2869973B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and in particular, to an image processing apparatus capable of performing various editing operations based on data held in an attribute memory, for example, a digital color copying machine About.

2. Description of the Related Art Conventionally, digital copiers inhibit output of a part of digital image data obtained based on scanning of an image to prohibit reproduction of a part of the image on paper or reduce the brightness of an image on a document. In some cases, a so-called white image can be reproduced on a sheet by reversing it.

Such an editing operation has been performed on an image memory for storing one page of the document image.

[Problems to be Solved by the Invention] In such an image processing apparatus having the conventional editing function,
Editing is possible on the image memory for one page, but the memory for one page of the document is large and expensive. Therefore, it is conceivable that the attribute of the image data is stored in the attribute memory without having the image memory for one page, and the image data is edited and output in real time according to the attribute data. However, the attribute data in the attribute memory is edited based on the original image data of the specified reading magnification, and even if the original is the same, the attribute data must be edited again with the change of the reading magnification. There was a point.

Also, depending on the editing content, the attribute memory itself may not need to be changed even if the magnification is changed. this is,
In the case where editing work is performed on the basis of output paper, that is, when a frame or the like is printed in advance on print paper and editing is desired to be performed on the basis of the frame, the reading magnification is changed in such a case. However, it is advantageous that the attribute data for the area inside and outside the frame is not changed.

Accordingly, an object of the present invention is to provide an image processing apparatus which does not require re-editing of attribute data even when the reading magnification is changed.

[Means for Solving the Problems] The present invention focuses on the fact that attribute data set at a predetermined magnification can be used as it is at the time of scaling if the read address signal of image data and the read address signal of attribute data are associated with each other. The gist of this is that an image data forming unit that scans a document and sequentially outputs image data representing each part of the image on the document in line units, and rewrites the image data in line units Hold possible, first
An image data memory that outputs in line units in response to an address signal, and a plurality of addressable storage areas corresponding to each of a plurality of scan areas obtained by dividing the scan range of the image data forming unit; An attribute memory for storing attribute data in the plurality of storage areas and outputting the attribute data in response to a second address signal; and an attribute memory for storing a portion of the image represented by the image data read from the image data memory. In an image processing apparatus provided with a processing unit for changing an attribute in accordance with the attribute data, a magnification setting unit for setting a magnification, and a generation timing of the second address signal corresponding to the magnification set by the magnification setting unit It is characterized by comprising a changing means for changing.

Further, the present invention has been made in view of the fact that if the read address signal of the image data and the read address signal of the attribute data correspond to each other, the attribute data set at a predetermined magnification can be used as it is at the time of scaling. The gist thereof is that an image data forming unit that scans a document line by line and sequentially outputs image data representing each part of an image on the document, and holds the image data in a rewritable line unit. An image data memory for outputting in units of lines in response to one address signal; and a plurality of addressable storage areas corresponding to a plurality of scanning areas obtained by dividing the scanning range of the image data forming unit. An attribute memory for holding attribute data in the plurality of storage areas and outputting the attribute data in response to a second address signal;
A magnification setting means for setting a magnification, comprising: a processing unit for changing an attribute of an image portion represented by image data read from the image data memory in accordance with the attribute data; First changing means for changing the generation of the first address signal according to the magnification set by the means, and second changing means for changing the generation timing of the second address signal in accordance with the generation of the first address signal And selecting means for selecting one of a first mode in which the generation timing of the second address signal is not changed and a second mode in which the generation timing of the second address signal is changed by the second changing means. It is characterized by the following.

[Operation of the Invention] When an image drawn on a document is formed at the same magnification by the image processing apparatus according to the above configuration, the image data forming unit scans the document and displays each part of the image on the document. The data is sequentially output, and each image data supplied from the image data forming unit is once made rewritable to the image data memory.
Each image data stored in the image data memory is output in response to the first address signal and supplied to the processing unit. On the other hand, the attribute memory holds attribute data in a plurality of addressable storage areas respectively corresponding to a plurality of scan areas obtained by dividing the scan range of the image data forming unit, and the attribute data is 2 is output in response to the address signal and supplied to the processing unit. At the same magnification, the second address signal advances in response to the first address signal. Therefore, the processing unit follows the attribute of the portion of the image represented by the image data read from the image data memory according to the attribute data. Change and submit for imaging. As mentioned above, the second
Since the address signal advances in accordance with the first address signal, the attribute data supplied to the processing unit corresponds to the instruction for the attribute of the image portion on the original, and Can be changed to any attribute.

On the other hand, when the image represented by the image data supplied from the image forming unit is reduced or enlarged, the image data from the image data memory is read, for example, intermittently or redundantly. The imaging must be controlled, for which the generation of the first address signal needs to be changed. At the time of image formation at such a magnification, the second address signal supplied to the attribute memory is changed in accordance with the magnification, so that the attribute data is also read, for example, intermittently or redundantly. As a result, the attribute data also corresponds to the image portion at the time of the variable magnification, and can be used at the time of the variable magnification without rewriting the attribute data set at the same magnification.

Also, at the time of image formation at such a magnification, the second address signal supplied to the attribute memory is changed in accordance with the first address signal by the selection of the operator, so the attribute data is also changed.
For example, it is read out intermittently or redundantly. As a result, the attribute data corresponds to the image portion even at the magnification,
The attribute data set at the same magnification can be used also at the magnification without rewriting.

On the other hand, even when the image is formed at the variable magnification, if the operator wants to perform the editing operation on the basis of the output sheet, the second address signal can be generated in the same manner as at the same magnification.
When such a selection is made, the setting of the attribute is the same as in the case of the same magnification as in the related art. Therefore, for example, by outputting only the image at the specified magnification and outputting the edited data at the same masking position at the same magnification, it is possible to obtain a variable magnification image output while matching the masking frame on the output paper.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram showing the configuration of one embodiment of the present invention. In the figure, reference numeral 1 denotes an image sensor composed of three rows of CCD elements. The three rows of CCD elements constituting the image sensor 1 are covered with red, green, and blue filters, respectively. In the following description, the column direction of the CCD elements is defined as a main scanning direction, and a direction orthogonal to the main scanning direction, that is, a scanning direction of a document (not shown) is defined as a sub-scanning direction.

As described above, the image sensor 1 receives the reflected light of the light emitted from the fluorescent lamp 2 to the original (not shown) on which the color image is drawn through the red, green, and blue filters, and Analog color signals R, G, of voltages corresponding to the respective intensities of the red component, the green component, and the blue component in the reflected light
Output B. These analog color signals R, G, and B are supplied to A / D converters 3, 5, and 7, respectively.
5, 7 periodically sample the analog color signals R, G, B to form digital color signals DR, DG, DB consisting of a plurality of bits having a value corresponding to the sampled voltage value. A / D
Converters 3, 5, and 7 supply reference voltages VrefR, Vre from central processing unit 39.
fG and VrefB, and the central processing unit 39 controls the reference voltages VrefR, VrefG, and VrefB so that the maximum value is constant for each color.
Set. These digital color signals DR, DG, and DB are sent to shading circuits 9, 11, and 13. The shading circuits 9, 11, and 13 correct errors due to uneven light emission of the fluorescent lamp 2 and variations in the characteristics of the CCD elements. The corrected digital color signals DR, DG, and DB are supplied in parallel to the scaling rams 15, 17, and 19. Therefore, in the present embodiment, the image sensor 1, the fluorescent lamp 2, the A / D converters 3, 5, and 7, and the shading circuits 9, 11, and 13 constitute an image data forming unit as a whole. The line rams 15, 17, and 19 for zooming constitute an image data memory as a whole.

The scaling line rams 15, 17, and 19 have two addressable storage circuits, that is, first storage circuits 21, 23, 25 and second storage circuits 27, 29, 31, respectively. ,twenty three,
25, 27, 29, 31 are digital color signals DR composed of a plurality of bits,
It has a storage capacity capable of storing a plurality of DGs and DBs. The line rams 15, 17, and 19 for zooming are stored in the storage circuits 21, 23, 25, 27, of the address specified by the write address generator 33.
Digital color signals DR, DG, and DB are held at 29 and 31, respectively. Write address generator 33 is clock generator 35
The write address signal ADW is formed based on the clock signal CKA supplied from the
Is the first storage circuit 2 while stepping in synchronization with the clock signal CKA.
Digital color signals DR, DG, and DB are sequentially written to 1, 23, and 25, and thereafter, the first storage circuits 21, 23, and 25 are switched to a read mode in response to the main scanning synchronization signal Hsync,
This time, the write address signal is supplied to the second memory circuits 27, 29, 31.
Since the ADW is supplied, the digital color signals DR, DG, and DB supplied in parallel to the scaling line rams 13, 15, and 17 from the shading circuits 9, 11, and 13 are thereafter stored in the second storage circuits 27, 29, and 31.
Is written to. On the other hand, the line rams 15, 17,
The digital color signals DR, DG, and DB written in the first memory circuits 21, 23, and 25 of the nineteenth circuit are used in response to the read address signal ADR formed by the read address generator 37 to generate the second color signals DR, DG, and DB.
The digital color signals DR, DG, and DB are read out from the storage circuits 27, 29, and 31 in parallel with the writing. The second storage circuits 27, 29,
When the writing of the digital color signals DR, DG, DB to 31 is completed, the second storage circuits 27, 29, 31 enter the read mode,
Since the first storage circuits 21, 23 and 25 are again in the write mode, the digital color signals DR, DG and DB are stored in the first storage circuit 2 this time.
The digital color signals DR, DG, and DB written in 1, 23, and 25 and held in the second storage circuits 27, 29, and 31 are read. As described above, the first storage circuits 21, 23, 25 and the second storage circuits 27, 2 constituting the scaling line rams 15, 17, 19 are described.
9 and 31 are alternately switched between the write mode and the read mode in response to the main scanning synchronization signal Hsync, so that any one of the first storage circuits 21, 23, 25 and the second storage circuits 27, 29, 31 On the other hand, while the digital color signals DR, DG, DB are being written, the digital color signals DR, DG, DB preceding the digital color signals DR, DG, DB being written are stored in the first storage circuits 21, 23, 25.
And the second storage circuit 27, 29, 31.

The read address generator 37 generates the read address signal ADR as described above, but the read address signal ADR is a clock signal at the time of enlargement magnification based on the instruction indicated by the scaling signal VR supplied from the central processing unit 39. It is also possible to advance at a timing where CKA is thinned out at a predetermined rate. Read address generator
Reference numeral 37 further generates a latch timing clock CKB for instructing a latch circuit, which will be described later, to perform a latch. The cycle of the latch timing clock CKB is lengthened at the time of reduction magnification based on the magnification signal VR.

That is, the read address generator 37
The circuit includes a latch timing generation circuit as shown in detail in FIG.
-1 and a latch circuit 37-2 for latching the output of the adder 37-1 in synchronization with the clock signal CKA. The set value is supplied, and the other input B is supplied with the output of the latch circuit 37-2. Latch timing clock CKB
Is obtained from the carry output C of the adder. For example, the scaling signal VR indicates reduction 1 / n of the original image, and one input A is N / n (for example, 5) based on the scaling signal VR.
(N> n), the first clock signal CK
At A, the latch circuit 37-2 latches "5" and the adder 37-
1 to the other input B. As a result, the adder 37-1
Adds "5" supplied to the input of one A and "5" supplied to the other input, and "10" appears in the output. This output "10" is latched by the latch circuit 37-2 with the second clock signal CKA. Thereafter, the adder 37-1 increases the sum by “5”, and when a carry occurs, this is supplied to the latch circuits 41, 43, and 45 as a latch timing clock CKB. However, if N / n '(for example, "2") is supplied to one input A of the adder 37-1 based on the scaling signal VR, the sum of the adder 37-1 becomes "2".
Therefore, the generation cycle of the latch timing clock CKB becomes longer. Therefore, if the increase number of the sum at the same magnification is appropriately selected, the latch timing clock at the reduction
CKB can be generated based on the scaling signal VR.
The relationship between the latch timing clock CKB and the read address signal ADR will be described later in detail.

Returning to FIG. 1, the description of the embodiment will be continued. The variable-power line rams 15, 17, and 19 are connected in parallel to latch circuits 41, 43, and 45. These latch circuits 41, 43, and 45 are connected to the above-described latch timing clock CKB supplied from the read address generator 37. Line ram 15,1 in response to
The digital color signals DR, DG, and DB output from 7, 19 are latched, and the digital color signals DR, DG, and DB latched by the latch circuits 41, 43, and 45 are supplied to the color processing circuit 47 in parallel.

The digital color signals DR, DG, DB read from the scaling line rams 15, 17, 19 based on the read address signal ADR formed by the read address generator 37.
And the digital color signal D actually supplied to the color processing circuit 47.
The correspondence between R, DG, and DB will be described in detail with reference to FIG. FIG. 3 is a graph showing a change between the read address signal ADR and the latch timing clock CKB when the magnification ratio signal VR indicates 0.5, 1 and 2 times. When the main scanning synchronization signal Hsync is supplied from the clock generator 35, the write address generator 33 and the read address generator 37 are reset, and thereafter, the clock signal CKA supplied from the clock generator 35
, The write address is sequentially incremented. As a result, the write address signal ADW indicating the sequentially incremented write address is also output in synchronization with the clock signal CKA. On the other hand, the read address signal ADR increases the scaling factor based on the instruction indicated by the scaling signal VR. That is, the read address advances in synchronization with the clock signal CKA at the time of equal magnification and at the time of reduction, and at the time of enlargement, the magnification indicated by the magnification signal VR (for example, 2).
In step with the timing thinned out corresponding to. On the other hand, the latch timing clock CKB is output in synchronization with the clock signal CKA at the time of equal magnification and at the time of enlargement, but is output at the time of contraction (for example, 0.5
) Is output in a long cycle based on the instruction shown in the scaling signal VR.

Therefore, at the same magnification, the line rams 15, 17, 19
The digital color signals DR, DG, and DB stored in are read out at the same timing as the clock signal CKA, and all the digital color signals read out from the scaling line rams 15, 17, and 19 are read out.
DR, DG, and DB are latched by the latch circuits 41, 43, and 45 and supplied to the color processing circuit 47. However, at the time of reduction, the read address advances in synchronization with the clock signal CKA, so that the digital color signals DR, DG, and DB held in the scaling line rams 15, 17, and 19 have the same timing as at the time of equal magnification. Although read, the latch timing clock CKB is half (0.5 times) of the clock signal CKA as shown in FIG.
Therefore, the digital color signals DR, DG, and DB output from the scaling line rams 15, 17, and 19 are intermittently latched by the latch circuits 41, 43, and 45. Therefore, at the time of 1/2 reduction, the color image drawn on the original is sent to the color processing circuit 47 every other pixel in the main scanning direction, and the image reproduced on the paper is reduced to 1/2 of the original image. You.

On the other hand, for example, when the original image is enlarged twice, the read address advances at half the speed of the same size, so that the read address signal ADR becomes the clock signal CKA.
Indicate the same address for a period of two clocks. On the other hand, since the latch timing clock CKB is output at the same period as the clock signal CKA, the same digital color signals DR, DG, DB are latched twice successively by the latch circuits 41, 43, 45. The original image is enlarged twice in the main scanning direction.

The reduction or enlargement in the sub-scanning direction at the time of changing the magnification is performed by changing the relative scanning speed between the document and the image sensor 1. That is, when the document is reduced, the relative movement speed between the document and the image sensor 1 is increased. Since the synchronization signal Hsync in the main scanning direction is generated at fixed intervals,
The distance that the image sensor 1 moves during each main scan increases, while the moving distance of the printing device during image formation is constant, so that the image is reduced. On the other hand, when the document is enlarged, the relative movement speed between the document and the image sensor 1 is reduced. As described above, the main scanning synchronization signal
Since Hsync is generated at regular intervals, the distance that the image sensor 1 moves during one main scan is reduced, and when an image is formed by a printing device with a constant moving distance, an enlarged image is obtained. .

Referring again to FIG. 1, the color processing circuit 47 performs a masking process in accordance with the ink characteristics of the output printing device (not shown) to convert the digital color signals DR, DG, and DB according to a predetermined procedure. , A color mode signal CL indicating the ink amounts of the magenta ink M and the cyan ink C, and a monochrome mode signal MN obtained by color density averaging or weighted averaging of the three color ink amounts represented by the color mode signal CL. To form The color mode signal CL and the monochrome mode signal MN are supplied to the selector 49, and the selector 49 performs the color mode signal CL and the monochrome mode signal based on the fourth bit of the attribute control signal AT output from the attribute memory 51 described later. The signal MN and one of them are sent to the comparison circuit 53. The attribute control signal AT is an 8-bit signal representing attribute data described later, and the attribute data is held at each address of the attribute memory 51.

More specifically, the attribute memory 51 has addresses corresponding to a minute range obtained by dividing the scanning range of the document into, for example, 1 square millimeter. At each address, 8-bit attribute data is written by the central processing unit 39. ing. Also,
These attribute data are read in response to the read address signal ADX supplied from the selector 56.
Outputs attribute data stored at the address represented by DX. The selector 56 selectively passes the write address signal ADW or the read address signal ADR based on an instruction from the central processing unit 39, and supplies this to the attribute memory 51 as a read X address signal ADX. The attribute control signal AT output from the attribute memory 51 is latched by the latch circuit 54 by the latch timing clock CKB.

As already described in connection with the latch circuits 41, 43, and 45, the read digital color signals DR, DG, and DB are read at the time of reduction.
Are intermittently latched, and the read address AD
Since R holds the same value for a long time, the digital color signals DR,
DG and DB are duplicated and latched. Similarly, attribute control signal A
T is also intermittently latched by the latch circuit 54 at the time of reduction, while the same X address is held over the duration of a plurality of clock signals at the time of enlargement, so that the attribute control signal AT representing the same attribute data is read in duplicate. It is possible,
It is possible to cope with the original image without changing the attribute data when copying the original image. In this embodiment, since the attribute data is set for each square millimeter, the digital color signal D
The number of attribute data is smaller than the number of R, DG, DB. Therefore,
The X address signal ADX uses only the upper bits of the read address signal ADR.

On the other hand, the Y address signal ADY is
Is supplied to the attribute memory 51. As shown in FIG. 4, the address generator 52 includes an initial value setting circuit 52-1 and a counter 52-2 for increasing the initial value supplied from the initial value setting circuit 52-1 by the clock signal CKA. When,
A counter 52-3 for sequentially increasing the value held by the ripple carry C of the counter 52-2;
and a latch circuit 52-4 for latching the value held in the counter 52-3 in response to c. Y address signal ADY is obtained as an output of latch circuit 52-4.
In the address generator 52 having such a configuration, the counter 52
-2, the initial value set by the initial value setting circuit 52-1 is increased by the clock signal CKA. When the carry C occurs, the initial value is set again by the counter 52-2 from the initial value setting circuit 52-1. Therefore, the timing at which the counter 52-3 is incremented can be adjusted by changing the desired value. As a result, as shown in FIG. 5, the Y address represented by the Y address signal ADY supplied to the attribute memory 51 advances by a plurality of addresses at the time of reduction, and a plurality of main scanning synchronization signals Hsync at the time of enlargement. Hold the same address value over the period.

In detail with reference to FIG. 5, when reducing (in FIG. 5,
At the time of 0.5 times), an initial value larger than the value set at the time of equal magnification is set in the initial value setting circuit 52-1.
The value of the latch circuit 52-3 increases faster than at the same time, and the latch circuit 52-4
Latches every other Y address in synchronization with the main scanning synchronization signal Hsync ("0", "2", and "4" are latched in FIG. 5). Therefore, the attribute data held at every other Y address is read from the attribute memory 51, and it is possible to cope with the reduction of the original image. On the other hand, at the time of enlargement (2 times in FIG. 5), a smaller initial value is set in the initial value setting circuit 52-1 than at the time of equal magnification. -3 holds the same value. Therefore, the latch circuit 52-4 can latch the same Y address over the period (two periods in FIG. 5) in which the plurality of main scanning synchronization signals Hsync are generated, and can read the same attribute data redundantly. As a result, the attribute memory 51 can output the attribute data redundantly in response to the enlargement of the original image, and can cope with the variable-size copy without rewriting the attribute data.

Here, the attribute data stored in the attribute memory 51 will be described. As described above, the attribute data has 8 bits d0 to
It is d7 data, and each bit d0 to d7 indicates the following attribute information. That is, the eighth bit d7 is the selector
This is information for validating or invalidating the color mode signal CL or the monochrome mode signal MN output from 49. When the eighth bit is supplied, it is possible to paint with a single color. The seventh bit d6 represents attribute information for instructing inversion of the information represented by the color mode signal CL or the monochrome mode signal MN. The seventh bit d6 indicates that complementary color image formation or black / white inverted image formation can be performed. Will be possible. 6th bit d5
Is a bit for selecting binary processing or dither processing,
When dither processing is selected, halftone image formation becomes possible. The bit d4 in FIG. 5 is a bit indicating which of the color mode and the monochrome mode is to be selected, and the selector 49 selects the color mode signal CL and the monochrome mode signal MN based on the fifth bit d4. . The fourth bit to the second bit d3 to d1 represent a color code designating a color at the time of image formation, and the first bit d1 indicates whether or not the output of the color mode signal CL or the monochrome mode signal MN is prohibited. ing. The color codes are defined as shown in Table 1 below.

The attribute data composed of 8 bits described above can be set for each minute portion constituting the scanning range of the image. Therefore, by manipulating the bits of the image data, masking, trimming, designated color single color mode, full color halftone You can edit the mode, etc. For example, a part of the image drawn on the document may be a color image, and the remainder may be a monochrome image, an image may be printed in a fixed color regardless of the color of the image drawn on the document, or the image may be drawn on the document. Or delete a part of the displayed image.

Returning to FIG. 1, the description of the configuration of the embodiment will be continued. 55
Indicates a ditherom. The ditherom 55 supplies a threshold value based on the dither method to the selector 57, and the selector 57
Is the sixth bit of the attribute data output from the attribute memory 51
The threshold value or the binary threshold value output from the ditherrom 55 in response to d5 is supplied to the comparison circuit 53. This comparison circuit
Since the second to fourth bits d1 to d5 and the eighth bit d7 of the attribute data are supplied to 53, if the normal color is selected based on the fifth bit d4, the data is supplied from the selector 49. The color represented by the color mode signal CL or the monochrome mode signal MN is output from the comparison circuit 53 as it is, and the fifth
If a fixed color is selected by the bit d4, it is replaced by the color code represented by the second to fourth bits d1 to d3. If the eighth bit d7 indicates validity, the information on shading included in the signal supplied from the selector 49 is controlled according to the threshold value supplied from the selector 57.

The output signal of the comparison circuit 53 is directly supplied to one input of the selection output circuit 59, and the inverted signal inverted via the inverter 61 is supplied to the other input of the selection output circuit 59. The selection output circuit 59 is the first bit of the attribute data
In response to d0, the output of both the output signal of the comparison circuit 53 and its inverted signal is inhibited, or in response to the seventh bit d6, one of them is supplied to a printing device (not shown). Therefore, in this embodiment, the color processing circuit 47, the selectors 49 and 57, the ditherrom 55, the comparison circuit 53, and the selection output circuit 59 constitute a processing unit as a whole.

Reference numeral 161 denotes a selection switch, which is used for instructing a magnification change image based on an output sheet.

Next, the operation of this embodiment will be described by taking as an example a case where the original shown in FIG. 6 is copied at the same magnification and a case where the original is copied at the variable magnification.

FIG. 6 is a plan view showing an original on which an image [A] is drawn. In the figure, reference numeral 61 denotes an area for specifying full-color coloring, and reference numeral 63 denotes an area for specifying white. The attribute designation of the image is set based on the document. That is, as shown in FIG. 7, the attribute data represented by (1111xxx1) is written in the address space 71 corresponding to the area 61 of the attribute memory 51, and the address space corresponding to the area 63 is written. Is written with attribute data represented by (01XX0001).

When the original copy is started after the setting of the attribute data, the image sensor 1 moves in the sub-scanning direction, and separates the red, green, and blue components of the light reflected from the original. Analog color signals R, G, B representing intensity
After converting the analog color signals into digital color signals DR, DG, and DB by A / D converters 3, 5, and 7, the shading circuit
It is corrected by 9,11,13. Accordingly, as the document is scanned in the sub-scanning direction, the shading circuits 9, 11, 13 supply the digital color signals DR, DG, DB for one column in the main scanning direction to the line rams 15, 17, 19 for scaling.

The line rams 15, 17, and 19 for scaling are synchronized with the main scanning synchronization signal Hsync, and the first storage circuits 21, 23, 25 and the second storage circuits 27, 29, 31 are synchronized.
And the digital color signals DR, DG,
Remember the DB.

Here, in response to a certain main scanning synchronization signal Hsync, the digital color signals DR, DG, DB for one column in the main scanning direction are written into the first storage circuits 21, 23, 25, and the next main scanning synchronization signal Hsync It is assumed that the first storage circuits 21, 23, 25 are switched to the read mode and the second storage circuits 27, 29, 31 are switched to the write mode in synchronization with the operation. Since copying is performed at the same magnification, the central processing unit 39 has already sent the read address signal ADR to the first storage circuits 21, 23, 25 in synchronization with the read address generator 37 in synchronization with the write address generator 33. The selector 56 supplies the write address signal ADW to the attribute memory 51 as the X address signal ADX based on the instruction from the central processing unit 39. The address generator 52 for the Y address can supply the Y address at the same magnification to the attribute memory 51 based on the initial value supplied from the central processing unit 39 to the initial value setting circuit 52-1.

Therefore, when the read address signal ADR is supplied to the first circuit portions 21, 23, and 25, and the X address signal ADX and the Y address signal ADY are supplied to the attribute memory 51, the original is placed on a sheet (not shown). The same image as the above image is formed according to the attribute data. That is, the image portion in the area 61 is formed in full color at a position corresponding to the area 61 on the paper, and the remaining part on the paper is white.

Next, an operation in the case of forming an image by reducing the image drawn in FIG. 6 to 1/2 will be described. In the case of reduction, the scaling factor is 50
% May be indicated to the central processing unit 39 by the selection switch 161. The attribute data in the attribute memory 51 may be the same as that shown in FIG. 7 at the same magnification and need not be rewritten again.

When the magnification is instructed to be 50% as described above, the central processing unit 39 switches the selection switch 161 as shown in FIG.
Is determined (step S1). When the original is the reference, the determination result of step S1 is YES (Y). Therefore, the selector 56 is switched to select the read address generator 37 (step S2). The scaling signal VR instructs the read address generator 37 to adjust the latch timing clock CKB so that the scaling factor becomes 50%. As a result, the read address generator 37 generates the latch timing clock CKB having a longer cycle than the clock signal CKA (see the latch timing clock at 0.5 times in FIG. 3). Further, the selector 56 is switched to change the read address signal ADR to X.
The address signal ADX is supplied to the attribute memory 51.
On the other hand, the Y address generator 52 holds an initial value larger than that at the same magnification corresponding to the magnification of 50% supplied from the central processing unit 39 in the initial value setting circuit 52-1 (step S5).
3), intermittent addresses are generated as shown in the 0.5 times Y address in FIG. As described above, the relative speed between the image sensor 1 and the document is twice as large as that at the same time, and the latch circuits 41, 43, and 45 latch the digital color signals DR, DG, and DB every other. The image of the document is reduced by half in both the main scanning direction and the sub-scanning direction. On the other hand, the attribute data read from the attribute memory 51 is also latched in the X address direction by the latch circuit 54 and supplied to the selector 49 and the like, and the Y address is designated every other. Even if the data is reduced by half in both the main scanning direction and the sub-scanning direction, the attribute data of the address space 71 is applied to the image part of the area 61, and the attribute data of the address space 73 is applied to the image part of the area 63. The image portion of the reduced area 61 formed on the paper becomes full color,
Other image portions are white.

Further, when the image on the document is enlarged by a factor of two, if a 200% enlargement ratio is indicated to the central processing unit 39 by a switch (not shown), the central processing unit 39 uses the scaling signal VR to read the address generator for reading. 37 is instructed to delay the increment of the read address, and the initial value setting circuit 52-1 of the address generator 52 holds an initial value smaller than that at the time of equal magnification, so that the image on the original is enlarged twice. Also, the image portion corresponding to the enlarged area 61 is formed according to the attribute data of the address space 71, and the other image portions are formed according to the attribute data of the address space 73. As described above, the present embodiment has the advantage that the attribute data set at the same magnification does not need to be reset at the time of image formation at the variable magnification, and the editing work at the variable magnification is extremely easy.

When the operator operates the selection switch 161 to set the attribute based on the output paper, the color processing circuit 47 supplies the digital color signals DR and DG corresponding to the magnification as described above. , DB are supplied, but the determination result in step S1 becomes no (N), so the selector 56 selects the write address generator 33 (step S4), and the initial value at the same magnification is supplied to the address generator 52. (Step S
Five). Therefore, the attribute data is read from the attribute memory 51 in the same manner as in the case of the equal magnification. For example, when the original shown in FIG. 6 is reduced by half with respect to the upper left corner, since the attribute data of the address space 71 is applied to the upper part of the area 61 and the left edge, it becomes a white background. Are formed on the output paper in full color.

In the above embodiment, the read address and the X address are supplied from the common address generator to the scaling ram and the attribute ram. However, dedicated address generators may be provided for the scaling ram and the attribute ram. .

Further, in the above-described embodiment, the data in the attribute memory is data at the same magnification, but this may be set based on data read at an arbitrary magnification.

[Effects of the Invention] As described above, in the present invention, the generation of the second address signal for reading attribute data is made to correspond to the generation of the first address signal for reading image data. And the attribute data set at a predetermined magnification can be used as it is even at the time of scaling, so that the editing operation at the time of scaling reading can be easily performed.

Further, in the present invention, the second address signal for reading attribute data is generated by selection in the same manner as in the case of equal magnification or in correspondence with the generation of the first address signal for reading image data, even during image formation at the magnification. Therefore, the attribute data set at the time of equal magnification can be used as it is at the time of magnification, and an effect of easily performing editing work at the time of magnification can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of a read address generator of one embodiment, and FIG. 3 is a read address signal of one embodiment. FIG. 4 is a block diagram showing a detailed configuration of a Y address generator according to one embodiment, FIG. 5 is a timing chart showing Y address generation timing, and FIG. FIG. 7 is a plan view showing an example of a document for explaining the operation of one embodiment. FIG. 7 is an address map diagram showing an address space of an attribute memory in which attribute data is set for the document shown in FIG. FIG. 4 is a flow chart at the time of image formation at a variable magnification in one embodiment. 1 image sensor 2 fluorescent light 3-7 A / D
Converters, 9 to 13: shading circuits, 15 to 19: line rams for scaling, 33: address generators for writing, 35: clock generators, 37: address generators for reading, 39: central processing unit, 41-45 ...
Latch circuit, 47 ... Color processing circuit, 49 ... Selector, 51 ...
... Attribute memory, 52 ... Y address generator, 53 ...
Comparison circuit, 55 ... Ditherom, 57 ... Selector, 59 ...
Selection output circuit, 161, selection switch.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/21 H04N 1/393 H04N 1/04

Claims (2)

(57) [Claims] An image data forming section for scanning a document and sequentially outputting image data representing each portion of the image on the document in line units; and holding the image data in a rewritable manner in line units. An image data memory that outputs in line units in response to an address signal, and a plurality of addressable storage areas corresponding to each of a plurality of scan areas obtained by dividing the scan range of the image data forming unit; An attribute memory for storing attribute data in the plurality of storage areas and outputting the attribute data in response to a second address signal; and an attribute memory for storing a portion of the image represented by the image data read from the image data memory. An image processing apparatus comprising: a processing unit for changing an attribute according to the attribute data; a magnification setting unit for setting a magnification; and a generation timing of the second address signal. The image processing apparatus characterized by comprising a changing means for changing in correspondence to the set magnification by the magnification setting means. 2. An image data forming section for scanning an original in units of lines and sequentially outputting image data representing each part of an image on the original, and holding each of the image data so as to be rewritable in units of lines. An image data memory that outputs in line units in response to an address signal, and a plurality of addressable storage areas corresponding to each of a plurality of scan areas obtained by dividing the scan range of the image data forming unit; An attribute memory for storing attribute data in the plurality of storage areas and outputting the attribute data in response to a second address signal; and an attribute memory for storing a portion of the image represented by the image data read from the image data memory. An image processing apparatus comprising: a processing unit configured to change an attribute according to the attribute data; a magnification setting unit configured to set a magnification; and a magnification set by the magnification setting unit. First changing means for changing the generation of the first address signal, second changing means for changing the generation timing of the second address signal in accordance with the generation of the first address signal, and the second address signal An image processing apparatus comprising: a first mode that does not change the generation timing of the second address signal; and a selection unit that selects one of a second mode that changes the generation timing of the second address signal by the second changing unit. .