JPH01183268A - Picture processor - Google Patents

Abstract

PURPOSE:To use attribute data as it is even at the time of varying a power, and to facilitate editorial work by generating a second address signal for reading the attribute data similarly to the time of an equal scale factor or correspondingly to the generation of a first address signal for reading picture data according to selection. CONSTITUTION:The title device is provided with picture data memories 15, 17, 19 to output the picture data by one line unit as responding to the first address signal and an attribute memory 51 to output the attribute data as responding to the second address signal, and the generating timing of the second address signal is left as it is or is changed correspondingly to the generation of the first address signal according to the selection. Thus, if the second address signal is changed correspondingly to the first address signal at the time of picture generation by the variable scale factor, the attribute data too is read out, for instance, intermittently or repeatedly, and the attribute data corresponds to a picture part. On the other hand, by generating the second address signal similarly the time of equally varying a power, only a picture can be outputted by the designated scale factor, and editorial data can be made to coincide with a masking frame on an outputting form.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device that can perform various kinds of fraud operations based on data held in an attribute memory, such as a digital color copying device. Regarding machines.

[Prior Art] Conventionally, digital copying machines have been equipped with methods such as prohibiting the output of a portion of digital image data obtained by scanning an image and prohibiting reproduction of that portion of the image on paper, or controlling the brightness of an image on a document. There are some that can be reversed to reproduce a so-called white image on paper.

Such editing work is performed on an image memory that stores one page of manuscript images.

[Problems to be Solved by the Invention] In an image processing device equipped with such a conventional editing function, editing is possible on the image memory for one page, but the memory for one page of the original has a large capacity and is expensive. be.

Therefore, instead of having an image memory for one page, it may be possible to store the attributes of image data in an attribute memory, edit the image data in real time to make the attribute data, and output the edited image data. However, the problem is that the attribute data in the attribute memory is edited based on the original image data at the specified reading magnification, and even if the original is the same, the attribute data must be re-edited when the reading magnification is changed. There was a point. Further, depending on the editing content, even if the magnification is changed, the attribute memory itself may not need to be changed. This is used when editing is performed using the output paper as a reference, that is, when a frame etc. is printed in advance on the print paper and you want to edit using that frame as a reference.In such cases, the reading magnification It is more convenient if the attribute data for areas inside and outside the frame are not changed even if the frame is changed.

Therefore, an object of the present invention is to provide an image processing apparatus that does not require re-editing attribute data even when the reading magnification is changed.

[Means for solving the problem] The present invention focuses on the fact that attribute data set at a predetermined magnification can be used as is when changing the magnification by making the read address signal of image data correspond to the read address signal of attribute data. The gist of this is that it includes an image data forming section that scans a document line by line and sequentially outputs image data representing each part of the image on the document, and the ability to rewrite each of the above image data line by line. and a plurality of addressable image data memory corresponding to each of a plurality of scanning areas obtained by dividing the scanning range of the image data forming section. an attribute memory having a storage area, each of which stores attribute data in the plurality of storage areas, and outputs the attribute data in response to a second address signal; and an attribute memory that is represented by image data read from the image data memory. a processing unit for changing the attributes of the portion of the image that has been processed according to the data; means for changing the generation of the first address signal in accordance with the magnification; and means for changing the generation of the second address signal according to the magnification; The generation timing can be left unchanged or changed in accordance with the generation of the first address signal.

[Operation of the Invention] When the image processing apparatus having the above configuration creates an image drawn on a document at the same magnification, the image data forming section scans the document and generates an image representing each part of the image on the document. Data is sequentially output, and each image data supplied from the image data forming section is made rewritable in the image data memory. Each image data held in this image data memory is
It is output in response to the address signal and supplied to the processing section.

On the other hand, the attribute memory stores attribute data in a plurality of addressable storage areas corresponding to each of a plurality of scanning areas obtained by dividing the scanning range of the image data forming section, and the attribute data is stored in a plurality of addressable storage areas. 2 is output in response to the address signal and supplied to the processing section. At the time of notification, the second address signal advances in response to the second address signal, so the processing section changes the attributes of the image portion represented by the image data read from the image data memory according to the attribute data. Change it and submit it for image creation. As mentioned above, since the second address signal advances in response to the first address signal, the attribute data supplied to the processing section corresponds to the instruction for the attribute of the 'image part' on the document. , each part of the image on the document can be changed to any attribute.

On the other hand, when reducing or enlarging an image represented by image data supplied from the image forming section, the image data may be read out from the image data memory intermittently, for example, or
It is necessary to control image formation by performing redundant reading, and for this purpose it is necessary to change the generation of the first address signal. When creating an image at such variable magnification, the second address signal supplied to the attribute memory is changed according to the first address signal according to the operator's selection, so that the attribute data is also changed, for example, intermittently or overlappingly. is read out. As a result, the attribute data corresponds to the image portion even when the magnification is changed, and the attribute data set when the magnification is constant can be used even when the magnification is changed without being rewritten.

On the other hand, even when creating an image with variable magnification, if the operator wishes to perform editing work based on the output paper, the second address signal can be generated in the same manner as when the image is outputted. If such a selection is made, the attribute settings will be the same as in the past, as in the case of notification.

Therefore, for example, by outputting only the image at a specified magnification and outputting the editing data at the same masking position at the time of notification, it is possible to obtain a variable magnification image output while matching the masking frame on the output paper.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention. In the figure, reference numeral 1 denotes an image sensor composed of three rows of CCD elements, and the three rows of CCD elements constituting the image sensor 1 are covered with red, green, and blue filters, respectively. In the following description, the column direction of the CCD elements will be referred to as the main scanning direction, and the direction perpendicular to the main scanning direction, that is, the scanning direction of the original (not shown) will be referred to as the sub-scanning direction.

As described above, the image sensor 1 receives the reflected light from the fluorescent lamp 2 through the red, green, and blue filters that illuminates an original (not shown) on which a color image is drawn, and receives the reflected light from the fluorescent lamp 2 through the red, green, and blue filters. analog color signals R, G of voltages corresponding to the respective intensities of the red component, green component, and blue component in the reflected light;
Output B.

These analog color signals R, G, and B are supplied to A/D converters 3.5.7, respectively, and A/D converters 3.5
．． Reference numeral 7 periodically samples the analog color signals R, G, and B to form digital color signals DR, DG, and DB consisting of a plurality of pits having values corresponding to the sampled voltage values. A/D converter 3, 5. 7, reference voltages Vr e f R, V r e f are supplied from the central processing unit 39.
The central processing unit 39 supplies reference voltages Vref R and VrefG so that the maximum value is constant for each color.

Set VrefB. These digital color signals DR
, DG, DB are sent to the shape ink circuit 9.11.13, and the shading circuit 9.11.13 is sent to the fluorescent lamp 2.
Digital color signals DR, DG corrected by correcting errors caused by uneven light emission and variations in characteristics of CCD elements,
DB is supplied in parallel to the variable power line rams 15, 17, and 19. Therefore, in this embodiment, the image sensor 1 and
Fluorescent lamp 2 and A/D converter 3. 5. 7 and shading circuits 9, 11, and 13 collectively constitute an image data forming section. In addition, the line ram 15, 1 for variable magnification
7.19 constitutes an image data memory as a whole.

Line ram 15.17.19 for variable magnification is addressable 2
two storage circuits, namely the first storage circuit 21.23.25
and the second memory circuit 27. 29. 31, respectively, and each memory time Pt21. 23゜25.27,29
．． 31 is a digital color signal DR, D consisting of multiple bits.
It has a storage capacity that can store a plurality of G and DB. The scaling line rams 15, 17, and 19 hold digital color signals DR, DG, and DB in storage circuits 21, 23, 25, 27, 29, and 31 at addresses designated by the write address generator 33. The write address generator 33 forms a write address signal ADW based on the clock signals CK and A supplied from the clock generator 35, and generates the write address signal ADW.
W steps forward in synchronization with the clock signal CKA.
Memory circuit 21. 23. 25, digital color signal DR
, DG, and DB are sequentially written, and then, in response to the main scanning synchronization signal HsynC, the first memory circuit 21.23
．． 25 to the read mode, and this time write address signal AD is sent to the second memory circuits 27, 29, and 31.
Since W is supplied, the shading circuit 9.11.13
Digital color signals DR, DG are supplied in parallel from the zoom line rams 13, 15, and 17.

DB is subsequently written into the second storage circuits 27, 29, and 31. On the other hand, the line ram 15.17.1 for variable magnification
9 first storage circuit 21. 23. The digital color signals DR, D, G, DB written in the second storage circuit 27.2 are sent to the second storage circuit 27.2 in response to the readout address signal ADH generated by the readout address generator 37.
The digital color signals DR, DG, and DB are read out in parallel with writing to 9.31. Second memory circuit 27.29
．． When the writing of digital color signals DR, DG, DB to 31 is completed, the second memory circuit 27.29.31 becomes the read mode, and the first memory circuit 21.23.25 becomes the write mode again. Signal DR,
DG and DB are now written into the first storage circuit 21.23.25, and the digital color signals DR, DG and DB held in the second storage circuit 27.29.31 are read out.

The first memory circuits 21, 23.25 and the second memory circuit 2 that constitute the variable power line rams 15, 17.19 in this way
7, 29.31 are alternately switched between the write mode and the read mode in response to the main scanning synchronization signal Hsync, so the first storage circuits 21, 23, 2δ and the second storage circuit 27. Digital color signal DR on either side of 29°31.

While writing DG, DB, the digital color signals DR, DG, , DB preceding the digital color signals DR, DG, DB being written are stored in the first storage circuit 21.23.25 and the second storage circuit 27. 29. 31.

The read address generator 37 generates the read address signal ADH as described above, but the read address signal ADR is a clock signal at the time of enlargement based on the instruction indicated by the variable magnification signal VR supplied from the central processing unit 39. It is also possible to advance at a timing when CKA is thinned out at a predetermined ratio. The read address generator 37 further generates a latch timing clock CKB that instructs a latch circuit, which will be described later, to latch, and the period of this latch timing clock CKB is lengthened based on the variable magnification signal VR when the magnification is reduced.

That is, the read address generator 37
It is equipped with a latch timing generation circuit as shown in detail in the figure, and this latch timing generation circuit is connected to the adder 3.
7-1 and the output of this adder 37-1 as a clock signal CK.
A, and one input A of the adder 37-1 receives a variable magnification signal V.
A setting value based on R is supplied, and the other human power B is supplied with the output of the latch circuit 37-2. The latch timing clock CKB is obtained from the carry output C of the adder. For example, if the variable magnification signal VR instructs the reduction of the original image by 1/n, and based on this variable magnification signal VR, N/n (for example, 5) J (Nun) is supplied to one human power. , the latch circuit 37- with the first clock signal CKA.
2 latches "5" and inputs the other human power B of the adder 37-1.
supply to. As a result, the adder 37-1 adds "5" supplied to the input of one A and "5" supplied to the other input, and "10" appears at the output. “1” of this output
0" is the second clock signal CKA and the latch circuit 37-
It is latched to 2. Thereafter, the adder 37-1 adds "5" to the sum.
Then, when a carry occurs, this is used as the latch timing clock CKB by the latch circuit 41. Supplied at 43°45. However, if N/n' (for example, "2") is supplied to one input A of the adder 37-1 based on the variable magnification signal VR, the adder 3
Since the sum of 7-1 increases by "2", the generation cycle of the latch timing clock CKB becomes longer.

Therefore, if the number of increases in the sum at the time of equal notification is appropriately selected, the latch timing clock CKB at the time of reduction can be generated based on the variable magnification signal VR. These latch timing clock CKB and read address signal AD
The relationship with H will be detailed later.

Returning again to FIG. 1, the description of one embodiment will be continued.

The line rams 15, 17, and 19 for variable magnification are connected to a latch circuit 41.
43.45, and these latch circuits 41, 43.45 are connected in parallel to the above-mentioned latch timing clock C supplied from the read address generator 37.
The digital color signals DR, DG, and DB output from the variable magnification line RAMs 15, 17, and 19 in response to KB are latched, and the digital color signals DR, DG, and DB latched in the latch circuits 41, 43, and 45 are It is supplied to the color processing circuit 47 in parallel.

Based on the readout address signal ADR generated by the readout address generator 37, the digital color signals DR, DG, and DB read out from the scaling line rams 15, 17, and 19 are actually supplied to the color processing circuit 47. The correspondence relationship between the digital color signals DR, DC, and DB will be explained in detail based on FIG. Figure 3 shows the variable magnification signal VR
Read address signal ADR and latch timing clock CK B when specifying 0° 5x, 1x, and 2x
This is a graph showing changes in When the main scanning synchronization signal Hsync is supplied from the clock generator 35,
The write address generator 33 and the read address generator 37 are reset, and thereafter the clock signal CKA supplied from the clock generator 35
In response to this, the write address is sequentially incremented, and as a result, the write address signal ADW representing the sequentially incremented write address is also output in synchronization with the clock signal CKA. On the other hand, the read address signal ADH increments the address based on the instruction indicated by the variable magnification signal VR. In other words, at the same magnification and when reduced,
The read address advances in synchronization with the clock signal CKA, and when enlarging, it advances at a timing thinned out corresponding to the enlargement magnification (for example, 2 times) indicated by the variable magnification signal VR. On the other hand, the latch timing clock CKB is output in synchronization with the clock signal CKA during equal notification and enlargement, but when reduced (for example, 0.5 times), the latch timing clock CKB is output with a long cycle based on the instruction indicated by the variable magnification signal VR. is output.

Therefore, at the time of notification, the line ram for magnification 15.17
．． Digital color signals DR, DG, held in 19
DB is read out at the same timing as the clock signal CKA, and all digital color signals DR, DG, and DB read out from the variable magnification line ram 15°17.19 are sent to the latch circuit 41. The signal is latched at 43°45 and supplied to the color processing circuit 47.

However, during reduction, the readout address advances in synchronization with the clock signal CKA, so the digital color signals DR, DG, and DB held in the scaling line rams 15, 17, and 19 are read at the same timing as when the image is output. The latch timing clock CKB is read out, and the latch timing clock CKB is 1/2 (0,
5x), so the line ram for variable magnification is 15
, 17. Digital color signal DR output from 19.

DG and DB are intermittently connected to the latch circuit 41. 43. 45
latched to. Therefore, in the case of 1/2 reduction, the color image drawn on the original is sent to the color processing circuit 47 every other pixel in the main scanning direction, and the image reproduced on the paper is reduced to 1/2 of the original image. be done.

On the other hand, for example, when the original image is enlarged twice, the readout address advances at half the speed of the regular image, so the readout address signal ADH is equal to 2 clocks of the clock signal CKA. It will show the same address for a period of . On the other hand, since the latch timing clock CKB is output at the same period as the clock signal CKA, the same digital color signals DR, DG, and DB are latched twice in succession by the latch circuit 41°43.4δ. , the original image will be enlarged twice in the main scanning direction.

Note that the reduction or enlargement in the sub-scanning direction of the variable magnification is performed by changing the relative scanning speed between the original and the image sensor 1. That is, when reducing the original, the relative movement speed between the original and the image sensor 1 is increased. Since the synchronization signal Hsync in the main scanning direction is generated at regular intervals,
The distance that the image sensor 1 moves during one main scan is large, while the distance that the printing device moves during image formation is constant, so the image is reduced. On the other hand, when enlarging the original, the relative movement speed between the original and the image sensor 1 is reduced. As mentioned above, since the main scanning synchronization signal Hsync is generated at regular intervals, the distance that the image sensor 1 moves during one main scan is small, and an image is created by a printing device whose moving distance is constant. , an enlarged image is obtained.

Again, in FIG. 1, the color processing circuit 47 converts the digital color signals DR, DG, and DB according to a predetermined procedure by performing masking processing in accordance with the ink characteristics of the output printing device (not shown), and converts the digital color signals DR, DG, and DB into yellow ink Y. , a color mode signal CL representing the ink amounts of magenta ink M and cyan ink C;
A monochrome mode signal MN is generated by averaging or weighting the color density of the data regarding the amounts of ink of the three colors expressed as the color mode signal C. These color mode signal CL and monochrome mode signal MN are supplied to the selector 49, and the selector 49 selects the color mode signal CL and monochrome mode based on the fourth bit of the attribute control signal AT output from the attribute memory 51, which will be described in detail later. signal MN
Either one of these is sent to the comparison circuit 53. This attribute control signal AT is an 8-bit signal representing attribute data to be described later, and the attribute data is held at each address of the attribute memory 51.

To be more specific, the attribute memory 51 has addresses corresponding to minute ranges obtained by dividing the scanning range of the document into units of, for example, 1 square millimeter, and 8-bit attribute data is written in each address by the central processing unit 39. ing. Further, in response to the read address signal ADX supplied from the selector 56, the attribute data held at the address represented by the read address signal ADX is output. The selector 56 selectively passes the write address signal ADW or the read address signal ADR based on an instruction from the central processing unit 39, and sends it to the attribute memory 5 as a read X address signal ADX.
Supply to 1. The attribute control signal AT output from the attribute memory δ1 is latched by the latch circuit 54 by the latch timing clock CKB.

As previously explained in connection with the latch circuits 41, 43, and 45, the digital color signal DR read out during reduction is
, DG, and DB are intermittently latched, and during enlargement, the read address ADH holds the same value for a long period of time, so the digital color signal DR.

DG and DB are latched redundantly. Similarly, the attribute control signal AT is also intermittently latched by the latch circuit 54 during reduction, while the same X address is held for the duration of a plurality of clock signals during expansion, so the attribute control signal AT represents the same attribute data. The AT can be read out redundantly, and the attribute data can be used as is without being rewritten even when copying the original image at variable magnification. In this embodiment, the attribute data is set for each square millimeter, so the number of attribute data is smaller than the number of digital color signals DR, DG, and DB obtained for the same image portion. Therefore, the X address signal ADX uses only the upper bits of the read address signal ADR.

On the other hand, the Y address signal ADY is output from the address generator 5.
2 is supplied to the attribute memory 51. As shown in detail in FIG. 4, this address generator 52 includes an initial value setting circuit 62-1 and a counter 52-2 that increases the initial value supplied from the initial value setting circuit 52-1 using a clock signal CKA. and a counter 52-3 that sequentially increases the value held by the counter 52-2 and the pull carry C.
In response to the main scanning synchronization signal Hsync, the counter δ2-3
It has a latch circuit 52-4 that latches the value held in the . Y address signal ADY is obtained as the output of this latch circuit 52-4.

In the address generator 52 having such a configuration, the counter 52-2 increases the initial value set by the initial value setting circuit 52-1 using the clock signal CKA, and when a carry C occurs, the counter 52-2 increases the initial value set by the initial value setting circuit 52-1 again. From counter 52-
Since the initial value is set to 2, the timing at which the counter 52-3 is incremented can be adjusted by changing the initial value. As a result, the Y address represented by the Y address signal ADY supplied to the attribute memory 51 is the fifth
As shown in the figure, during reduction, the address value is incremented for each plurality of addresses, and during enlargement, the same address value is held for a period of one sync (multiple main scanning synchronization signals).

To explain in detail with reference to Fig. 5, when reducing (in Fig. 5, 0
．． 5 times), an initial value larger than the value set at the time of equal notice is set in the initial value setting circuit 52-1, so the value of the counter 52-3 increases faster than at the time of equal notice, and the latch circuit 52 -4 latches every other Y address in synchronization with the main scanning synchronization signal Hsync (in Fig. 5, "0", "
2” and 4 are latched). Therefore, the attribute data held at every other Y address is read from the attribute memory δ1, and it is possible to correspond to the reduction of the original image. On the other hand, during enlargement (double time in FIG. 5), the initial value is smaller than that during equal notification.
1, multiple main scanning synchronization signals Hsync
The counter 52-3 holds the same value over the period of occurrence of . Therefore, multiple main scanning synchronization signals) (syn
The latch circuit 52-4 latches the same Y address over the generation period c (two periods in FIG. 5), and can read the same attribute data redundantly. the result,
The attribute memory 51 can output duplicate attribute data in response to enlargement of the original image, and can cope with variable-size copying without rewriting the attribute data.

The attribute data held in the attribute memory 51 will now be explained. As mentioned above, attribute data is 8-bit dO
~d7 data, and each bit do-d7 indicates the following attribute information.

That is, the eighth signal d7 is the color mode signal CL or monochrome mode signal MN output from the selector 49.
This is information that enables or disables the 8th bit, and when this 8th bit is supplied, it becomes possible to fill with a single color. 7th bit) d6 represents attribute information that instructs to invert the information expressed by the color mode signal CL or monochrome mode signal MN, and the 7th bit d6 allows the formation of an image in complementary colors or an image with black and white reversed. becomes possible. 6th bit) d5
is a bit that selects binary processing or dither processing,
When dither processing is selected, image formation in halftones becomes possible. The fifth bit d4 is a bit indicating whether to select color mode or monochrome mode, and the selector 49 outputs a color mode signal C based on this fifth bit d4.
Selection between L and monochrome mode signal MN is executed. Fourth
Bit to second bit) d3 to dl represent a color code that specifies the color during image formation, and the first bit dl indicates whether to inhibit the output of the color mode signal CL or monochrome mode signal MN. There is. The above color code is defined as shown in Table 1 below.

(Margin below) The attribute data made up of 8 bits explained above can be set for each minute part that makes up the scanning range of the image, so
By manipulating bits of image data, editing such as masking, trimming, specified color single color mode, full power exclusive halftone mode, etc. can be performed. For example, part of the image drawn on the manuscript may be a color image and the rest may be a monochrome image, or the image may be printed in a constant color regardless of the color of the image drawn on the manuscript. You can also erase part of the image.

Returning again to FIG. 1, the explanation of the configuration of one embodiment will be continued. 55
indicates a dither ROM, and this dither ROM 55 supplies a threshold value based on the dither method to a selector 57, and the selector 57 outputs a threshold value from the dither ROM 55 in response to the sixth bit (d5) of the attribute data output from the attribute memory 51. The output threshold value or binary threshold value is supplied to the comparator circuit 53. This comparison circuit 53 has the second to fourth bits of the attribute data.
Since bits d1 to d5 and the eighth bit d7 are supplied, if the normal color is selected based on the fifth bit d4, the color mode signal CL supplied from the selector 49
Alternatively, if the color represented by the monochrome mode signal MN is output as is from the comparator circuit 53, and a fixed color is selected by the fifth bit d4, the color coat represented by the second to fourth bits d1 to d3 is output. will be replaced with Further, if the eighth bit d7 indicates validity, the information regarding the shading contained in the signal supplied from the selector 49 is transferred to the selector 57.
is controlled according to a threshold value supplied from

The output signal of the comparison circuit 53 is directly supplied to one input of the selection output circuit 59, and the inverted signal inverted via the inverter 61 is supplied to the other input of the selection output circuit 59. In response to the first bit dO of the attribute data, the selection output circuit 59 inhibits the output of both the output signal of the comparator circuit 53 and its inverted signal, or inhibits the output of both the output signal of the comparison circuit 53 and its inverted signal (the seventh bit) d
In response to a t:L, one of them is supplied to a printing device (not shown). Therefore, in this embodiment, the color processing circuit 47, the selector 49, 57, and the dither ROM 5 are
5, the comparison circuit 53, and the selection output circuit 59 collectively constitute a processing section.

A selection switch 161 is used to instruct variable magnification image formation based on output paper.

Next, the operation of this embodiment will be described using as examples when copying the original shown in FIG. 6 at the same size and when copying at variable magnification.

FIG. 6 is a plan view showing a document on which image [A] is drawn, and in the figure, 61 is an area for specifying full color coloring, and 63 is an area for specifying white color. The attribute designation of such an image is set based on the original. That is, the seventh
As shown in the figure, the address space 71 corresponding to the area 61 of the attribute memory 51 contains (1111xxxl
) is written in the area 63.
Attribute data represented by (01xxooo 1) is written into the address space corresponding to .

When the same-size copying of the original is started after setting the attribute data, the image sensor 1 moves in the sub-scanning direction and converts the red, green, and blue components of the light reflected from the original into different colors. Analog color signals R, G representing intensity,
A/D converter 3. 5. After the analog color signals are converted into digital color signals DR, DG, and DB at step 7, they are corrected at shading circuits 9, 11, and 13. Therefore, as the document is scanned in the sub-scanning direction, the shading circuits 9, 11, 13 supply digital color signals DR, DG, DB for one column in the main-scanning direction to the line rams 15, 17, 19 for scaling.

Line rams 15, 17, and 19 for variable magnification are main scanning synchronization signals H
In synchronization with sync, the digital color signals DR for one column in the main scanning direction are alternately sent to the first storage circuit 21°23.25 and the second storage circuits 27, 29.31.

Memorize DG and DB.

Here, in response to a certain main scanning synchronization signal Hsync, digital color signals DR for one column in the main scanning direction are generated.

DG and DB are written in the first memory circuits 21 and 23.25, and in synchronization with the next main scanning synchronization signal) (sync, the first memory circuits 21 and 23.25 enter the read mode, and the second memory circuit 27 , 29.31 is switched to the write mode.Since the copying is performed at the same magnification, the central processing unit 39 sends the read address signal ADH to the read address generator 37 in synchronization with the write address generator 33. First memory circuit 21.23.2
The selector 56 sends the write address signal A based on the instruction from the central processing unit 39.
DW is supplied to the attribute memory 51 as the X address signal ADX. Further, the address generator 52 for the Y address is supplied from the central processing unit 39 to the initial value setting circuit 52-1.
Based on the initial value supplied to the attribute memory 51, the Y address at the same magnification can be supplied to the attribute memory 51.

Therefore, the read address signal ADR is supplied to the first circuit portions 21, 23.25, and the X address signal AD
When the X and Y address signals ADY are supplied to the attribute memory 51, an image identical to the image on the document is formed on a sheet (not shown) according to the attribute data. That is,
The image portion within area 61 is formed in full color on the paper at a position corresponding to area 61, and the remaining portion on the paper is white.

Next, an explanation will be given of the operation when the image depicted in FIG. 6 is reduced to 172 and created. In case of reduction, the scaling factor is 5.
0% selection switch 161 and central processing unit 3
You can instruct 9. The attribute data in the attribute memory 51 may remain as it is at the time of notification shown in FIG. 7, and there is no need to rewrite it.

When the magnification ratio of 50% is instructed as described above, the central processing unit 39 switches the selection switch 6 as shown in FIG.
1 is on or not (step S1), and when the original is the standard, the judgment result in step S1 is yes (Y), so the selector 56 is switched to select the reading address generator 37 (step S2), and the change is made. Read address generator 37 by magnification signal VR
The latch timing clock CKB is instructed to be adjusted so that the magnification ratio becomes 50%. As a result, the read address generator 37 generates the latch timing clock CKB having a longer period than the clock signal CKA (see the latch timing clock at 0.5 times the clock signal in FIG. 3). In addition, the selector 56 is switched to convert the read address signal ADH to the X address signal AD.
It is supplied to the attribute memory 51 as X. On the other hand, the Y address generator 52 maintains in the initial value setting circuit 52-1 an initial value larger than that at the time of notification corresponding to the magnification ratio of 50% supplied from the central processing unit 39 (step S3).
Intermittent addresses are generated as shown in the Y address at 0.5 times in FIG. As mentioned above, the relative speed between the image sensor 1 and the document is twice as high as when the image sensor 1 is in the same position, and the latch circuits 4.1 and 43.45 latch every other digital color signal DR, DG, and DB. Therefore, the image of the document is reduced to 1/2 in both the main scanning direction and the sub-scanning direction. On the other hand, the attribute data read from the attribute memory 51 is also latched by the latch circuit 54 at every other address in the X address direction and supplied to the selector 49, etc., and the Y address is specified at every other address. Even if the area is reduced to 1/2 in both the main scanning direction and the sub-scanning direction, the attribute data in the address space 71 for the image part in the area 61 is
The attribute data of the address space 73 is respectively applied to the image portions No. 3, and the image portion of the reduced area 61 formed on the paper becomes full color, and the other image portions become white.

Furthermore, when enlarging an image on a document to 2 times, if you instruct the central processing unit 39 to enlarge the image to 200% using a switch (not shown), the central processing unit 39 uses the variable magnification signal VR to generate a reading address generator. 37 to delay the readout address, and the initial value setting circuit 52-1 of the address generator 52 is made to hold a smaller initial value than that at the time of equal notification, so even if the image on the document is enlarged twice. , the image portion corresponding to the enlarged area 61 is imaged according to the attribute data of the address space 71, and the other image portions are imaged according to the attribute data of the address space 73. In this way, this embodiment has the advantage that the attribute data set at the time of image creation does not need to be reset when creating an image at a variable magnification, and editing work at a variable magnification becomes extremely easy.

Further, when the operator operates the selection switch 161 and desires to set attributes based on the output summary, the color processing circuit 47 receives digital color signals DR, DG in accordance with the magnification ratio, as described above. , DB are supplied, but since the judgment result in step S1 becomes NO (N), the selector 56 selects the address generator 33 for writing.
4) The initial value at the time of notification is supplied to the address generator 52 (step S5). Therefore, the attribute data is read from the attribute memory 51 in the same way as when the notification is made.

For example, if the manuscript in FIG. 6 is reduced to 1/2 based on the upper left edge, the attribute data of the address space 71 is applied to the upper and left edges of the area 61, so they become white.
Others are imaged in full color on the output paper.

In the above embodiment, the read address and the
Although the addresses are supplied to each other, dedicated address generators may be provided for each of the scaling line ram and attribute ram.

Further, in the above embodiment, the data in the attribute memory is shown as the data at the time of notification, but this may be set based on data read at an arbitrary magnification.

[Effects of the Invention] As explained above, in the present invention, even when creating an image at variable magnification, the second address signal for reading out attribute data can be selectively transmitted in the same way as when creating an image at variable magnification, or the second address signal for reading out image data. Since the attribute data is generated in response to the generation of the 1 address signal, the attribute data set at the time of notification can be used as is even at the time of changing the size, and the editing work at the time of changing the size can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of a read address generator of one embodiment, and FIG. 3 is a read address signal of one embodiment. FIG. 4 is a block diagram showing the detailed configuration of the X address generator of one embodiment. FIG. 5 is a timing chart showing the generation timing of the X address. FIG. A plan view showing an example of a manuscript for explaining the operation of one embodiment; FIG. 7 is an address map showing the address space of the attribute memory in which attribute data is set for the manuscript of FIG. 6; FIG. 12 is a flowchart of an example of variable magnification image formation. 1... Image sensor, 2... Fluorescent lamp, 3-7... A/D converter, 9-13... Shading circuit, 15-19.・
・Line ram for scaling, 33...Address generator for writing, 35...Clock generator, 37...
...Reading address generator, 39...Central processing unit, 41-45φ...Latch circuit, 47...Color processing circuit, 49...Selector, 61... ...Attribute memory, 52...X address generator, 53...
... Comparison circuit, 55 ... Dither ROM, 57 ... Selector, 59 ... Selection output circuit, 161 ... Selection switch.

Claims (1)

[Scope of Claims] An image data forming section that scans a document line by line and sequentially outputs image data representing each part of an image on the document; It has an image data memory that outputs line by line in response to one address signal, and a plurality of addressable storage areas corresponding to each of a plurality of scanning areas obtained by dividing the scanning range of the image data forming section. , an attribute memory that stores attribute data in each of the plurality of storage areas and outputs the attribute data in response to a second address signal; and a portion of the image represented by the image data read from the image data memory. and a processing unit that changes the attribute of the first address signal according to the attribute data, the image processing device has means for changing the generation of the first address signal according to the magnification, and the second address signal is changed according to the operator's selection. An image processing device characterized in that the generation timing is changed as is or in correspondence with the generation of the first address signal.