JPH01182819A - Optical scanner - Google Patents

Abstract

PURPOSE:To eliminate a need for manual adjustment of the gain of the D/A converter output after varying the output power of a semiconductor laser by adjusting the gain of the A/D converter in accordance with the output of a reference voltage generator. CONSTITUTION:The output of a D/A converter 44 is sent to a computing element 57. A reference voltage generator 63 sends a reference voltage Vref to a comparator 48 and a gain adjusting part 64, and the gain adjusting part 64 adjusts the gain of the D/A converter 44 in accordance with the reference voltage Vref. At the time of turning on a switch 62, the gain adjusting part 64 adjusts the gain of the D/A converter 44 so that the output intensity of a semiconductor laser 42 is most suitably changed by the output value of the D/A converter 44. Thus, it is unnecessary to manually adjust the gain of the D/A converter output after the output power of the semiconductor laser is varied.

Description

[Detailed description of the invention] (Technical field) The present invention relates to an optical scanning device that does not use an fO lens.

(Prior art) An optical scanning device scans a surface to be scanned with a light beam,
It is known as a device for writing optical information or reading image information.

In such optical scanning devices, the light beam is normally deflected at a constant angular velocity by a rotating deflector such as a polygon mirror or a holo scanner. An fO lens is used. However, since the fO lens is a special lens and is expensive, there is a desire to avoid using it if possible.

In addition, polygon mirrors in which the scanning angular velocity of the light beam is not constant have recently been proposed (Japanese Patent Application No. 59-27
No. 4324), in such a case, even if an fO lens is used, the scanning speed will not be constant.

In such cases, the fO lens cannot be used.

The image scanning clock is a clock signal for turning on and off the scanning light beam during optical scanning, and its frequency fk
is given by 1/T, where T is the time allocated to reading or writing information for one pixel. If the fO lens is not used, the scanning speed of the scanned surface by the scanning light beam will not be constant, so the frequency of the image scanning clock fk
If it is kept constant, distortion will occur in the writing and reading of information.

For example, in FIG. 7, reference numeral 30 indicates a photoconductive photoreceptor as an object to be scanned, reference numeral 32 indicates a polygon mirror for deflecting the light beam L at a constant angular velocity, and reference numeral 34 indicates a photoconductor for deflecting the light beam L at a constant angular velocity. The light beam L, which represents a condensing lens for focusing onto the scanning surface, is generally laser light from a gas laser or a semiconductor laser. If the distances Ω and h are chosen as shown in Figure 7.

h=nStanθ Since the angular velocity of the polygon mirror 32 is ω0 (constant), the scanning speed - is t.The scanning area length is <ZU as shown in the figure, and H+h=h''
If so.

Now, assuming that there are 2n pixels in this scanning area length 211, the scanning speed Vn at the nth pixel counted from the scanning start side on the left side of the scanning area in FIG. 7 is. Here, d is 1 pixel width.0 The frequency fk of the image scanning clock is, from its definition, - in this case of V. Therefore, the image scanning clock frequency fk is divided into (1 ), optical scanning can be realized without distortion in reading or writing information without using an fO lens. However, since the scanning speed of the polygon mirror 32 is not constant, the amount of exposure in the scanning area is uniform in the scanning direction, resulting in uneven exposure.

Therefore, an optical scanning device scans the surface to be scanned using a rotary deflector with modulated light from a semiconductor laser, and does not use an fOL/lens. An image scanning lock generator that generates a scanning clock, a digital value setting circuit that generates a digital value for changing the output intensity of the semiconductor laser in accordance with changes in the scanning speed of the scanned surface, and this digital value. In an optical scanning device comprising a digital/analog converter that converts an output value of a setting circuit into an analog value and changes a current of the semiconductor laser according to the analog value, the gain of the output of the digital/analog converter is controlled. A method of adjusting the output intensity of the semiconductor laser according to the output value of the digital/analog converter has been proposed (Japanese Patent Laid-Open No. 62-3046
Publication No. 6).

To explain an example of an optical scanning device to which this method is applied, the image scanning clock generator in this example includes an oscillator, a first frequency divider, an up/down counter, a control circuit, and a phase-locked loop. It has a circuit. The phase-locked loop circuit will be abbreviated as PLL below.

An oscillator generates a reference clock. sfo, where the frequency of this reference clock is hereinafter fo, is a direction constant.

The first divider divides the frequency of the reference clock.

Generates a position control clock.

The up/down counter (hereinafter abbreviated as U/D counter) switches the frequency division ratio N of the first frequency divider.

Of course, N is a natural number.

The control circuit has the following functions. The scanning area is divided in advance into K blocks BLi (1=1 to K), and a predetermined finite number sequence Mi (i==1
~K), the i-th block BLi (i =
In steps 1 to K), the U/D counter is driven every pulse of the position control clock, and stepwise switching of the frequency division N is realized over the entire scanning area. That is, if the initial value of the frequency division ratio N is NO, the position control block f.

Initially, the frequency of BL+O is -, but when this position control block is counted with M1 pulses in the first block BL+O, the control circuit uses the U/D counter.

Change the frequency division ratio of the first frequency divider from No to N+ (=No+ΔN)
Switch to Then, (frequency f of clock for i position control)
.

The wave number is -. The clock with this frequency becomes the old pulse. When this new frequency clock is counted as the old pulse, the frequency division ratio is further switched from NI to Nt. Repeat this n1 times, and continue.

In the second block BL2, the position control block M2
This process of switching the frequency division ratio for each pulse is repeated 12 times for each block. In the i-th block DLi, switching of the frequency division ratio is performed ni times for every Mi pulse of the 1-position control clock.

The PLL circuit includes a 1-phase detection circuit, a low-pass filter, a second frequency divider, and a voltage controlled oscillator.The second frequency divider has a fixed division ratio M.

This PLL circuit has a stage π of the frequency of the position control clock.
An image scanning clock whose frequency changes continuously according to changes in the image quality is generated.

This image scanning clock generator will be explained below with reference to the drawings.

In FIG. 5, the one-phase detection circuit 18. The low pass filter 20, voltage controlled oscillator 22, and second frequency division c24 are PL
It constitutes an L circuit.

The reference clock of frequency fo generated from the oscillator 10 is divided by the first frequency divider 12 to obtain the frequency f.

The signal becomes a position control clock of 1-2, and is input to the control circuit 16 and the phase detection circuit 18 of the PLL circuit.

The phase detection circuit 18 uses this position control clock.

The phase of the clock CLA input from the frequency divider 24 is compared, and the phase difference is output to the low-pass filter 20 as a pulse signal. When the information on the phase difference is input to the voltage controlled oscillator 22 via the low-pass filter 20, the oscillator 22 outputs a clock having a frequency corresponding to the output voltage of the low-pass filter 20.

This clock becomes a one-image scanning clock. The image scanning clock is frequency-divided by a frequency divider 24, applied as a clock CLA to the phase detection circuit 18, and compared in phase with the 1-position control clock.

Now, in the PLL circuit, the frequency of the clock emitted from the voltage controlled oscillator 22 does not change when there is no change in the phase difference between the clock CLA whose phase is compared in the 1-phase detection circuit 18 and the position control clock. This state will be referred to as the balanced state of the PLL circuit.

For example, f for one position control in a balanced state of a PLL circuit.

If the lock frequency is -, then f.

Since the frequency of the lock CLA is also -, in this state, the fk of the clock emitted from the voltage controlled oscillator 22 is
teeth.

It is. In this state, the frequency division ratio of the frequency divider 12 is changed from N to N'
When switching to , the frequency of the position control clock is generated.

Accordingly, the output clock frequency fk of the voltage controlled oscillator 22 changes accordingly, but this change in frequency fk occurs continuously and changes to one frequency fk.

Therefore, by changing the frequency division ratio N of the frequency divider 12 stepwise, the frequency fk of the image scanning clock can be changed continuously.

Now, the control circuit 16 controls a clock CK for outputting a preset value of the frequency division ratio in the frequency divider 12 from the U/D counter 14, a signal EN for enabling the U/D counter 14 to count, and an up/down mode. A signal U/D is issued to determine the

In the up-down mode, the signal U/D is generated so as to switch from the up mode (or down mode) to the down mode (or up mode) near the extreme value of the scanning speed.

When the clock CK is input, the U/D counter 14 updates the preset value and switches the total ratio of the frequency divider 12.

As mentioned above, the clock CK is generated by a finite number sequence Mi (i = 1 to K) for each block BLi (i = 1 to K).
1-K). That is, Mi and ni are set in advance for each block.

At the 1st block opening Li, there is a 1-position control cloflock K.
A clock CK is generated from the control circuit 16 every time 11li pulses are input, and this clock CK is generated ni times in this block [SLi.

The number of blocks, Mi, and ni are determined by the frequency fk of the image scanning clock generated from the voltage controlled oscillator 22.
Frequency change 1 due to change in scanning speed is set to closely approximate equation (1), for example. this is.

It is determined experimentally or theoretically depending on the design conditions.

FIG. 8 shows changes in the ideal image scanning clock fk (curve r
jA4-1) and by switching at the same rate. The numbers 5, 6, 10, and 16 below the 0-step frequency variation, which shows an example of a step-like change in the clock f', are Ml, M2, . Compatible with M3° and M4. As can be seen from the figure, n1 = 6° n2 = 9.
n3=3. n4=5. This figure shows only the right half of the symmetric figure, and M5=10. n5=3.

M6=6. n6=9. M7=5. n7=6. As can be seen from this figure, the block [3Li has a frequency fk
It is an area where a continuous curve of 1 is approximated by a straight line, and the width of the step is equal within each block. The clock f' corresponds to M times the one-position control clock. clock f
' itself changes stepwise, but the frequency of the actual image running clock changes continuously due to the action of the PLL circuit, and closely approximates the song 1jA4-1.

FIG. 6 shows an explanatory timing diagram of the device shown in FIG. 5, in order from the top: synchronization signal, scanning speed, frequency division ratio N1
The up/down mode of the U/D counter 14, which indicates the frequency of the position control clock - the frequency fk of both fine scanning clocks, is switched near the scanning speed of 1 (1, so the 1 frequency division ratio N, fo/N, Both f and k are symmetrical with respect to the position near the slope value.

The synchronization signal is the output of the optical sensor shown at 36 in FIG. 7, and the first frequency divider 12 is initialized by this synchronization signal. The synchronization signal is also applied to the control circuit 16.

The signal IEN causes the counter operation to be performed with a delay of a predetermined time Ta after receiving the synchronization signal, and ends the counter operation with a delay of a time Tb after completion of scanning the print area. Upon completion of the counter operation, the frequency division ratio N is fixed to the initial value.

FIG. 4 shows this circuit configuration.

The digital value setting circuit 41 generates a digital value for eliminating uneven exposure by changing the output intensity of the semiconductor laser 42 in accordance with changes in the light beam scanning speed on the surface to be scanned. is used.

This U/D counter 41 is connected to the control circuit 16 in the image scanning clock generation section 43 as shown in FIG. 9(a).
A clock CK, an enable signal IEN, and an up/down mode signal U/D are applied to the TJ/D counter 14 to perform a U/D count and generate a digital value corresponding to a change in the light beam scanning speed. Further, the digital value setting circuit 41 uses an adder (or wt calculator) as shown in FIG. 9(b) to add (subtract) the output of the U/D counter 14 and a predetermined value. The output of the digital value setting circuit 41 is converted to an analog value by the digital/analog converter 44, and
As shown in Figure 0, the value changes depending on the change in the light beam scanning speed.

On the other hand, the laser beam emitted from the semiconductor laser 42 as described above is focused by a condenser lens 34 and deflected by a polygon mirror 32, as shown in FIG.

An image is formed on the surface of the photoreceptor 30 that is charged by the charger, and the imaged spot moves repeatedly as the polygon mirror 32 rotates, and at the same time, the photoreceptor 30 rotates.

An optical sensor 36 is provided outside the information writing area and detects the laser beam deflected by the polybon mirror 32 to generate a synchronizing signal. The semiconductor laser driving circuit 45 receives the variable A signal in synchronization with the image scanning clock and drives the semiconductor laser 42 based on this variable II times signal, so that the laser beam modulated by the variable A signal is applied to the photoreceptor. 30 to form an electrostatic latent image. This electrostatic latent image is developed by a developing device and transferred onto paper or the like by a transfer device.

The laser beam emitted backward from the semiconductor laser 42 enters a photodetector 46 consisting of a photodiode,
Photodiode 46 outputs a current proportional to the intensity of the laser beam. This current is converted into a voltage by an amplifier 47, and compared with a reference voltage Vref by a ratio V converter 48. The output voltage of the comparator 48 becomes high level or low level depending on the magnitude relationship of the surface input voltage of the comparator 48.
Controls the count mode of the down counter 49.

For example, when the intensity of the laser beam from the semiconductor laser 42 is weaker than the reference value, the output of the comparator 48 becomes a low level, and the up/down counter 49 enters a state in which it operates as an up counter.

The edge detection circuit 50 detects the rising edge of the frame synchronization signal FSYNC which becomes low level in the recording mode.

The detected I-sign passes through an OR circuit 51 and then goes through an AND circuit 52.
AND is performed with frame synchronization figFsYNc.

Flip-flop 53 is set at the beginning of the standby mode by the output signal of AND circuit 52 to produce an output signal, which is ANDed with the non-exposed main scan signal from the signal processing circuit in AND circuit 54. up/
The down counter 49 is enabled by the output No. 13 of the AND circuit 54, and the clock pulse generator 55
The clock pulse from UP/DOWN is 1~. The count output of the up/down counter 49 is converted into an analog quantity by the digital/analog converter 56 and applied to the semiconductor laser drive circuit 45 via the R encoder 5't. The semiconductor laser drive circuit 45 drives the semiconductor laser 42 using the variable li signal from the signal processing circuit, and changes its drive current in accordance with the output of the digital/analog converter 56. Therefore, as the count value of the up/down counter 49 gradually increases, the intensity of the laser beam from the semiconductor laser 42 gradually increases, and the output voltage of the increase Wt 47 increases. During photoconductor scanning, the non-photoconductor scanning signal is lost, the AND circuit 54 is turned off, the up/down counter 49 is disabled, and the semiconductor laser 42 is not driven when the photoconductor is in standby mode. A power set is suspended if it is not yet completed.

Then, when scanning a non-photoreceptor, the power setting of the semiconductor laser 42 is restarted again. After that, when the output of the comparison Wg48 is reversed from low level to high level, the edge detection circuit 5
8 detects the rising edge of the output of comparator 48 and resets flip-flop 53 via OR circuit 60, returning up/down counter 49 to the disabled state. Therefore, the up/down counter 49 holds the count value, and therefore the magnitude of the driving current of the semiconductor laser 42 is held as it is. Furthermore, when the up/down counter 49 is enabled by the output signal of the AND circuit 54, if the output of the comparator 48 is at a high level (if the output intensity of the semiconductor laser is strong), the up/down counter 49 will go down. It operates as a counter and the count value is decreased by the clock signal from the clock pulse generator 55. Therefore, the output of the digital/analog converter 56 decreases, the Na current of the semiconductor laser 42 decreases, and the output of the amplifier 47 decreases. and amplifier 4
The output of comparator 4 becomes smaller than the reference voltage Vref.
When the output of 8 flips from high level to low level, edge detection circuit 58 detects the rising edge of the output of comparator 48 and resets flip-flop 53, returning up/down counter 49 to the disabled state. .

Therefore, the up/down counter 49 holds the count value.

The magnitude of the driving current of the semiconductor laser 42 is maintained as it is. If the edge detection circuit 58 is configured to disable the up/down counter 49 only when the output of the comparator 48 is inverted from a low level to a high level, the output of the comparator 48 will be at a low level. Upload with /
When the down counter 49 is in the enabled state, the comparator 4
When the output of 8 is inverted from a low level to a high level, the up/down counter 49 is disabled and holds the count value. When the output of the comparator 48 is high and the up/down counter 49 is enabled, when the output of the comparator W48 goes from high to low, the up/down counter 49 remains disabled and the comparator The output of 48 causes it to operate as an up counter. When the drive current of the semiconductor laser 42 increases and the output of the comparator 48 is reversed from low level to high level, the error detection circuit 58 detects the rising edge and disables the up/down counter 49. , the count value is held.

Further, the output control timing generator H61 operates in standby mode by the frame synchronization signal FS'11NC.

By generating an output control timing signal at a constant period T and outputting it to the OR circuit 51, the power of the semiconductor laser 42 is set at a constant period.

Note that the up/down counter 49 operates as a down counter when the output of the comparator 48 is at a low level.
8 may operate as an up/down counter when the output is at a high level, and the count value and the drive current of the semiconductor laser 42 may be inversely proportional.

The output of the digital/analog converter 44 is amplified by an amplifier 59 and applied to the semiconductor laser drive circuit 45 via an arithmetic unit 57.
Generates a zero image scan clock that changes the current! At a43, the control circuit 16 uses the output signal of the flip-flop 53 to set the digital value setting circuit 41 so that the output of the digital/analog converter 44 has a value that does not contribute to the semiconductor laser drive circuit 45 when setting the power of the semiconductor laser 42. When the power of the semiconductor laser 42 is not set, the output of the digital/analog converter 56 is held, and the drive current of the semiconductor laser 42 changes according to the change in scanning speed by the output of the digital/analog converter 44. do. The output intensity of the semiconductor laser 42 is controlled to a constant value by the power set.

Its value is a′! by varying the reference signal Vref. Ii can. Furthermore, if the output intensity change of the semiconductor laser 42 due to the output of the digital value setting circuit 41 is appropriate, exposure unevenness due to a change in scanning speed will be eliminated. During production, etc., a worker turns on the switch 62 to set the semiconductor laser output intensity modulation mode, and changes the output intensity of the semiconductor laser 42 to an analog value of the digital/analog converter 44 based on the output of the digital value setting circuit 41. The semiconductor laser drive circuit 45 drives the semiconductor laser with a drive current corresponding to the value calculated by the arithmetic unit 57 from the output value held by the up-down counter 49 and the analog value of the output of the digital/analog converter 56. This semiconductor laser output intensity is measured with a power meter and adjusted by varying the gain of the amplifier 59 so that the maximum value becomes an appropriate value.In this case, the control circuit 16 in the image scanning clock generator 43 The ON signal from the switch 62 forcibly resets the flip-flop 53 via the OR circuit 60 and disables the up/down counter 49.Therefore, the count value of the up/down counter 49 is held. The output intensity of the semiconductor laser 42 is determined by the digital value setting circuit 41 based on the intensity corresponding to the count value.
decreases in response to the output of

In this optical scanning device, the output power P of the semiconductor laser 42 is
The relationship between the change width ΔP, the change width ΔP of the driving current I of the semiconductor laser 42, and the image height is shown in FIGS. 11 and 12, and the semiconductor lasers 42 have greatly different I-P characteristics. Therefore, by adjusting the gain of the output of the digital/analog converter 44 (the gain of the amplifier 59), the change in the output intensity of the semiconductor laser 42 depending on the output value of the digital/analog converter 44 is optimized by varying the Δ factor. I am adjusting it so that it is. However, the output power P of the semiconductor laser 42 to the edge and center of the scanned surface before this adjustment is P^ and Pa, respectively, and the output power P of the semiconductor laser 42 to the edge and center of the scanned surface after adjustment is P^ and Pa, respectively.
Let the output power P of , respectively, be PA' and P's, then after adjusting the gain of the output of the digital/analog converter, the reference voltage Vref is adjusted to vary the output power of the semiconductor laser 42, and P^ is changed to P^'' When it is closed, Δ1 becomes Δwork as shown in Figs. 13 and 14. Therefore,
There is no need to manually adjust the gain of the digital/analog converter to vary ΔI'.

(Objective) An object of the present invention is to improve the above-mentioned drawbacks and provide an optical scanning device that does not require manual adjustment of the gain of the digital/analog converter output after varying the output power of the semiconductor laser. .

(Structure) The present invention is an optical scanning device that scans a scanned surface using a rotary deflector with modulated light from a semiconductor laser and does not use an fO lens. An image scanning clock generator having an analog converter and a gain adjustment section generates an image scanning clock whose frequency changes continuously according to changes in the scanning speed of the scanned surface, and a digital value setting circuit generates an image scanning clock whose frequency changes continuously according to changes in the scanning speed of the surface to be scanned. A digital value is generated for changing the output intensity of the semiconductor laser in accordance with a change in the scanning speed of the scanning surface. The digital/analog converter converts the output value of the digital value setting circuit into an analog value and changes the current of the semiconductor laser according to this analog value, and the gain adjustment section uses the gain of the digital/analog converter to generate a reference voltage. Adjust according to the output of the device.

Next, examples of the present invention will be described.

FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 4 are given the same reference numerals.

In this embodiment, the main circuit operation is the same as that in FIG.
Sent to 7. The reference voltage generator 63 generates a reference voltage Vraf.
is sent to the comparator 48 and the gain g adjustment section 64.

The gain adjustment section 64 adjusts the gain of the digital/analog converter 44 according to the reference voltage Vref. Further, the gain adjustment section 64 adjusts the gain of the digital/analog converter 44 by manual operation when the switch 62 is on.
Adjust so that the change in output intensity in step 2 is optimal. Note that instead of directly manually adjusting the gain of the digital/analog converter 44, an amplifier is provided after the digital/analog converter 44, and the gain of this amplifier is manually adjusted when the switch 62 is turned on. The output intensity of the semiconductor laser 42 may be optimized depending on the output value of the semiconductor laser 44, and this case is also included in the present invention.

When adjusting the image density, the operator must set Vre.
The reference voltage generator 63 uses a device (not shown) to generate the f variable signal.
The reference voltage generator W63 varies the reference voltage Vref using the Vref variable signal. By applying this variable reference voltage Vref to the comparator 48, the output power P of the semiconductor laser 42 is varied, and the density of the image is uniformly adjusted. At the same time, the gain adjustment section 64 adjusts the digital/analog converter 44 according to the varied reference voltage Vref from the reference voltage generator 63, thereby eliminating unevenness in the amount of light.

Gain: lI'! For example, as shown in FIG.
The output voltage according to ef is converted to digital/analog converter 4.
4 and set its gain.

Further, by manually adjusting the variable resistor VR when the switch 46 is turned on, the output is adjusted and the gain of the digital/analog converter 44 is adjusted. Reference voltage generator 63
For example, as shown in FIG. 2, the Vref variable signal from a device (not shown) is converted into a digital/analog converter and a reference voltage Vref is generated.
It is output to the comparator 48 and the gain; * adjustment section 64 as .

This reference voltage generator 63 is an example in which the reference voltage Vref is varied in multiple stages (for example, 46 stages), and for example, the output power of the semiconductor laser 42 is set to 1.2 of the initial emission power.
If the adjustment is to be doubled, the reference voltage Vrefi may be increased by 1.2 times.

When the reference voltage generator 63 varies the reference voltage Vref in three stages, the reference voltage generator 63 uses open-circuit buffers AI, A2. It can also be configured by resistors R3 to R6 and buffer A3. In this case base 2F! Voltage Vr
ef is a power supply voltage Vcc on a Vref variable signal input from a device not shown through a buffer At, A2.
is made up of resistors R3 to R6 and output via buffer A3. For example, this occurs when the Vref variable signal variable signal is off, when the Vref variable signal (2) is off on the Vref variable signal, and this occurs when the Vref variable signal (2) is on on the Vref variable signal. Here, Ri/Rj represents the resistance value of a circuit in which resistor Rj and resistor Rj are connected in parallel.

(Effects) As described above, according to the present invention, there is provided an optical scanning device in which a surface to be scanned is scanned by a rotary deflector with modulated light from a semiconductor laser, and no fO lens is used, and the scanning speed of the surface to be scanned is an image scanning clock generator that generates an image scanning clock whose frequency changes continuously in accordance with changes in the image scanning clock; and a digital value that changes the output intensity of the semiconductor laser in accordance with changes in the scanning speed of the surface to be scanned. It has a digital value setting circuit that generates a digital value, and a digital/analog converter that converts the output value of the digital value setting circuit into an analog value and changes the current of the semiconductor laser according to the analog value. In an optical scanning device that adjusts the gain of the output of the analog converter so that the change in the output intensity of the semiconductor laser depending on the output value of the digital/analog converter is optimized, the gain of the digital/analog converter is adjusted to a reference voltage. Equipped with a gain adjustment section that adjusts according to the output of the generator, it is no longer necessary to manually readjust the gain of the digital/analog converter output after varying the output power of the semiconductor laser, and the reference voltage generator can be adjusted. By providing this, the output power of the semiconductor laser can be easily varied.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing a part of the same embodiment, and FIG. 3 is a block diagram showing a part of another embodiment of the invention. 4 is a block diagram showing the circuit configuration of a conventional optical scanning device, FIG. 5 is a block diagram showing the image scanning clock generator in the same device, FIG. 6 is a timing chart of the same device, and FIG. 7 is a block diagram showing the circuit configuration of a conventional optical scanning device. FIG. 8 is a plan view showing the optical scanning device, FIG. 8 is a diagram for explaining the device, FIGS. 9(a) and (b) are block diagrams showing each digital value setting circuit, and FIG. 10 is a diagram for explaining the device. The timing charts of FIGS. 11 to 14 are diagrams showing the characteristics of the device. 41... Digital value setting circuit, 43... Image scanning clock generator, 44... Digital/analog converter, 63... Reference voltage generator, 64... Gain adjustment section. ChiZenteiσno/? )5F2J

Claims (1)

[Claims] An optical scanning device that scans a scanning surface using a rotating deflector with modulated light from a semiconductor laser and does not use an fθ lens,
an image scanning clock generator that generates an image scanning clock whose frequency changes continuously according to changes in the scanning speed of the surface to be scanned; and an image scanning clock generator that changes the output intensity of the semiconductor laser according to changes in the scanning speed of the surface to be scanned. a digital value setting circuit that generates a digital value to set the output value, and a digital/analog converter that converts the output value of the digital value setting circuit into an analog value and changes the current of the semiconductor laser according to the analog value. and adjusts the gain of the output of the digital/analog converter so that the change in the output intensity of the semiconductor laser depending on the output value of the digital/analog converter is optimized, What is claimed is: 1. An optical scanning device comprising: a gain adjustment section that adjusts the gain of the device according to the output of a reference voltage generator.