JPH01181560A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

Info

Publication number
JPH01181560A
JPH01181560A JP63005059A JP505988A JPH01181560A JP H01181560 A JPH01181560 A JP H01181560A JP 63005059 A JP63005059 A JP 63005059A JP 505988 A JP505988 A JP 505988A JP H01181560 A JPH01181560 A JP H01181560A
Authority
JP
Japan
Prior art keywords
epitaxial layer
layer
conductivity type
type
photodetector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63005059A
Other languages
Japanese (ja)
Inventor
Tetsuya Yamanaka
山中 哲也
Masaru Kubo
勝 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP63005059A priority Critical patent/JPH01181560A/en
Publication of JPH01181560A publication Critical patent/JPH01181560A/en
Pending legal-status Critical Current

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  • Bipolar Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To improve the photosensitivity of a photodetector by a method wherein the conductivity type of the epitaxial layer of the photodetector region is turned into N-type by autodoping and the effective thickness of an N-type epitaxial layer is increased. CONSTITUTION:A second conductivity type (N-type) buried layer 8b is formed in the photodetector region of a first conductivity type (P-type) semiconductor substrate 1 beforehand and a first conductivity type epitaxial layer 7 is made to grow on the semiconductor substrate 1 and a second conductivity type portion 8c is formed in a part of the epitaxial layer 7 corresponding to the buried layer 8b by autodoping. Further, a second conductivity type epitaxial layer 2, is made to grow on the autodoped part to form a photodetector and another second conductivity type epitaxial layer 2' is made to grow on the other part of the first conductivity type epitaxial layer 7 which is not autodoped to form circuit elements. By taking structures like this, the effective thickness of the epitaxial layer 2' of the photodetector part can be increased. With this constitution, the sensitivity of a photodiode, which is the photodetector, can be improved.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、受光素子と共に回路素子を形成させた半導体
受光素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor light receiving element in which a circuit element is formed together with the light receiving element.

(従来の技術) レーザーディスク、コンパクトディスク等の発達に伴な
い、受光素子の利用が増加し、受光素子を単体として使
用する以外に、受光した信号の処理用の回路素子と一体
に構成したものが使用されている。その−例は第2図に
示される。同図において、P型の半導体基板1の上KN
型のエピタキシャル層2を成長させである。エピタキシ
ャル層2を成長させる前に、予め半導体基板lの回路素
子領域部に、N++埋込層5(a)及び受光素子領域部
にN”ffiの埋込層5(b)を設けておくと、これら
はエピタキシャル層2の内部に拡散し、図に示されるよ
うになる。このエピタキシャル層20表面の、埋込層6
(b)に対応する部分に、P+型の拡散層3を設けると
、この両者のPN接合によりホトダイオードが構成され
る。また埋込層5(a)に対応する、エピタキシャル層
2の表面にP+型拡散層からなるベース層4(a)、N
+型型数散層らなるエミツタ層4(b)、及びN+型型
数散層らなるコレクタコンタクト層4(C)等を設ける
と、これらによって、ホトダイオードの出力信号を処理
するためのトランジスタが構成される。ホトダイオード
とトランジスタの領域の間は、P+型の分離拡散層6,
6゜6によって分離されている。
(Prior art) With the development of laser discs, compact discs, etc., the use of light-receiving elements has increased, and instead of using light-receiving elements as a single unit, devices that are integrated with circuit elements for processing received signals are now available. is used. An example thereof is shown in FIG. In the figure, KN on the P-type semiconductor substrate 1 is shown.
A type epitaxial layer 2 is grown. Before growing the epitaxial layer 2, an N++ buried layer 5(a) is provided in the circuit element region of the semiconductor substrate l and an N''ffi buried layer 5(b) is provided in the light receiving element region. , these diffuse into the epitaxial layer 2, as shown in the figure.The buried layer 6 on the surface of the epitaxial layer 20
When a P+ type diffusion layer 3 is provided in a portion corresponding to (b), a photodiode is constituted by a PN junction between the two. Further, on the surface of the epitaxial layer 2, a base layer 4(a) consisting of a P+ type diffusion layer, N
By providing an emitter layer 4 (b) consisting of a + type scattering layer, a collector contact layer 4 (C) consisting of an N+ type scattering layer, etc., the transistor for processing the output signal of the photodiode is formed. configured. Between the photodiode and transistor regions, there is a P+ type isolation diffusion layer 6,
separated by 6°6.

(発明が解決しようとずぶ課題) このような装置において、受光素子であるホトダイオー
ドの感度を向上させるためには、(1)  ホトダイオ
ードとして使用するPN接合の面積を大きくする。
(Problems to be Solved by the Invention) In such a device, in order to improve the sensitivity of the photodiode, which is a light receiving element, (1) the area of the PN junction used as the photodiode is increased;

(2)エピタキシャル層2の厚さを厚くする。(2) Increase the thickness of the epitaxial layer 2.

(3)  エピタキシャル層2の比抵抗を大きくする。(3) Increase the specific resistance of the epitaxial layer 2.

こと等が必要となる。しかしながら、前記の(1)及び
(2)の場合はチップの面積9体積等が増大し、原価が
高くなる。また、(2) p (a)の場合には、回路
素子であるトランジスタのコレクタにおける少数キャリ
アの蓄積時間やコレクタ直列抵抗が増大し、応答速度が
遅くなるという問題があった。
This is necessary. However, in the cases of (1) and (2) above, the area, volume, etc. of the chip increases, leading to an increase in cost. In addition, in the case of (2) p (a), there is a problem that the accumulation time of minority carriers in the collector of a transistor serving as a circuit element and the collector series resistance increase, resulting in a slow response speed.

(課題を解決するための手段) 本発明においては、第1の導電型の半導体基板の受光素
子の領域に予め第2の導電型の埋込層を設け、その上に
第1の導wtmのエピタキシャル層を成長させ、オート
ドーピングにより前記の埋込層に対応する部分に第2の
導電型の部分を形成させ、このオートドーピングされた
部分の上にさらに第2の導電型のエピタキシャル層を成
長させて受光素子を形成させ、残りのオートドーピング
されていない第1の導電型のエピタキシャル層の上に第
2の導電型のエピタキシャル層を成長させて回路素子を
形成させ丸。
(Means for Solving the Problems) In the present invention, a buried layer of the second conductivity type is provided in advance in the region of the light receiving element of the semiconductor substrate of the first conductivity type, and a buried layer of the first conductivity type wtm is provided thereon. Growing an epitaxial layer, forming a second conductivity type part in a part corresponding to the buried layer by autodoping, and further growing a second conductivity type epitaxial layer on the autodoped part. A light-receiving element is formed, and a second conductivity type epitaxial layer is grown on the remaining non-autodoped epitaxial layer of the first conductivity type to form a circuit element.

(作用) 前述のような構造にすることにより、受光素子部のエピ
タキシャル層の実効厚さを厚くすることができる。回路
素子部は受光素子部とは別に最適のエピタキシャル層の
厚さを設定することができる。
(Function) With the structure as described above, the effective thickness of the epitaxial layer of the light receiving element portion can be increased. The optimum epitaxial layer thickness can be set for the circuit element section separately from the light receiving element section.

(実施例〕 本発明の一実施例を第1図<8) 、 (b) 、及び
(c)に示す。
(Example) An example of the present invention is shown in FIGS. 1<8), (b), and (c).

まず、第1図(a)に示すように、P型半導体基板1の
受光素子の領域に、ホトリソグラフィ、不純物拡散によ
りN+型の埋込み層8(b)を形成する。
First, as shown in FIG. 1(a), an N+ type buried layer 8(b) is formed in the light-receiving element region of the P-type semiconductor substrate 1 by photolithography and impurity diffusion.

次に、第1図(b)に示すように、P型の下部エピタキ
シャル層7を成長させ、N+fi+込層8(b)上の下
部エピタキシャル層7が、N中型埋込層8(b)のオー
トドーピング罠より、8層8(c)に゛変化するように
熱処理を施す。この熱処理は、これ以後の工程の熱処理
も含めて、全体として結果的に、埋込層5(b)に対応
する下部エピタキシャル層゛7が8層13 (c)に変
化するように諸条件を設定することができる。熱処理の
条件を変更することにより、受光素子の領域のN中型埋
込層8(b)のオートドーピングをコントロールできる
ので、下部エピタキシャル層7の成長条件線、任意に設
定できる。その後、受光素子と回路素子を分離するため
のP十型埋込層9を形成する。この埋込層9を設けるこ
となく後の工程で分離拡散層を形成することもできる。
Next, as shown in FIG. 1(b), a P-type lower epitaxial layer 7 is grown, and the lower epitaxial layer 7 on the N+fi+ buried layer 8(b) is replaced by the N medium-type buried layer 8(b). Using an auto-doping trap, heat treatment is applied to transform the layer into 8 layers (8(c)). This heat treatment, including the heat treatment in subsequent steps, is performed under conditions such that the lower epitaxial layer 7 corresponding to the buried layer 5 (b) changes into 8 layers 13 (c) as a whole. Can be set. By changing the heat treatment conditions, autodoping of the N medium-sized buried layer 8(b) in the light receiving element region can be controlled, so the growth conditions for the lower epitaxial layer 7 can be set arbitrarily. Thereafter, a P-shaped buried layer 9 is formed to separate the light receiving element and the circuit element. It is also possible to form a separation diffusion layer in a later step without providing this buried layer 9.

さらに、第1図(c)VC示されるように、図の左方の
回路素子の領域において、下部エピタキシャル層7に、
N中型埋込層8(a)を、N中型埋込層8(b)と同様
の方法により、形成させる。その上にN型の上部エピタ
キシャル層2′を成長させ、ホトリックラフィ、不純物
拡散等により、受光素子領域には、ホトダイオード電極
取出し用のN+型型数散層10びホトダイオード用のP
N接合を形成するためめP+型拡散層8′を形成させ、
回路素子領域−ハ、信号処理用トランジスタのペースと
なる戸型拡散層4 ta)’tエミフタとなるN+型型
数散層4b)’及びコレクタコンタクトとなるN+型型
数散層4c)’を形成する。さらに、受光素子と回路素
子の境界には、−素子の分離用のP+型拡散層11.1
1を設け□る。
Furthermore, as shown in FIG. 1(c) VC, in the region of the circuit element on the left side of the figure, in the lower epitaxial layer 7,
The N medium-sized buried layer 8(a) is formed by the same method as the N medium-sized buried layer 8(b). An N-type upper epitaxial layer 2' is grown thereon, and by photo-raffy, impurity diffusion, etc., an N+-type scattering layer 10 for taking out the photodiode electrode and a P layer for the photodiode are formed in the light-receiving element region.
A P+ type diffusion layer 8' is formed to form an N junction,
Circuit element area - C, door-shaped diffused layer 4 which becomes the base of the signal processing transistor ta)'t N+ type scattered layer 4b)' which becomes the emitter and N+ type scattered layer 4c)' which becomes the collector contact. Form. Further, at the boundary between the light receiving element and the circuit element, a P+ type diffusion layer 11.1 for separating the negative element is provided.
Set 1□.

(発明の効果) 上記のような構造にすることにより、受光素子領域の下
部のエピタキシャル層は、オートドーピングによりN型
に変化しているので、N型のエピタキシャル層の実効厚
さが増加し九ことになり、下部エピタキシャル層におい
て光により発生した少数キャリアもホトダイオードの光
電流として寄与する仁とになり、チップ面積を増加する
ことなく受光素子の光感度を向上させることができる。
(Effects of the Invention) With the above structure, the epitaxial layer below the light receiving element region is changed to N type by autodoping, so the effective thickness of the N type epitaxial layer is increased. Therefore, the minority carriers generated by light in the lower epitaxial layer also become particles contributing to the photocurrent of the photodiode, and the photosensitivity of the light receiving element can be improved without increasing the chip area.

また回路素子は所望の応答速度を実現できるエピタキシ
ャルの条件を受光素子と関係なく設定できる。
Furthermore, epitaxial conditions for the circuit element that can achieve a desired response speed can be set independently of the light receiving element.

従来の一例と本発明の一例とを比較したものを下に示す
A comparison between a conventional example and an example of the present invention is shown below.

光感度はホトダイオードの光電流に寄与する光吸収量で
示される。使用された光は、一般的に用いられる半導体
レーザー光であって波長は760nmである。
Photosensitivity is indicated by the amount of light absorption that contributes to the photocurrent of the photodiode. The light used is a commonly used semiconductor laser light with a wavelength of 760 nm.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)(b)及び(c)は、本発明の実施例の工
程及び完成品の断面略図を示し、第2図は従来の例の断
面略図を示す。 !・・・半導体基板  2′・・・N型エピタキシャル
層8′・・・P+拡散層  7・・・P型エピタキシャ
ル層8(a)・・・N++埋込層  8(b)・・・N
++埋込層8(C)・・・8層    9・・・P 型
埋込層10・・・N+型型数散層 11・・・P+型分
離拡欲層特許出願人  シャープ株式会社 代理人 弁理士 福 士 愛 彦
FIGS. 1(a), (b), and (c) show a schematic cross-sectional view of the process and finished product of an embodiment of the present invention, and FIG. 2 shows a schematic cross-sectional view of a conventional example. ! ...Semiconductor substrate 2'...N type epitaxial layer 8'...P+ diffusion layer 7...P type epitaxial layer 8(a)...N++ buried layer 8(b)...N
++ Embedded layer 8 (C)...8 layers 9...P-type embedded layer 10...N+-type scattered layer 11...P+-type separated greedy layer Patent applicant Sharp Corporation Agent Patent Attorney Aihiko Fukushi

Claims (1)

【特許請求の範囲】[Claims] (1)受光素子の領域に第2の導電型の埋込層を設けた
第1の導電型の半導体基板と、前記の半導体基板の上に
形成された第1の導電型のエピタキシャル層と、そのエ
ピタキシャル層の一部に前記の第2の導電塵の埋込層の
オートドーピングによって形成された第2の導電型の部
分とよりなり、オートドーピングされた第2の導電型の
部分の上に受光素子を形成し、オートドーピングされて
いない第1の導電型のエピタキシャル層の残りの部分の
上に回路素子を形成させた半導体受光素子。
(1) a semiconductor substrate of a first conductivity type in which a buried layer of a second conductivity type is provided in a region of a light receiving element; an epitaxial layer of a first conductivity type formed on the semiconductor substrate; A part of the epitaxial layer is of a second conductivity type formed by autodoping the buried layer of the second conductive dust, and a part of the second conductivity type which has been autodoped is formed on a part of the epitaxial layer. A semiconductor light-receiving element in which a light-receiving element is formed and a circuit element is formed on the remaining portion of an epitaxial layer of a first conductivity type that is not auto-doped.
JP63005059A 1988-01-12 1988-01-12 Semiconductor photodetector Pending JPH01181560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63005059A JPH01181560A (en) 1988-01-12 1988-01-12 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63005059A JPH01181560A (en) 1988-01-12 1988-01-12 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPH01181560A true JPH01181560A (en) 1989-07-19

Family

ID=11600826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63005059A Pending JPH01181560A (en) 1988-01-12 1988-01-12 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPH01181560A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141419A (en) * 2000-11-06 2002-05-17 Texas Instr Japan Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141419A (en) * 2000-11-06 2002-05-17 Texas Instr Japan Ltd Semiconductor device

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