JPH01181532A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01181532A JPH01181532A JP305588A JP305588A JPH01181532A JP H01181532 A JPH01181532 A JP H01181532A JP 305588 A JP305588 A JP 305588A JP 305588 A JP305588 A JP 305588A JP H01181532 A JPH01181532 A JP H01181532A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- mask
- substrate
- dry etching
- depths
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims abstract description 28
- 238000001312 dry etching Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 230000004048 modification Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
- 230000009466 transformation Effects 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、より詳しくは、
基体上に深さの異なる溝を同時に設けることが可能な半
導体装置の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more specifically,
The present invention relates to a method of manufacturing a semiconductor device that can simultaneously provide grooves of different depths on a substrate.
（従来の技術）
従来、半導体装置の製造方法においては湿式エツチング
が主流であったが、種々の問題点、例えば半導体クエハ
ーの面方位により順メサになったり逆メサになったりす
るような面方位依存性などの問題点を持つために湿式エ
ツチングに代わってドライエツチングが現在主流になろ
うとしている。但し、このドライエツチングにおいても
１回のエツチングにより形成出来る溝の深さは、マスク
の材料と半導体基板とのエツチング速度の相対値により
決まってしまう。第８図に、従来のドライエツチングに
よる溝の形成法を示、す。図中、１は基体、２はマスク
材料である。この基体１をドライエツチング装置に装着
してエツチングを行なうと、マスク材料２と基体１とめ
エツチング速度の相対比によりエツチング溝の深さが決
まる。通常はこの比をおよそ１：１０（マスク材二基体
）にして溝の深さを深くする訳である。エツチング後の
状態を第９図に示す。基体１の溝４Ａ及び４Ｂの深さは
同じ位で大体３μ程度とすると、マスク材料２も大体０
．３１ｕｍ程度エツチングされて３のようになる。以上
のような理由のためにエツチングに際しては、基体１の
中で最も深い溝に合わせてエツチングするか、何回かに
エツチングをわけて溝の深さを変えなければならなかっ
た。つまり、多数の深さの異なる溝を同時にエツチング
により形成することが出来ないという欠点があった。(Prior Art) Conventionally, wet etching has been the mainstream method for manufacturing semiconductor devices, but it has various problems, such as the surface orientation of the semiconductor wafer, which may become a normal mesa or a reverse mesa depending on the surface orientation. Due to problems such as dependence, dry etching is now becoming mainstream in place of wet etching. However, even in this dry etching, the depth of the groove that can be formed by one etching is determined by the relative values of the etching rates of the mask material and the semiconductor substrate. FIG. 8 shows a conventional method of forming grooves by dry etching. In the figure, 1 is a base and 2 is a mask material. When this substrate 1 is mounted on a dry etching device and etched, the depth of the etching groove is determined by the relative ratio of the etching speed between the mask material 2 and the substrate 1. Usually, this ratio is set to about 1:10 (two mask materials) to increase the depth of the groove. The state after etching is shown in FIG. If the depths of the grooves 4A and 4B in the base 1 are the same and are approximately 3μ, then the mask material 2 also has a depth of approximately 0.
．． It is etched to about 31 um and becomes like 3. For the above reasons, when etching, it is necessary to perform etching to match the deepest groove in the substrate 1, or to divide the etching into several steps to change the depth of the groove. In other words, there was a drawback in that it was not possible to simultaneously form a large number of grooves of different depths by etching.
（発明が解決しようとする問題点）
本発明は、上記従来例の欠点を除去するとともに、１回
のドライエツチングにより深さの異なる溝を基体上に多
数設けることが可能な半導体装置製造方法を提供するこ
とを目的とする。(Problems to be Solved by the Invention) The present invention provides a method for manufacturing a semiconductor device that eliminates the drawbacks of the above-mentioned conventional example and also enables formation of a large number of grooves with different depths on a substrate by one dry etching. The purpose is to provide.
（問題点を解決するための手段）
本発明は、半導体基体上にエツチングによる溝を形成す
る半導体装置の製造方法において、エツチング速度の異
なる２種以上のマスク材料を使用してドライエツチング
するか、あるいは単一マスク材料の一部に変成部を形成
させるかまたは厚みを変えてドライエツチングすること
により、半導体基体に異なる深さのパターンを同時に形
成することを特徴とする半導体装置の製造方法である。(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device in which a groove is formed by etching on a semiconductor substrate. Alternatively, a method for manufacturing a semiconductor device is characterized in that patterns of different depths are simultaneously formed on a semiconductor substrate by forming a metamorphosed part in a part of a single mask material or by dry etching the thickness of the material by changing the thickness. .
以下、本発明を実施例に従い、図を参照しながら説明す
る。Hereinafter, the present invention will be described according to examples and with reference to the drawings.
（実施例１〕
第１〜３図は本発明方法によるドライエツチングによる
実施の１例を示す模式図である。第１゜３図において１
１は基体、１２および１３はエツチング用マスクを示す
。本実施例においては、基体１１は半導体であるＧａＡ
ｓ、マスク１２の材料としてポジレジスト材料である＾
Ｚ１３５０Ｊ （ヘキストジャパン社製）、マスク１３
の材料としてはＳ ｉ０２を用いたが、基体の材料とし
てはＧａＡｓに限らず他の化合物半導体、例えばＩｎＰ
などが用いられ、またマスク１３の材料としてはＳｉ３
Ｎ４ 、Ａｌ２Ｏ３またはＴｉ、 Ｗ％ＭＯなどを用い
た三層レジストなどを用いてもよい。なおマスク１２お
よび１３の厚みはそれぞれ２ＪＡＪ＆、０．５μとした
。(Example 1) Figures 1 to 3 are schematic diagrams showing an example of dry etching according to the method of the present invention.
1 is a substrate, and 12 and 13 are etching masks. In this embodiment, the base 11 is made of semiconductor GaA
s, the material of the mask 12 is a positive resist material ^
Z1350J (manufactured by Hoechst Japan), mask 13
Although SiO2 was used as the material for the substrate, the material for the substrate is not limited to GaAs but also other compound semiconductors, such as InP.
etc., and the material of the mask 13 is Si3
A three-layer resist using N4, Al2O3, Ti, W%MO, etc. may also be used. The thicknesses of the masks 12 and 13 were 2JAJ& and 0.5μ, respectively.
前記半導体基板１１をドライエツチング装置、例えば第
２図に示すＥＣＲを利用したりアクティブイオンエツチ
ング装置（日型アネルバ社： Ｅ（：Ｒ−３１０Ｅ）の
基板ホルダー４０に装着し、エツチング室４１をおよそ
ｌＯ“’ Ｔｏｒｒ、まで高真空排気を行なった後、エ
ツチングを開始した。エツチングを行うリアクティブイ
オンを生ずるガスとしてＣＩ、ガス４２を用い、ガス導
入口４３からイオン源室４４に導入するとともに、マイ
クロ波導入口４５から２．４５ ＧＨｚのマイクロ波を
導入しイオン化してプラズマ流４６を生成させ、基板ホ
ルダー４０上の基板１１にプラズマ流を照射してエツチ
ングを行った。リアクティブイオンを生ずるガスとして
は、Ｃ１２ガスのほか、エツチングされる材料に適した
ガスであれば何であってもかまわない。The semiconductor substrate 11 is mounted on the substrate holder 40 of a dry etching device, for example, an ECR shown in FIG. After performing high vacuum evacuation to lO"' Torr, etching was started. CI gas 42 was used as a gas to generate reactive ions for etching, and was introduced into the ion source chamber 44 from the gas inlet 43. A 2.45 GHz microwave was introduced from the microwave inlet 45 to ionize and generate a plasma flow 46, and etching was performed by irradiating the substrate 11 on the substrate holder 40 with the plasma flow. In addition to C12 gas, any gas suitable for the material to be etched may be used.
本実施例のエツチング条件を表１に示す。Table 1 shows the etching conditions of this example.
表１
ＳＣＣＭ ： ｃｃ／ｗｉｎ （標準状態）上記条件で
エツチングした場合、半導体基板ＩＩのエツチング速度
は約１７００人／ｍｉｎ、であり、前記材料＾Ｚ１３５
０Ｊを用いたマスク１２のエツチング速度は約１５０Ａ
／ｗｉｎ、 、また５ｉ０２を用いたマスク１３のそ
れは約５００人／ｗｉｎ、であった。第３図はエツチン
グ後の形状を示している。エツチング時間が第１図のマ
スク１３の５ｉ０２を完全に除去してしまう時間より短
い場合には、満１５Ａのみが得られるが、長い場合には
５ｉ０２が完全にエツチングされてしまい、半導体基板
１１もエツチングされることになる。本実施例の場合、
第３図の溝の深さは、溝１４＾が２．０４μで満１４Ｂ
が１．７μであった。Table 1 SCCM: cc/win (standard state) When etched under the above conditions, the etching rate of semiconductor substrate II is about 1700 people/min, and the etching rate of the material ^Z135
The etching speed of the mask 12 using 0J is approximately 150A.
/win, and that of mask 13 using 5i02 was about 500 people/win. FIG. 3 shows the shape after etching. If the etching time is shorter than the time to completely remove 5i02 of the mask 13 in FIG. You will be etched. In the case of this example,
The depth of the groove in Figure 3 is 2.04μ for groove 14^, which is full 14B.
was 1.7μ.
以上のように２種のマスク材料を用いて基体上に深さの
異なる２つの溝を同時に形成することができたが、本発
明方法によれば２種類以上のマスク材料を使用して同一
ウニバー内の任意の場所に深さの異なる複数の溝を形成
することができる。As described above, it was possible to simultaneously form two grooves with different depths on the substrate using two types of mask materials, but according to the method of the present invention, two or more types of mask materials can be used to form the same uniform groove. A plurality of grooves with different depths can be formed anywhere within the groove.
また、本実施例においては、エツチングプラズマ４６を
基板ホルダー４０に垂直に入射させて凹状の溝を形成し
たが、基板ホルダー４０に角度をもたせ、基板１１を面
内回転させることで第４図のような形状をもつ溝も得ら
れる。図中のθはエツチングプラズマの入射角である。Further, in this embodiment, the etching plasma 46 was made perpendicularly incident on the substrate holder 40 to form a concave groove, but by setting the substrate holder 40 at an angle and rotating the substrate 11 in the plane, the etching plasma 46 was etched as shown in FIG. A groove having a shape like this can also be obtained. θ in the figure is the incident angle of the etching plasma.
さらに第４図の状態からθ＝θ度としてエツチングする
と、第５図に示すような形状の溝が形成できる。Further, by etching with θ=θ degrees from the state shown in FIG. 4, a groove having a shape as shown in FIG. 5 can be formed.
（実施例２〕
第６図−（１）〜（３）は本発明方法の他の例を示す断
面図である。第６図−（１）に示すように、単一マスク
材料１２、例えばＡＺ１３５０Ｊを基体１１上に形成し
、第６図−（２）のようにイオン打ち込み等によるマス
クレジスト変成部２０を形成する。この基体をドライエ
ツチングすることにより、第６図−（３）に示すように
１回の処理で異なる深さのパターンを基体上に形成する
ことができた。(Example 2) Figures 6-(1) to (3) are cross-sectional views showing other examples of the method of the present invention.As shown in Figure 6-(1), a single mask material 12, e.g. AZ1350J is formed on the base 11, and a mask resist modified portion 20 is formed by ion implantation or the like as shown in FIG. 6-(2).By dry etching this base, the mask resist modified portion 20 is formed as shown in FIG. 6-(3). Thus, patterns with different depths could be formed on the substrate in a single process.
本例においては、変成部２０が通常のレジスト部１２よ
りもエツチング速度が速くなっている例であるが、この
他薬品による硬化変成、例えばクロルベンゼン処理等に
より、エツチング速度を遅くすることも可能である。ま
た、レジスト部１２の一部の厚さを変えることによって
も異なる深さのパターンを基体上に形成できる。In this example, the etching rate of the modified part 20 is faster than that of the normal resist part 12, but it is also possible to slow down the etching rate by hardening and modifying with other chemicals, such as chlorobenzene treatment. It is. Furthermore, by changing the thickness of a portion of the resist portion 12, patterns with different depths can be formed on the substrate.
（実施例３）
第７図−（１）〜（６）はさらに本発明方法の他の例を
示す断面図である。第７図−（１）に示すように基体１
１上に例えば窒化シリコン（Ｓｉ３Ｎ４ ） ３０を形
成し、第１図−（２）に示すレジストパターン１２を形
成する。その後、ドライエツチングあるいは湿式エツチ
ングにより第７図−（３）のようなある一定の深さをも
つパターンを形成する。更にこの基体上にレジストパタ
ーン（第７図−（４））を形成し、ドライエツチングあ
るいは湿式エツチングによりＳｉ３Ｎ４３４の露出して
いる溝３１の部分を完全に除去する。次に第７図−（５
）に示すようなレジストパターン１２を形成し、ドライ
エツチングを行なうことにより、第７図−（６）に示す
ような深さの異なったパターンを基体上に形成すること
ができた。(Example 3) FIGS. 7-(1) to (6) are cross-sectional views showing another example of the method of the present invention. As shown in Figure 7-(1), the base 1
For example, silicon nitride (Si3N4) 30 is formed on the resist pattern 12 shown in FIG. 1-(2). Thereafter, a pattern having a certain depth as shown in FIG. 7-(3) is formed by dry etching or wet etching. Furthermore, a resist pattern (FIG. 7-(4)) is formed on this substrate, and the exposed groove 31 portion of the Si3N434 is completely removed by dry etching or wet etching. Next, Figure 7-(5
) By forming a resist pattern 12 as shown in FIG. 7 and performing dry etching, patterns with different depths as shown in FIG. 7-(6) could be formed on the substrate.
（発明の効果）
以上説明したように、本発明は基体上に基体とエツチン
グ速度の異なる二種以上のマスク材料を用いることによ
り、基体上の任意の場所に深さの異なる多数の溝を１回
のドライエツチングにより形成することが出来るという
極めて優れた効果がある。(Effects of the Invention) As explained above, the present invention uses two or more types of mask materials having different etching rates on the substrate, thereby forming a large number of grooves with different depths at any location on the substrate. It has an extremely excellent effect in that it can be formed by multiple dry etching steps.
さらに、単一マスク材料の一部を変成することによりま
たは単一マスク材料の厚みを変えることにより上記と同
様な効果が得られる。Furthermore, effects similar to those described above can be obtained by modifying a portion of a single mask material or by varying the thickness of a single mask material.
第１図は本発明方法の１例を示す模式的断面図、
第２図は溝を形成するためのドライエツチング装置を示
す断面図、
第３図は本発明方法により基板をドライエツチングした
後の状態を示す模式的断面図、第４〜５図、第６図−（
１）〜（３）、第７図−（１）〜（６）は本発明方法の
他の例を示す断面図、第８〜９図は従来方法による溝形
成法を示す断面図、
である。
１．１１：基体
２．１２：マスク
３：エツチング後のマスク
４Ａ、４Ｂ ：同じ深さのエツチング溝１３：マスク１
２とエツチング速度の異なるマスク１４Ａ、１４Ｂ ：
異なる深さのエツチング溝２０ニレジスト変成部
３０：５ｉ３Ｎ４
３１：溝
特許出願人 キャノン株式会社Fig. 1 is a schematic cross-sectional view showing an example of the method of the present invention, Fig. 2 is a cross-sectional view showing a dry etching device for forming grooves, and Fig. 3 is a schematic cross-sectional view showing an example of the method of the present invention. Schematic sectional views showing the state, Figures 4-5, Figure 6-(
1) to (3), and FIGS. 7-(1) to (6) are cross-sectional views showing other examples of the method of the present invention, and FIGS. 8-9 are cross-sectional views showing a conventional groove forming method. . 1.11: Substrate 2.12: Mask 3: Masks 4A and 4B after etching: Etching grooves of the same depth 13: Mask 1
2 and masks 14A and 14B with different etching speeds:
Etching grooves of different depths 20 Resist metamorphic parts 30: 5i3N4 31: Grooves Patent applicant Canon Co., Ltd.
Claims (1)
体装置の製造方法において、エッチング速度の異なる２
種以上のマスク材料を使用してドライエッチングするか
、あるいは単一マスク材料の一部に変成部を形成させる
かまたは厚みを変えてドライエッチングすることにより
、半導体基体に異なる深さのパターンを同時に形成する
ことを特徴とする半導体装置の製造方法。1. In a method for manufacturing a semiconductor device in which a groove is formed by etching on a semiconductor substrate, 2.
Patterns at different depths can be created simultaneously in a semiconductor substrate by dry etching using more than one type of mask material, or by dry etching a portion of a single mask material to form a metamorphosed region or varying thickness. 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP305588A JPH01181532A (en) | 1988-01-12 | 1988-01-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP305588A JPH01181532A (en) | 1988-01-12 | 1988-01-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01181532A true JPH01181532A (en) | 1989-07-19 |
Family
ID=11546638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP305588A Pending JPH01181532A (en) | 1988-01-12 | 1988-01-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01181532A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5985766A (en) * | 1997-02-27 | 1999-11-16 | Micron Technology, Inc. | Semiconductor processing methods of forming a contact opening |
| US6664032B2 (en) * | 1999-02-16 | 2003-12-16 | Canon Kabushiki Kaisha | Method of producing two-dimensional phase type optical element |
| KR100519540B1 (en) * | 1998-07-09 | 2005-12-05 | 삼성전자주식회사 | Manufacturing Method of Semiconductor Device |
| JP2012209397A (en) * | 2011-03-29 | 2012-10-25 | Toppan Printing Co Ltd | Pattern formation method and pattern formation body |
-
1988
- 1988-01-12 JP JP305588A patent/JPH01181532A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5985766A (en) * | 1997-02-27 | 1999-11-16 | Micron Technology, Inc. | Semiconductor processing methods of forming a contact opening |
| KR100519540B1 (en) * | 1998-07-09 | 2005-12-05 | 삼성전자주식회사 | Manufacturing Method of Semiconductor Device |
| US6664032B2 (en) * | 1999-02-16 | 2003-12-16 | Canon Kabushiki Kaisha | Method of producing two-dimensional phase type optical element |
| JP2012209397A (en) * | 2011-03-29 | 2012-10-25 | Toppan Printing Co Ltd | Pattern formation method and pattern formation body |
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