JPH01181460A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce signal propagation delay, by connecting a word line of a third conductor layer with a plurality of word lines formed by second conductor layer, at specific intervals via switching circuits. CONSTITUTION:The output of an X decoder XD is connected with a main word line MW formed by a third conductor layer of low resistive material like aluminum. This main word line MW is connected with two auxiliary word lines W0, W1 formed by a second conductor layer, at two portions, via two switching circuits SC0, SC1. As to the switching circuits SC0, SC1, the respective operations are controlled by the respective switching signal A0, A1. Namely, when a switching circuit SC0 (or SC1) is selected by a switching signal A0 (or A1), the main word line MW is electrically connected with the auxiliary word line W0 (or W1) at two portions of node points (a), (b), and the signal of the main word line MW is propagated to the auxirialy word line W0 (or W1), thereby restraining the signal propagation delay in a small range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory in which word line signal propagation delay is reduced.

[Conventional technology]

In a semiconductor memory, when word lines are configured to also serve as gate electrodes of MOSFETs for data transfer in memory cells, a high melting point material such as polysilicon or silicide is used for each word line. Such a word line has a relatively large resistance and also has a large capacitive load constituted by a large number of data transfer MOSFETs coupled to it. Such resistance and capacitance reduce the propagation delay of the word line selection signal. large capacity to produce,
This has become a major problem in obtaining high-speed semiconductor memory.

A method to solve this problem is to place low-resistance aluminum wires in parallel with the high-resistance word lines and connect them at predetermined intervals to reduce the apparent resistance of the word lines. There is (Japanese Patent Application Laid-Open No. 58-199557)
.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory described above, a relatively high-resistance gate wiring such as polysilicon is used as the sub-word line, and a low-resistance wiring such as aluminum is used as the main word line. Although resistance can be lowered and higher speeds have been achieved, there is a problem in increasing capacity. In other words, with the miniaturization of memory cells, the pitch of main and sub-word lines must also be made finer to the same extent.However, in terms of -i, upper layer interconnects such as aluminum are smaller than lower layer interconnects such as polysilicon. It is difficult to miniaturize, so if we adopt this word line configuration,
The size of the memory cell is limited by the minimum pitch of the aluminum wiring, which poses a serious problem in increasing capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that is not limited in size by processing technology for upper-layer low-resistance wiring such as aluminum wiring, and can suppress word line signal propagation delay to a small value.

[Means for solving problems]

The semiconductor memory of the present invention includes a memory cell arranged in rows and columns formed on a semiconductor substrate and including transistors and capacitors, a bit line connecting the memory cells in the column direction through a first conductor layer, and a gate electrode of the transistor. In the semiconductor memory, the second conductor layer corresponds to the plurality of word lines formed by the second conductor layer. A switch circuit is provided with a word line formed by a third conductor layer formed in a separate layer, and the word line formed by this third conductor layer is connected to a plurality of word lines formed by the second conductor layer at predetermined intervals. [Example] Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, in which only portions related to word lines are shown. That is, in the figure, the output of the X decoder ,S
A case is shown in which the two sub-word lines WO and Wl formed of the second conductor layer are connected at two locations via CI.

Switch circuits SCO and SCI each receive switch signal A.
Its operation is controlled by O and AI. That is, the switch circuit SCO (
or 5CI) is selected, the main word line MW is electrically connected to the sub-word line WO (or Wl) at two points, nodes a and b, and the signal on the main word line MW is connected to the sub-word line WO (or Wl).
(or is propagated to Wl>.

Next, the operation of FIG. 1 will be explained by taking as an example the case where the memory cell MO is selected. When a semiconductor memory chip is selected, an address is first read into the chip. A part of the switch signal AO is generated to select the switch circuit SCO, and the main word line MW and the sub-word line W are connected to each other.
O and node a.

At the same time, the main word line M is electrically connected at two locations b and is specified by the remaining address taken into the chip.
W is selected by the X decoder XD. At this time, since the switch circuit S01 is unselected, the sub word line W1 remains unselected, but the selected switch circuit SC
A word line selection signal is applied to the sub-word line WO through O, the memory cell MO is selected, and the memory cell M
The binary information held by O is output onto the bit line BO. Thereafter, the minute signal read onto the bit line BO is amplified by the sense amplifier SA using the voltage on B1, which has no output, as a reference voltage.

The above is the operation when selecting the memory cell MO.
When selecting the memory cell M1, the same explanation as in the above case is made by generating the switch signal A1 and selecting the switch circuit SCI.

As mentioned above, by providing one main word line for each of multiple sub-word lines and connecting them under the control of a switch circuit, memory cells that are not limited by main word line processing technology can be created. You will get it. Therefore, it is possible to use upper layer wiring such as aluminum, which is difficult to microfabricate, for the main word line.

Figures 2 to 4 show the switch circuit SCO described in Figure 1,
This is a specific example of an SCI circuit. In these figures,
TN1 to TN4 indicate n-type MO8FETs, TPI, T
P2 indicates a p-type MO3FET.

Figure 2 shows an example of a switch circuit configured with n-type MO3FET, in which MOSFET TNI receives switch signal A (A
The word line W (O or Al) is received at the gate to control the electrical connection between the main word line MW and the sub word line W (WO or Wl). Furthermore, MO3FETTN2 receives a reset signal P at its gate in a struggle to bring the sub-word line W to the ground level.

In this example, the reset MO3FET TN2 is incorporated into each switch circuit, but it is also possible to combine them into one transistor and add it to each sub-word line.

Figure 3 shows the n-type MOS FETTN in the example of Figure 2.
1 is replaced with a p-type MOSFET TPI. By doing this, the n-type MO3FE for reset
The reset signal received at the gate of TTN3 can be the switch signal A.

Figure 4 is a combination of the examples in Figures 2 and 3.
Switch circuits SCO and SCI are p-type and n-type MO3FETs.
TP2. This is an example configured with TN4. By doing so, if the relationship between the switch signals AO and A1 is AO=A4, one of them can be omitted. That is, p-type, n-type MO8FET TP2. Make the gate signal of TP4 common (for example, use n-type MO3FET TN4
A reset signal AO can be applied to the gate of the

In addition, each sub-word line WO, Wl has a reset MOSFET.
Similar to the examples shown in FIGS. 2 and 3, it is also possible to add ET.

〔Effect of the invention〕

As explained above, according to the semiconductor memory of the present invention, the size of the memory cell can be determined without being limited by the processing technology of the upper layer low resistance wiring forming the main word line, and the signal propagation delay of the word line can be This has the effect of keeping it small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 to 4 are circuit diagrams showing specific examples of the switch circuit shown in FIG. 1, respectively. MW...Main word line, WO, Wl...Sub word line,
XD...X decoder, SCO, SCI...switch circuit, MO, Ml...memory cell, AO, Al...
Switch signal, SA... sense amplifier.

Claims (1)

[Claims] A memory cell arranged in rows and columns consisting of transistors and capacitors formed on a semiconductor substrate, a bit line connecting the memory cells in the column direction by a first conductor layer, and a bit line connecting the memory cell to the memory cell which also serves as the gate electrode of the transistor. In a semiconductor memory comprising word lines connected in the row direction by two conductor layers, a plurality of word lines formed in a layer separate from the second conductor layer correspond to the plurality of word lines by the second conductor layer. 3, and the word lines formed from the third conductive layer are connected to the plurality of word lines formed from the second conductive layer at predetermined intervals via switch circuits. A semiconductor memory characterized by