JPH01179538A - Time-division multiplexing device - Google Patents

Time-division multiplexing device

Info

Publication number
JPH01179538A
JPH01179538A JP261188A JP261188A JPH01179538A JP H01179538 A JPH01179538 A JP H01179538A JP 261188 A JP261188 A JP 261188A JP 261188 A JP261188 A JP 261188A JP H01179538 A JPH01179538 A JP H01179538A
Authority
JP
Japan
Prior art keywords
speed line
time
circuit
data
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP261188A
Other languages
Japanese (ja)
Inventor
Toru Honda
透 本多
Fusayoshi Aso
麻生 房儀
Akitoshi Yugawa
湯川 章敏
Fumio Akiyama
秋山 文夫
Keisuke Iwasaki
岩崎 慶介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Computer Electronics Co Ltd
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Computer Electronics Co Ltd
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Computer Electronics Co Ltd, Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Computer Electronics Co Ltd
Priority to JP261188A priority Critical patent/JPH01179538A/en
Publication of JPH01179538A publication Critical patent/JPH01179538A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To improve the traffic efficiency by fetching a carrier detection CD signal into a buffer in the same timing RT as the timing RT fetching a received data RD into a buffer and sending the data RD, CD to an opposite time-division multiplexing device TDM while keeping the relation of time between the RD and CD from a low speed line. CONSTITUTION:In the case of fetching the RD from a low speed line into a buffer circuit 13 comprising a first-in first-out FIFO in the timing RT, the data CD is also fetched in the same timing RT. Then by an OR circuit 14, ORs data CD1 and CD extracted from the FIFO and gives the result as an HCD. That is, the circuit fetching the RD and CD into the buffer 13 acts like storing the RD and CD in the same time because of fetching of the same timing RT. Then the relation of the RD, CD is kept the same as that arrived from a low speed line and sent to the opposite TDM, then no effect is given onto the response.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、低速回線のデータを高速回線に時分割多重す
る多重集配信装置(以下TDMと称す)に係り、特にマ
ルチポイント接続によるキャリア検出信号をオン、オフ
する回線をサポートした時のTDMに好適なCD信号伝
送方式に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiplexing and distribution device (hereinafter referred to as TDM) that time-division multiplexes data on a low-speed line onto a high-speed line, and particularly relates to carrier detection using multi-point connections. The present invention relates to a CD signal transmission method suitable for TDM when supporting a line that turns signals on and off.

〔従来の技術〕[Conventional technology]

従来の装置は、特開昭5i −88140号公報に記載
のように、TDMの低速回線対応部のバッファによるデ
ータの遅れで発生するキャリア検出信号(堤下CDと称
す)と受信データ(以下RDと称す)の重なりを防ぐた
めに、CDオフの情報を相手方TDMの低速回線対応部
で一定数カウントしてから送信要求信号(以下R8と称
す)あるいはCDをオフにしていた。しかし、モデムか
らのRDとCDオフの関係に対し、相手方のモデムへの
送信データ(以下SDと称す)とR,Sオフの関係ある
いは、相手方のCCPへのR,DとCDオフの関係の方
が時間的に長くなり、CDのオン、オフによるレスポン
スが長くなることが配慮されていなか上記従来技術は、
TDMのバッファだよるデータの遅れで発生するRDと
CDの重なりを防ぐために相手方TDMの低速回線対応
部で一定数CDオフをカウントしていた。このため、相
手方TDMのモデム接続時はRSオフの時間が端末装置
接続時はCDオフの時間が長くなり、レスポンスの点に
ついて配慮がされておらず、使用頻度の高い回線では、
使用効率が悪くなるという問題があった。
As described in Japanese Unexamined Patent Publication No. 1988-88140, the conventional device uses a carrier detection signal (referred to as Tsutsukushita CD) and received data (hereinafter referred to as RD), which are generated due to a data delay caused by a buffer in the low-speed line compatible section of TDM. In order to prevent overlapping of CD-OFF information (hereinafter referred to as R8), a transmission request signal (hereinafter referred to as R8) or CD was turned off after counting the CD-off information by a certain number in the low-speed line support section of the other party's TDM. However, in contrast to the relationship between RD from the modem and CD off, there is a relationship between transmission data to the other party's modem (hereinafter referred to as SD) and R, S off, or a relationship between R, D and CD off to the other party's CCP. The conventional technology described above does not take into consideration the fact that the response time due to turning on and off the CD becomes longer.
In order to prevent RD and CD overlaps caused by data delays due to TDM buffers, the low-speed line support section of the other party's TDM counted a certain number of CD offs. For this reason, when the other party's TDM modem is connected, the RS off time is longer, and when the terminal device is connected, the CD off time is longer, and no consideration has been given to response, and on frequently used lines,
There was a problem that usage efficiency deteriorated.

本発明の目的は、従来技術の問題点を排除し、上記目的
は、RDをR,Tのタイミングで、バッファに取込むの
と同じRTのタイミングで、CDをバッファに取込み、
低速回線からのRDとCDの時間関係を保ちつつ相手方
TDMにRDとCDを伝送することによ)達成される。
It is an object of the present invention to eliminate the problems of the prior art, and the above object is to take a CD into a buffer at the same RT timing as the RD is taken into the buffer at the R, T timing,
This is achieved by transmitting the RD and CD to the other party's TDM while maintaining the time relationship between the RD and CD from the low-speed line.

〔作用〕 バッファにRDとCD6取込む回路は、同じタイミング
FLTで取込むので同じ時間のFLDとCDを記憶する
ように動作する。それによって、RDとCDの関係が、
低速回線から来たときと同じに保たれて相手方TDMに
伝送することができるので、CDオフの情報が早くなっ
て、データを破壊したり、CDオフの情報が遅くなって
、レスポンスに影響することがない。
[Operation] The circuit that takes in RD and CD6 into the buffer takes them in at the same timing FLT, so it operates to store FLD and CD at the same time. As a result, the relationship between RD and CD is
Since the data can be transmitted to the other party's TDM while being kept the same as when it came from a low-speed line, the CD-off information may become early and destroy the data, or the CD-off information may become slow and affect the response. Never.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図〜第5図によ。 An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

り説明する。I will explain.

第1図は、本発明が活用されるシステム構成例で、端末
側のモデムM1.M2.M3がマルチポイント接続であ
る。
FIG. 1 shows an example of a system configuration in which the present invention is utilized, in which a terminal side modem M1. M2. M3 is a multipoint connection.

第2図は、第1図の低速回線対応部LAD9の内部構成
図である。
FIG. 2 is an internal configuration diagram of the low-speed line support section LAD9 of FIG. 1.

第5図、第4図は、低速回線対応部I、 A D 1の
内部構成図である。
5 and 4 are internal configuration diagrams of the low-speed line support units I and AD1.

第5図は、第1図のモデムM1からのCDオンオフとR
Dが相手方TDM1の低速回線対応部LAD1のCD、
RDになるまでのタイムチャートである。
Figure 5 shows CD on/off and R from modem M1 in Figure 1.
D is the CD of the low-speed line support section LAD1 of the other party TDM1,
This is a time chart until it becomes RD.

TDM2の低速回線対応部LAD9において、第2図の
低速回線(Ml)からのRDをRTのタイミングで、フ
ァーストイン・7アーストアウト(以下FIFOと称す
)で構成されるバッファ回路16に取込む際、同じRT
のタイミングでCDも取込む。このあと、OR回路14
によりFIFOから取出したCDIとCDの論理利金と
り、HCDとして出力する。このOR回路14の入力の
CDは、CDのオン情報=iR,Dより早く相手方TD
M1に送るためのもので、FIFOバッファ13による
RDの遅延により可能となる。又、FIFOバッファ1
3ヲ辿ったCDIは、CDオフの情報が相手方TDM1
に正確にかつ、余計な遅延を防ぐだめのものである。
When the low-speed line support unit LAD9 of the TDM2 takes in the RD from the low-speed line (Ml) shown in FIG. , same RT
Also import the CD at the same time. After this, OR circuit 14
The logical interest rate of the CDI and CD taken out from the FIFO is calculated and output as HCD. The input CD of this OR circuit 14 is earlier than the ON information of CD = iR,D.
This is for sending to M1, and is made possible by the delay of RD by the FIFO buffer 13. Also, FIFO buffer 1
The CDI traced to 3 has CD off information as the other party's TDM1.
accurately and to prevent unnecessary delays.

HRDとHCDをSEI、回路22により第5図の高速
フレームの通り合成する。この合成した信号iI、AD
9の高速フレーム用データとして、多重制御部T D 
M 2へ送り、多重制御部TDM2で各回線の7レーミ
ングを行い第5図の高速フレームを作って、I)SUl
に送信する。
HRD and HCD are combined by SEI and circuit 22 as shown in the high-speed frame of FIG. This synthesized signal iI, AD
As high-speed frame data of 9, the multiplex control unit T D
The multiplex control unit TDM2 performs 7-raming on each line to create the high-speed frame shown in Figure 5, and I) SUl
Send to.

第5図の高速フレームを作る際、第2図のOR。When creating the high-speed frame shown in Fig. 5, use the OR shown in Fig. 2.

回路14により、CDのオン情報は有効なRD (D4
、D5.D6 )に対し遅れることなく伝送が可能であ
る。又、CDのオフ情報は、前のフレームの最終RD(
D7)の時のCD(C7)を伝送することにより、RD
とCDの関係が保たれたまま相手方TDM1への伝送が
可能となる。
By the circuit 14, the ON information of the CD is changed to a valid RD (D4
, D5. D6), transmission is possible without delay. Also, the CD off information is the last RD of the previous frame (
By transmitting the CD (C7) at the time of D7), the RD
Transmission to the other party's TDM 1 is possible while maintaining the relationship between the data and the CD.

これに対し、相手方TDM1の低速回線対応部LAD1
では、第5図の高速フレームの中の自分の回線分のデー
タだけを、第3図あるいは、第4図の回路にて取出し、
第5図のCD、RDに分解してCCPに伝える。ここで
、第3図の場合は、CDオフまでのデータを保障するた
めに、FF回路15.16によるシフトレジヌタを用い
た例で、第4図はFIFOを用いた例である。第3図の
OR回路17、第4図のOR回路21のHCDはオン情
報を最優先で伝えるためで、HCDlはオフ情報がデー
タを追越すことなく伝えるための信号で、それぞれの論
理和をCDとして低速回線に伝える。
In contrast, the low-speed line support section LAD1 of the other party TDM1
Now, extract only the data for your own line in the high-speed frame shown in Fig. 5 using the circuit shown in Fig. 3 or 4,
It is broken down into CD and RD as shown in Figure 5 and sent to CCP. Here, the case of FIG. 3 is an example in which a shift register with FF circuits 15 and 16 is used to guarantee data until CD-OFF, and FIG. 4 is an example in which a FIFO is used. The HCD of the OR circuit 17 in FIG. 3 and the OR circuit 21 in FIG. Send it to a low-speed line as a CD.

第3図と第4図の違いは、CDをサンプリングするタイ
ミングが違う点で、第5図に示す通り第6図はCDを取
込むタイミングRT2で、第4図は0、RDを取込むタ
イミングRT1でCD情報をサンプリングしている。従
い、第2図の回路により、TDM2側のLAD9でCD
オフの情報がデータより遅れて送信されてくるならば、
第5図のようにRT2による取込みの方が、時間の遅れ
が少な(’CD信号をオフできる。しかし、その時間的
な遅れは、高速データの1ビット時間に相当し、低速回
線の速度が遅く、レスポンスに影響のないときけ、第4
図の回路が物量的に小さく有効である。
The difference between Fig. 3 and Fig. 4 is that the timing of sampling the CD is different.As shown in Fig. 5, Fig. 6 is the timing to take in the CD, RT2, and Fig. 4 is the timing to take in 0 and RD. CD information is sampled at RT1. Therefore, with the circuit shown in Figure 2, CD
If the off information is sent later than the data,
As shown in Figure 5, there is less time delay when importing by RT2 ('CD signal can be turned off. However, the time delay is equivalent to 1 bit time of high-speed data, and the speed of low-speed line is When it is slow and does not affect the response, the fourth
The circuit shown in the figure is small and effective.

以上、本実施例によれば、CDオフ情報がデータを追越
すことなく、かつ大幅に遅れることなくCDの伝送が可
能である。
As described above, according to this embodiment, it is possible to transmit a CD without the CD off information overtaking the data and without significant delay.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、モデムインタフェースの受信データと
キャリア検出信号の同時性が保たれキャリア検出信号の
オン、オフによる一定の回線の専有時間が短縮され、レ
スポンスの向上によるトラフィックの効率向上に効果が
ある。
According to the present invention, the simultaneity of the received data of the modem interface and the carrier detection signal is maintained, the exclusive time of a certain line is shortened by turning on and off the carrier detection signal, and the efficiency of traffic is improved by improving the response. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例のシステム構成図1、第2
図〜第4図は、低速回線対応部のブロック図1、第5図
は、CD、RDの関係を示すタイムチャートである。 1・・・通信制御装置(CCP) 2.7・・・低速回線対応部(1・AI)1〜16)3
.6・・・多重制御部(TDMl、2)4.5・・・回
線終端装置(DSU’+、2)8^10・・・モデム(
M1S5) 11、12・・・端末装置(T1.2)13、18.1
9・・・バッファ 14、17.21・・・OR回路(OR)躬 1 口 躬2固 躬3図 躬( q 躬5国
FIG. 1 shows system configuration diagrams 1 and 2 of an embodiment of the present invention.
1 to 4 are block diagrams of the low-speed line support section, and FIG. 5 is a time chart showing the relationship between CD and RD. 1... Communication control device (CCP) 2.7... Low speed line support unit (1/AI) 1-16) 3
.. 6... Multiplex control unit (TDMl, 2) 4.5... Line termination unit (DSU'+, 2) 8^10... Modem (
M1S5) 11, 12...Terminal device (T1.2) 13, 18.1
9...Buffer 14, 17.21...OR circuit (OR) 1.

Claims (1)

【特許請求の範囲】[Claims] 1、時分割方式の多重集配信装置において、多重集配信
装置の低速回線のモデムインタフェース信号のキャリア
検出信号を多重集配信装置間を通して伝送する場合、モ
デムインタフェース信号の受信データを受信タイミング
でバッファリングする時に、受信データとともにモデム
インタフェース信号のキャリア検出信号も同時にバッフ
ァリングする回路と、バッファリングしたあとのキャリ
ア検出信号オフあるいはオン情報を高速回線を通して相
手方多重集配信装置に伝える回路と、前記キャリア検出
信号オフあるいはオン情報を高速回線を通して伝えられ
て該当する低速回線のモデムインタフェース信号のモデ
ム接続時は送信要求信号を端末装置接続時はキャリア検
出信号をオフあるいは、オンにする回路を有することに
より、受信データに対するキャリア検出信号の時間のず
れを少なくし、特定の回線が専有する時間を短縮するこ
とを特徴とした多重集配信装置。
1. In a time-division multiplexing and distribution device, when transmitting the carrier detection signal of the modem interface signal of the low-speed line of the multiplexing and distribution device between multiplexing and distribution devices, the received data of the modem interface signal is buffered at the reception timing. a circuit that simultaneously buffers the carrier detection signal of the modem interface signal along with the received data; a circuit that transmits information on whether the carrier detection signal is off or on after buffering to the other party's multiplexing/distributing device through a high-speed line; By having a circuit that transmits signal off or on information through a high-speed line and turns off or on the transmission request signal when the modem is connected to the corresponding low-speed line modem interface signal and the carrier detection signal when the terminal device is connected, A multiplexing and distributing device characterized by reducing the time lag of a carrier detection signal with respect to received data and shortening the time that a specific line is exclusively occupied.
JP261188A 1988-01-11 1988-01-11 Time-division multiplexing device Pending JPH01179538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP261188A JPH01179538A (en) 1988-01-11 1988-01-11 Time-division multiplexing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP261188A JPH01179538A (en) 1988-01-11 1988-01-11 Time-division multiplexing device

Publications (1)

Publication Number Publication Date
JPH01179538A true JPH01179538A (en) 1989-07-17

Family

ID=11534192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP261188A Pending JPH01179538A (en) 1988-01-11 1988-01-11 Time-division multiplexing device

Country Status (1)

Country Link
JP (1) JPH01179538A (en)

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