JPH01176391A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect a fault within the short period of time by corresponding with two sets of inverter circuits constituting a static type memory cell, providing two electric power source voltage supply lines and providing a data set circuit to selectively supply the grounding potential of a circuit on either of the electric power source voltage supply line. CONSTITUTION:Two power source voltage supply lines VAo-VAm, VBo-VBm are provided to correspond with two sets of inverter circuits Q1, Q21, Q2, and Q22 constituting the static type memory cell, the electric source voltage of a circuit is normally supplied to these electric source voltage supply lines, when a prescribed control signal is effective, the data set circuit DSC to selectively supply the grounding potential of the circuit to either of the electric source voltage supply lines VAo-VAm, VBo-VBm is provided. Thus, the holding data of a memory cell can be arbitrarily and shortly inverted through the electric source voltage supply VAo-VAm, VBo-VBm and corresponding loads MOSFETQ1, and Q2, the normality of the load MOSFETQ1, Q2 of the memory cell can be confirmed, since the test time of the memory cell can be shortened, the test tie of a logical integrated circuit or the like is shortened and a low cost is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
Static RAM (Random Access Memory) built into logic integrated circuits such as microcomputers
This article relates to techniques that are particularly effective when used for such purposes.

[Conventional technology]

There is a static type RAM built into a logic integrated circuit such as a microcomputer. Static type RAM is
For example, the basic configuration is a memory array in which 0 MO3 (complementary MO3) static type memory cells are arranged in a grid pattern.

The static memory cells constituting the memory array are, for example, P-channel MOSFETs as shown in FIG.
A CMOS inverter circuit consisting of SFETQ3 and N-channel MOSFETQ37, and a P-channel MOSF
Another CMOS inverter circuit consisting of ETQ4 and N-channel MOSFETQ38 is cross-connected to include a flip-flop circuit. Of these, N-channel MOSFETs Q37 and Q38 are drive MOSFETs.
functions as P-channel MOSFETs Q3 and Q4
The commonly coupled input/output terminals of both inverter circuits functioning as load MOS FETs are input/output nodes of a flip-flop circuit, and a pair of transmission gate MOS
It is coupled to the corresponding complementary data line DO/10τ via FETs Q39 and Q40. Above transmission gate MOSFE
The gates of TQ39 and Q40 are connected to the corresponding word line WO
are commonly combined.

For static type RAM, for example,
-184790, etc.

[Problem that the invention seeks to solve]

The above-mentioned static type RAM has the following problem. Namely, in the static type memory cell shown in FIG. and Q
40, and correspondingly the flip-flop circuit is set or reset. In other words, the stored information is stored in the drive MOSFETQ39.
and Q40 in the form of charges, and these charges are complementary to the load MOSFET that is turned on.
The leakage amount is replenished via Q3 or Q4. Therefore, the load MOSFETs Q3 and Q4 are set to the minimum necessary size so as to have a conductance sufficient to compensate for the leakage of charge, and the number of contacts provided in the diffusion layer thereof is usually only one. For this reason,
In these memory cells MC, there is a relatively high possibility that a failure such as a disconnection will occur, for example, at a position indicated by an x in FIG. 2. Moreover, even if the load MOSFET Q4 becomes non-functional due to the above-mentioned failure,
The memory cell has a gate capacitance C of drive MOSFET Q37.
The charge stored in g allows normal storage data to be retained for a period corresponding to the dynamic information retention time. This causes the memory cell to have its load MO
Even though the SFET has a fault, it is considered normal.

To deal with this, write/write data to all memory cells is
If a read test is performed at a time interval longer than the discharge time of the gate capacitance, that is, the dynamic information retention time of the memory cell, the test time becomes enormous and the manufacturing cost increases. It is also possible to reduce the above test time by lowering the power supply voltage (or increasing the ambient temperature) to shorten the dynamic information retention time of the memory cells. etc., if the power supply voltage is lowered or the ambient temperature is raised, the peripheral logic section will malfunction, making it impossible to perform a normal functional test.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device such as a static RAM that reduces test time for memory cells. Another object of the invention is to provide a static type R
Shortens test time for logic integrated circuits with built-in AM, etc.
The aim is to reduce costs.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, two power supply voltage supply lines are provided corresponding to the two sets of inverter circuits that constitute a static memory cell, and the power supply voltage of the circuit is normally supplied to these power supply voltage supply lines so that a predetermined control signal is valid. A data set circuit is provided for selectively supplying the ground potential of the circuit to either one of the power supply voltage supply lines when the power supply voltage is set.

[For production]

According to the above means, it is possible to invert the data held in the memory cell arbitrarily and in a short time via the power supply voltage supply line and the corresponding load MOSFET, and it is possible to invert the data held in the memory cell arbitrarily and in a short time. By making this determination, the normality of the load MOSFET of the memory cell can be confirmed. As a result, the test time for memory cells can be shortened, so the test time for logic integrated circuits and the like including static RAMs can be shortened and costs can be reduced.

〔Example〕

FIG. 1 shows a circuit block diagram of a CMOS static type RAM to which the present invention is applied. The static RAM of this embodiment is, although not particularly limited, built into a logic integrated circuit such as a microcomputer. Each circuit element constituting the static RAM is formed on a single semiconductor substrate such as, but not limited to, single crystal N-type silicon, together with circuit elements constituting other blocks of the logic integrated circuit. In addition, in FIG. 1, an arrow is added to the channel (back gate) section.
The OSFET is a P-channel type, and is shown to be distinguished from the N-channel MOSFET, which is not marked with an arrow.

The static RAM of this embodiment is activated by changing the chip selection signal T from a high level to a low level, although this is not particularly limited.

At this time, when the data cent mode signal DS is at a high level, the static RAM is placed in a normal operation mode, and is selectively put into a write operation mode or a read operation mode according to the write enable signal WE. When the chip selection signal C3 is changed to low level and the data center mode signal DS is low level, the static type RAM is placed in the data set mode. At this time, the static type RAM is a memory array MARY.
The data held in all the memory cells MC constituting the memory cell MC is selectively set to logic "0" or logic "1" according to the write data supplied via the data input terminal DI.

In FIG. 1, the memory array MARY has m+1 word lines WO-y W arranged in parallel in the horizontal direction.
m, and n+1 sets of complementary data lines DO-DO to Dn- arranged in parallel in the vertical direction are arranged in a grid pattern below and below and at the intersections of these word lines and complementary data lines (m±1)
x (n+1) (liiil) static type memory cells MC.

Each of the memory cells MC includes a P-channel MOSFET QI and an N-channel MOSFET that are connected in series, as exemplarily shown in FIG. 1, although there are no particular restrictions.
TQ21 and P channel MO5FETQ2 and N
It includes first and second CMOS inverter circuits each consisting of a channel MOSFETQ22. In these inverter circuits, N-channel MOSFETs Q21 and Q2
2 functions as a drive MOSFET, and P-channel MOSFETs QI and Q2 function as load means for the drive MOSFET. The above two sets of inverter circuits constitute one flip-flop circuit by having their input terminals and output terminals cross-connected to each other. The two sets of commonly coupled input and output terminals are input/output nodes a and b of the flip-flop circuit.

The input/output nodes a and b of the flip-flop circuits constituting the m+1 memory cells MC arranged in the same column of the memory array MARY are connected via a corresponding pair of N-channel type transmission gate MOSFETs Q23 and Q24. They are respectively coupled below the complementary data lines DO and Dn-D.

The gates of the transmission gate MOSFETs Q23 and Q24 of the n+1 memory cells MC arranged in the same row of the memory array MARY are commonly coupled to the corresponding word lines WO to Wm, respectively.

In the static RAM of this embodiment, the sources of one load MOSFETQI of n+1 memory cells MC arranged in the same row of the memory array MARY are connected to the corresponding power supply voltage supply lines VAO to VAm (second power supply voltage supply lines). Similarly, the source of the other load MOSFET Q2 of fi+1 memory cells MC arranged in the same row of the memory array MARY is
They are commonly coupled to corresponding power supply voltage supply lines VBO to VBm (third power supply voltage supply lines), respectively. Further, the sources of the driving MOSFETs Q21 and Q22 of n+1 memory cells MC arranged in the same row of the memory array MARY are common to the corresponding ground potential supply lines GO to Gm (first power supply voltage supply line), respectively. be combined.

The power supply voltage supply lines VAO to VAm are connected to the corresponding CMOS of the data set circuit DSC, although not particularly limited.
It is coupled to the output terminals of inverter circuits N1 to N2, respectively. P-channel MOS FET and N-channel MOS F making up inverter circuit N1-N2
ET is designed to have a relatively large conductance. Input terminals of inverter circuits N1-N2 are further coupled to output terminals of corresponding NOR gate circuits N0GI-NOG2. One of the input terminals of the NOR gate circuits N001 to N0G2 is connected to a data buffer DI, which will be described later.
A non-inverted internal write signal wd is commonly supplied from B. The other input terminals of the NOR gate circuits N0CI-NOG2 are commonly supplied with an inverted timing signal φsa from a timing generation circuit TO, which will be described later. The non-inverted internal write signal wd is sent to the data input terminal D as described later.
It is formed according to write data supplied via I. Further, the inverted timing signal 7Tτ is set to a high level when the static RAM is in a normal operation mode, and is temporarily set to a low level at a predetermined timing when the static RAM is set to a predetermined test mode.

Similarly, the power supply voltage supply lines VBO to VBm are connected to the corresponding CM of the data set circuit DSC, although not particularly limited thereto.
It is coupled to the output terminals of OS inverter circuits N3 to N4, respectively. The P-channel MOSFET and N-channel MOSFET that constitute inverter circuits N3 and N4 are designed to have relatively large conductance. Input terminals of inverter circuits N3-N4 are further coupled to output terminals of corresponding NOR gate circuits N0G3-N0G4. An inverted internal write signal wd is commonly supplied to one input terminal of the NOR gate circuits N003 to N0G4 from the data input buffer sofa DIB. Further, the other input terminals of the NOR gate circuits N003 to N0G4 are commonly supplied with the above-mentioned inverted timing signal φsa from the timing generation circuit TO; a 0 inverted internal write signal;
i is formed complementary to the non-inverted internal write signal Wd according to write data supplied via the data input terminal DI.

Further, the ground potential supply line G O-G m connects the corresponding N-channel MOSFETs Q33 to Q34 (the first M
OSFET) to the ground potential (first power supply voltage) of the circuit. These MOSFETQ33~Q
34 are designed to have relatively small conductance and have their gates coupled to their respective drains to form a diode. Ground potential supply line G O-
G m further represents N-channel MOSFETs Q35 to Q35, which are provided in parallel to the MOSFETs Q33 to Q34.
Coupled to circuit ground potential via Q36.

These MOSFETs Q33-Q34 are designed to have relatively large conductance.

An inverted timing signal 7sb is commonly supplied from the timing generation circuit TG to the gates of the MOSFETs Q35 to Q36. This inverted timing signal φsb is set to a high level when the static RAM is in a normal operation mode, and is temporarily set to a low level together with the inverted timing signal 77T when the static RAM is set to a predetermined test mode. .

For these reasons, when the static RAM is in the normal operation mode and the inversion timing signal 7Ti is set to high level, the NOR gate circuits N0GI to N0G2
and N0G3 to N0G4 (7) output signals are all at low level regardless of the non-inverted internal write signal wd and the inverted internal write signal wd. Therefore, the output signals of the inverter circuits N1 to N2 and N3 to N4 become high level, and the power supply voltage supply lines V A O to V-Am and VB
The power supply voltage Vcc (second power supply voltage) of the circuit is supplied to θ~■Bm via the P-channel MOS FET of CMOS inverter circuits N1~N2 and N3~N4. At this time, the above Since the inverted timing signal φsb is also set to high level, MOSFETs Q35 to Q30 having relatively large conductance are turned on. Therefore, the ground potential supply lines GO to Gm have
The ground potential of the circuit is supplied through the MOSFETs Q35 to Q36 and Q33 to Q34, which have relatively small conductance. Thereby, all memory cells MC of memory array MARY function as normal static type memory cells.

On the other hand, when the static RAM is put into a predetermined test mode and the inverted timing signals φsa and φSb are temporarily set to low level, in the data center circuit DSC, the inverted timing signal φ3b is first set to low level, so that relatively MOSFETQ with large conductance
35 to Q36 are turned off. Therefore, the ground potential supply &jLGO-Gm is coupled to the ground potential of the circuit only through MOSFETs Q33 to Q34 having relatively small conductance. In the data set circuit DSC, the inverted timing signal φsa is further set to low level, so that the NOR gate circuit N is activated.

The output signals of Gl~NOG2 and N003~NOG4 are
It is selectively set to high level according to the non-inverted internal write signal wd and the inverted internal write signal wd. That is, when the inverted timing signal psτ is set to a low level, the write data supplied via the data input terminal DI is logic "0" and the non-inverted internal write signal w
When d is set to low level, NOR gate circuit N0G1
The output signals of ~NOG2 are selectively set to high level.

Therefore, the output signals of the inverter circuits N1 to N2 become low level, and the power supply voltage supply lines VAO to VAm have
N-channel MOSFET of inverter circuit N1-N2
The ground potential of the circuit is supplied through the circuit. At this time, NOR gate circuit N.

The output signals of 03 to N0G4 are set to low level, and the power supply voltage Vcc of the circuit is supplied to the power supply voltage supply lines VBO to VBm. Therefore, all the memory cells MC constituting the memory array M A RY have their load MOS F
Logic “0” only if ETQ 2 functions normally.
” is held in one set state. At this time, the ground potential supply line Go-Gm is set as
MOSFETQ33 with relatively small conductance
~Q34, coupled to the ground potential of the circuit. Therefore, the level difference between notes a and b of the flip-flop circuit of each memory cell MC is compressed, and the reversal operation of each memory cell MC to the reset state is sped up.

If a fault such as a disconnection occurs in one of the memory cells MC and the load MOSFET Q2 cannot function normally,
In that memory cell MC, the node b remains at a low level and cannot be reversed from the set state to the reset state.

When the inverted timing signal φsa is set to low level,
When the write data supplied via the data input terminal DI is logic "L" and the above-mentioned inverted internal write signal wd is set to low level, the NOR gate circuits N0G3 to N0G3-N
The output signal of 0G4 is selectively set to high level. Therefore, the output signals of the inverter circuits N3 to N4 become low level, and the ground potential of the circuit is supplied to the power supply voltage supply lines VBO to VBm via the inverter circuits N3 to N4ON channel MOSFETs. At this time, the output signals of the NOR gate circuits N0G1 to N0G2 are set to a low level, and the power supply voltage Vcc of the circuit is supplied to the power supply voltage supply lines VAO to VAm.

In addition, as mentioned above, the ground potential supply lines GO to Qm are connected to MOSFETs Q33 to Q33, which have relatively small conductance.
It is coupled to the circuit ground potential via Q34. Therefore, all memory cells MC constituting the memory array MARY are brought into a set state in which they hold stored data of logic "1" only when their load MOSFET QI functions normally. If a fault such as a disconnection occurs in any memory cell MC and the load MOSFET QI cannot function normally, the node a of that memory cell MC remains at a low level and cannot be reversed from the reset state to the set state.

In FIG. 1, word lines W OW m constituting memory array MARY are coupled to an X address decoder XDCR and are selectively brought into a selected state according to X address signals AXO to AXi.

The X address decoder XDCR receives i+1-bit complementary internal address signals axQ to xi (here, for example, a non-inverted internal address signal axQ and an inverted internal address signal axQ are combined to generate a complementary internal address signal from an A signal axQ (the same applies hereinafter) is supplied. Further, a timing signal φce is supplied from the timing generation circuit TG. This timing signal φce is normally set to a low level, and is set to a high level at a predetermined timing when the static RAM is placed in the sent state.

The X address decoder XDCR receives the timing signal φ
By setting ce to a high level, the device is selectively put into an operating state. In this operating state, the X address decoder
The DCR decodes the complementary internal address signal axOxaxi and outputs one corresponding word line WO=W m
is alternatively set to the /S level selection state.

The X address buffer node XADB is connected to an address input terminal AX from a memory control unit (not shown) of the logic integrated circuit.
X address signal AXO= supplied via O”AXi
Capture and hold AXi. Also, based on these X address signals AXO to AXi, the complementary internal address signals axQ to -ax i are formed and supplied to the X address decoder XDCR.

On the other hand, complementary data line D constituting memory array MARY
O.DO to Dn-Dn are coupled to the power supply voltage Vcc of the circuit through corresponding MOSFETs Q25, Q26 to Q27, and Q2B on one side. These MOS
The gate and drain of the FET are commonly coupled to form a diode, and complementary data lines Do-DO to D
Functions as a load MOSFET for n-Dn.

Complementary data lines DO and D forming memory array MARY
O~Dn-Dn is called Karamsu (7) in that region.
Switch MOSFET Q29/Q3 corresponding to C8W
0 to Q31-Q32, respectively. The other of these switch MOSFETs is commonly coupled to a non-inverting signal line CD and an inverting signal line CD of complementary common data lines, respectively. The gates of each pair of switch MOSFETs are commonly coupled, and a corresponding data line selection signal YO to Yn is supplied from a Y address decoder YDCR.

As a result, each switch MOS of column switch C8W
The FETs are turned on when the corresponding data line selection signals YO to Yn are alternatively set to a high level, and the corresponding complementary data lines DO/Cloth to Dn-101 and the complementary common data line CD-7 are connected to each other. Selectively connect.

The Y address decoder YDCR is supplied with j+1 bits of complementary internal address signals ayO to ayj from a Y address buffer YADB, which will be described later. Further, the above-mentioned timing signal φce is supplied from the timing generation circuit TO.

The Y address decoder YDCR receives the timing signal φ
By setting ce to a high level, the device is selectively put into an operating state. In this operating state, the Y address decoder Y
The DCR decodes the complementary internal address signals ayQ to ayj and selectively selects the corresponding data line selection signals YO to Yn at a high level.

Y address buffer YADB receives address input terminal AY from a memory control unit (not shown) of the logic integrated circuit.
Y address signal AYO~ supplied via O~AYj
Incorporate and retain AYJ. Also, based on these Y address signals AYO-AYj, the complementary internal address signals ayO-ayj are formed and supplied to the Y-address decoder YDCR.

The complementary common data line CD-CD is coupled to the input terminal of the read amplifier RA and the output terminal of the write amplifier WA, although this is not particularly limited. The output terminal of the read amplifier RA is further coupled to the input terminal of the data output buffer DOB. In addition, the input terminal of the light amplifier WA is further connected to the data driver DIB.
is coupled to the output terminal of The read amplifier RA, write amplifier WA, and data output buffer DOB receive a timing signal φra from the timing generation circuit TG.

φwe and φoe are respectively supplied. Of these, timing signals φra and φOe are used for static type RA.
When M is selected in the read operation mode, it is selectively set to a high level at a predetermined timing. Further, the timing signal φwe is selectively set to a high level at a predetermined timing when the static RAM is brought into a selected state in a write operation mode.

The read amplifier RA is selectively brought into operation when the timing signal φra is set to a high level. In this operating state, read amplifier RA amplifies the read signal output from selected memory cell MC of memory array MARY via complementary common data line CD-CD, and transmits it to data output buffer DOB.

The data output buffer DOB receives the above-mentioned timing signal φo.
By setting e to a high level, it is selectively put into an operating state. In this operating state, the data output buffer DO
B sends out the read signal transmitted from the read amplifier RA to a data bus (not shown) of the logic integrated circuit via the data output terminal DO. When the timing signal φOe is set to a low level, the output of the data output buffer DOB is set to a high impedance state.

The data input buffer DIB converts write data supplied via a data input terminal DI from a data bus (not shown) of the logic integrated circuit into a complementary internal write signal, and transmits the signal to the write amplifier WA.

, these complementary write signals, that is, the non-inverted internal write signal wd and the inverted internal write signal wd, are also supplied to the data set circuit DSC, as described above.

The write amplifier WA is selectively brought into operation when the timing signal φWe is set to a high level. In this operating state, the write amplifier WA forms a complementary write current in accordance with the complementary internal write signal transmitted from the data input buffer sofa DIB, and writes a selected signal in the memory array MARY via the complementary common data line CD--. Supplied to memory cell MC. Timing signal φWe
When is set to a low level, the output of write amplifier WA is set to a high impedance state.

The timing generation circuit TG receives input terminals C3, WE and D from a memory control unit (not shown) of the logic integrated circuit.
The various timing signals mentioned above are formed based on the chip selection signal C8, write enable signal WE, and data set mode signal DS supplied via S, and are supplied to each circuit.

In the static RAM of this embodiment, a test operation for confirming the information retention characteristics of the memory cell MC is performed as follows. That is, although the static type RAM is not particularly limited, it is first repeatedly brought into a selected state in a normal write operation mode, and storage data of, for example, logic "0" is written into all memory cells MC of the memory array MARY. At this time, the data write mode signal DS is set to a high level, and write data of logic "O" is supplied from a data bus (not shown) via the data input terminal DI.

When the write operation for all memory cells MC of the memory array MARY is completed, the static RAM is repeatedly brought into the selected state in the normal read operation mode,
It is confirmed that storage data of logic "O" is normally written into all memory cells MC. At this time, the read data of logic "0" read from each memory cell MC is sent out via the data output terminal DO.

Next, the static RAM is put into the data set mode, and all memory cells MC of the memory array MARY are
The stored data is inverted to logic "1". At this time,
The data set mode signal DS is set to a low level, and write data of logic "1" is supplied to the data input terminal DI.

In static RAM data set mode,
The data set circuit DSC includes a timing generation circuit TG.
Inverted timing signals φsa and φsb are supplied from
Also, a non-inverted internal write signal wd and an inverted internal write signal wd are supplied from the data input cover sofa D1B.

As a result, as described above, the stored data in all memory cells MC of memory array MARY are simultaneously rewritten to logic "1" in a short time.

When the inversion of the stored data in the data set mode is completed, the static RAM is repeatedly selected again in the normal read operation mode, and it is confirmed that the stored data in all memory cells MC has been inverted to logic "1". .

At this time, when read data of logic "0" is output from any memory cell MC, that memory cell MC
The load MOSFET QI is determined to have a fault such as a disconnection on its drain side, for example.

Furthermore, the static RAM is again put into the data center mode, and the stored data in all memory cells MC of the memory array MARY is inverted to logic ""O". At this time, the data set mode signal DS is similarly set to a low level. , and write data of logic "0" is supplied to the data input terminal DI.

When the second data cent mode ends, the static RAM is repeatedly brought into the selected state again in the normal read operation mode, and it is confirmed that the stored data in all memory cells MC has been inverted to logic "0". At this time, when read data of logic "1" is output from any memory cell MC, the load MOS of that memory cell MC
FETQ2 is determined to have a fault such as a disconnection on its drain side, for example.

As described above, the static RAM of this embodiment is
The basic configuration is a memory array MARY in which CMOS static type memory cells MC are arranged in a grid pattern. Each memory cell MC has a P-channel type load MOSFET and an N-channel type drive MOSFET connected in series.
It includes a flip-flop circuit formed by cross-connecting two CMOS inverter circuits each composed of SFETs. Among these, O3 between P channels that constitutes one inverter circuit.
The source of the FET is connected to the corresponding power supply voltage supply line VAO~V
The sources of the P-channel inter-channel O3FETs constituting the other inverter circuit are commonly coupled to the corresponding power supply voltage supply lines VBO to VBm, respectively. Furthermore, the sources of the N-channel MOSFETs constituting both inverter circuits are connected to the corresponding ground potential supply line GO.
- Gm, respectively. Power supply voltage supply line VA
O to V A m and V B O to V B m include, when the static RAM is in the normal operation mode,
Both are supplied with the circuit power supply voltage Vcc. Further, when the static RAM is placed in a predetermined test mode, that is, data set mode, the inverted timing signal φsa,
According to φsb and complementary internal write signals wd-wd, the ground potential of the circuit is supplied to one of them. The ground potential supply line G O-G m normally has MOSFETs Q35 to Q36 that have a relatively large conductance and MOSFETs Q33 to Q3 that have a relatively small conductance.
4, the ground potential of the circuit is supplied. Further, when the above-mentioned inversion timing signals ψ5abt, u·ψsb and 10 are set, the ground potential of the circuit is supplied only through MOSFETs Q33 to Q34 (7) having relatively small conductance. For these reasons, in the static RAM of this embodiment, the memory array MARY
It is possible to forcibly set the stored data of all memory cells MC to logic "0" or logic "1" according to the write data. Also, by performing this data set mode while inverting the stored data, the memory Negative EI of cell MC
It can be determined whether MOS FETQl and Q2 are normal. As a result, it is possible to shorten the test time for static RAM and promote cost reduction of logic integrated circuits and the like that incorporate static RAM. Needless to say, these test operations do not need to be performed with the logic integrated circuit's power supply voltage low (or its surrounding temperature raised), and the data cent mode described above is not required for static RAM. It can also be used for the initial set.

As shown in the above embodiment, when the present invention is applied to a static RAM built into a logic integrated circuit such as a microcomputer, the following effects can be obtained. That is, (1) two power supply voltage supply lines are provided corresponding to the two sets of inverter circuits constituting a static memory cell, and the power supply voltage of the circuit is normally supplied to these power supply voltage supply lines to receive a predetermined control signal. By providing a data center circuit that selectively supplies the circuit's ground potential to one of the voltage supply lines (a), data held in memory cells can be reversed arbitrarily and in a short time. Effects can be obtained.

(2) By determining whether it is possible to invert the data held in a memory cell according to item (1) above, failures such as disconnection that occur in the load MOSFET of a static memory cell can be detected using the power supply voltage and ambient temperature. This has the effect of being able to detect it in a short time without changing it.

(3) The above items (11 and (2)) provide the effect of shortening the test time regarding the information retention characteristics of a memory cell of a static RAM.

(4) The above-mentioned items +11 to (3) provide the effect of shortening the testing time of logic integrated circuits such as microcomputers including static type RAM, etc., and reducing the cost thereof.

(5) By the above (11) and (2), it is possible to obtain the effect that the stored data held in a memory cell such as a static RAM can be initialized to logic "O" or logic "1" in a short time. .

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment of FIG. 1, each memory cell MC has a load MOSFETQ
In place of I and Q2, there is a high resistance load made of polysilicon or the like, or an N-channel M in the form of a diode.
It is also possible to use an OSFETi load. Further, MOSFETs Q33 to Q34 of the data set circuit DSC may not be provided, and their gates may be coupled to the power supply voltage Vcc of the circuit.

Power supply voltage supply lines V AO to V A m and VBO-V
Inverter circuits N1 to N4 and NOR gate circuits NO01 to N0G4 of data center circuit DSC coupled to Bm
etc. can be replaced with other logic gate circuits on the condition that the logic is the same. Further, the levels of the inverted timing signals φsa and 7T and the complementary internal write signals wd-wd can be arbitrarily combined. The power supply voltage given to static RAM is
It is also possible to set the power supply voltage Vcc of the circuit to a ground potential and set the ground potential of the circuit to a negative power supply voltage.
The polarity of the power supply voltage may be reversed by replacing the FET and the N-channel MOSFET.

The memory array MARY may be composed of a plurality of memory mantles, and the complementary data line DO-
Load MOSFET Q25 provided at 5 lower ~ Dn-5 T
・Q26 to Q27 and Q28 are, for example, timing signals φ
It may also be selectively turned on by ce or the like.

Furthermore, various embodiments can be adopted, such as the circuit block configuration of the static RAM shown in FIG. 1 and the combination of address signals and control signals.

The above description will mainly focus on the static RAM built into logic integrated circuits such as microcomputers, which is the field of application for which the invention was made by the present inventor.
Although the present invention has been described for a case where it is applicable to a static RAM, it is not limited thereto. The present invention is widely applicable to at least semiconductor memory devices whose memory arrays are constituted by static memory cells including load means, and digital devices incorporating such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, 2 cells constituting a static memory cell
Two power supply voltage supply lines are provided corresponding to each set of inverter circuits, and the power supply voltage of the circuit is normally supplied to these power supply voltage supply lines, and when a predetermined control signal is enabled, either one of the power supply voltages is supplied. By providing a data set circuit that selectively supplies the ground potential of the circuit to the line, the data held in the memory cells can be inverted easily and in a short time. In addition, by determining whether the data held in a memory cell can be inverted, failures such as disconnection that occur in the load MO3FE'r of a static memory cell can be avoided without changing the power supply voltage or ambient temperature. Can be detected in a short time. As a result, it is possible to shorten the test time for logic integrated circuits such as microcomputers including static RAM, etc., and to reduce the cost thereof.

[Brief explanation of the drawing]

Figure 1 shows a static type RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an example of a conventional static RAM memory array. MARY...Memory array, MC...Static type memory cell, DSC...Data center circuit, C3W
...Column switch, XDCR...X address decoder, YDCR...Y address decoder, XADB.
...X address buffer, YADB...Y address buffer, RA...read amplifier, WA...write amplifier, DOB...data output cover sofa, DIB...
...Data input cover sofa, TG...timing generation circuit. Q1 to Q4...P channel MOSFET. Q21~Q40...N channel MOS FET,
N1-N4...CMOS inverter circuit, N. 01~N0G4...Nor gate circuit, Cg...Gate capacitance.

Claims (1)

[Claims] 1. Load means and drive MOSFE provided in series between the first power supply voltage supply line and the second power supply voltage supply line
A first inverter circuit consisting of T and a second inverter circuit consisting of a drive MOSFET and a load means provided in series between the first power supply voltage supply line and the third power supply voltage supply line are cross-connected. A memory array in which memory cells including flip-flop circuits are arranged in a lattice pattern, and a first power supply voltage is normally supplied to the first power supply voltage supply line, and the second and third power supply voltage supply lines are normally connected to the first power supply voltage supply line. and a data set circuit that supplies a second power supply voltage to the second power supply voltage supply line and selectively supplies the first power supply voltage to the second or third power supply voltage supply line according to a predetermined control signal. Semiconductor storage device. 2. The data set circuit selectively supplies the first power supply voltage to the second or third power supply voltage supply line in accordance with a write data signal supplied from the outside. The semiconductor memory device according to item 1. 3. Between the first power supply voltage supply line and the first power supply voltage, there is a first MOSFET that has a relatively small conductance and is kept in a steady on state, and a first MOSFET that has a relatively large conductance and is normally in the on state. a second M that is turned on and selectively turned off according to the predetermined control signal;
3. The semiconductor memory device according to claim 1, wherein the OSFET is provided in parallel. 4. The memory cell is a CMOS static type memory cell having a P-channel MOSFET as the load means and an N-channel MOSFET as the drive MOSFET. 3. The semiconductor storage device according to item 3. 5. The semiconductor memory device according to claim 1, 2, 3, or 4, wherein the semiconductor memory device is built in a logic integrated circuit.