KR890010720A - Semiconductor memory having a circuit for testing flip-flop characteristics and a single-chip microcomputer comprising the same - Google Patents

Abstract

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Description

Half-memory device having circuit for characterizing flip-flops and single-chip microcomputer comprising the same

Since this is an open matter, no full text was included.

1 is a circuit diagram of a static RAM showing a state in which an output of a data set circuit DSC to which the present invention is applied is supplied to a load MOSFET of a memory cell.

3 is a plan view of a logic integrated circuit such as a single chip microcomputer including a static RAM to which the present invention is applied,

5 is a timing chart of the normal write operation mode and the normal read operation mode of the static RAM to which the present invention is applied.

Claims (15)

A first load element comprising a first, second, and third line (VAO, VBO, GO), a first load element and a first drive element connected in series with the first line and the third line; An inverter (Q1, Q21), a second load element and a second drive element connected in series with the second line and the third carrier, each coupled to an output node and an input node of the first inverter. A second inverter (Q2, Q22) having a connected input node and an output node, one line selected from among the first and second lines in response to a predetermined control signal, coupled to the first and second lines And a voltage supply means for supplying a potential to be supplied to said third line. The method of claim 1, wherein the first and second driving elements Q21 and Q22 are formed of a MOSFET having a drain and a gate cross-coupled to each other and a source coupled to the third line GO. A semiconductor memory device, characterized in that. The semiconductor memory device according to claim 2, wherein the MOSFET is made of an N channel MOSFET. 4. The gate of claim 3 wherein the first and second load elements are coupled to a source-drain path coupled between the first line and the drain of the corresponding MOSFET and a gate coupled to the gate of the corresponding MOSFET. One P-channel MOSFET Q1 having a source-drain path coupled between the second line and the drain of the corresponding MOSFET and another P-channel MOSFET Q2 having a gate coupled to the gate of the corresponding MOSFET. A semiconductor memory device, characterized in that consisting of. 4. The semiconductor memory device according to claim 3, wherein the first and second load elements (Q1, Q2) are made of a resistance element made of polycrystalline silicon. The semiconductor memory device according to claim 1, wherein the memory device is formed in a semiconductor substrate of one chip together with a central processing unit (CPU). Has first, second and third terminals and accumulates information therein, and is coupled between a gate and a drain cross-coupled with each other and a source coupled to the first terminal, between the second terminal and one drain A storage means (MC) consisting of a pair of MOSFETs having a first load element coupled, a second load element coupled between the third terminal and the other drain, coupled to the first terminal and First means for supplying a first operating voltage of the semiconductor memory device to the first terminal, the semiconductor memory coupled to the second and third terminals and different from the first operating voltage to the second and third terminals; A second means for supplying a second operating voltage of the device, the second means further comprising: a third for supplying the first operating voltage to the second terminal in response to a first control signal; The first copper terminal to the third terminal in response to a second control signal and And a fourth means for supplying a working voltage, wherein said third and fourth means comprise voltage supply means selectively operated by said first and second control signals. 8. The semiconductor memory device according to claim 7, wherein the pair of MOSFETs comprise N channel MOSFETs. 9. The semiconductor memory device according to claim 8, wherein the first and second load elements are made of P-channel MOSFETs. A plurality of memory cells MC each consisting of first, second and third terminals and flip-flops for storing information therein, the gates and drains cross-coupled to each other and coupled to the first terminals A pair of MOSFETs, each having a source, a first load element coupled between the second terminal and one drain, and a second load element coupled between the third terminal and the other drain, each A plurality of word lines and a plurality of complementary data line pairs coupled to a plurality of memory cells so that the memory cells are coupled to a word line and a pair of complementary data lines, coupled to the first terminal and attached to the first terminal. First means for supplying an operating voltage of one and a second operating voltage of the semiconductor memory device coupled to the second and third terminals and different from the first operating voltage to the second and third terminals; As a second means of supplying The second means is further adapted to supply the first operating voltage to the second terminal in response to a first control signal and the third in response to a second control signal. A fourth means for supplying said first operating voltage to a terminal of said third means, said third and fourth means comprising voltage supply means selectively operated by said first and second control signals. Semiconductor memory device. The semiconductor memory device according to claim 10, wherein the pair of MOSFETs comprise N channel MOSFETs. 12. The semiconductor memory device according to claim 11, wherein the first and second load elements are made of P-channel MOSFETs. 1. A single-chip microcomputer comprising a central processing unit, which stores information therein, is connected to the central processing unit, and has gates and drains cross-coupled to each other at first, second and third terminals, and the first. A pair of sources having a source coupled to a terminal of the first load element coupled to the second terminal and one drain high, and a second load element coupled between the third terminal and the other drain. Storage means comprising a MOSFET, first means coupled to the first terminal, the first means for supplying a first operating voltage of a semiconductor memory device to the first terminal, and coupled to the second and third terminals; And second means for supplying a third terminal with a second operating voltage of the semiconductor memory device, the second operating voltage being different from the first operating voltage, the second means being further configured in response to the first control signal. The first copper to a second terminal A third means for supplying a voltage and a fourth means for supplying the first operating voltage to the third terminal in response to a second control signal, the third and fourth means Is a single chip microcomputer comprising voltage supply means selectively operated by said first and second control signals. 14. The single chip microcomputer of claim 13, wherein the pair of MOSFETs comprise N channel MOSFETs. 15. The single chip microcomputer according to claim 14, wherein the first and second load elements are P channel MOSFETs. ※ Note: The disclosure is based on the initial application.