JPH01175347U - - Google Patents
Info
- Publication number
- JPH01175347U JPH01175347U JP7312888U JP7312888U JPH01175347U JP H01175347 U JPH01175347 U JP H01175347U JP 7312888 U JP7312888 U JP 7312888U JP 7312888 U JP7312888 U JP 7312888U JP H01175347 U JPH01175347 U JP H01175347U
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- information processing
- master system
- processing
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Multi Processors (AREA)
Description
第１図は本考案に係る情報処理装置のシステム
構成図、第２図は第１図に示した情報処理装置の
処理流れを示すフローチヤート、第３図は１つの
単一処理系システムだけが設けられている場合の
データの処理の仕方を説明するための図、第４図
は複数の単一処理系システムが設けられている場
合のデータの分散処理の仕方を説明するための図
、第５図は従来の情報処理装置の概略構成図であ
る。
１……情報処理装置、２……システム入力キユ
ー、３ａ乃至３ｍ……単一処理系システム、４…
…構成情報記憶部、５……データ分散プロシージ
ヤ、６ａ乃至６ｍ……入力キユー、７ａ乃至７ｍ
……入力プロシージヤ、８ａ乃至８ｍ……処理部
。
Fig. 1 is a system configuration diagram of the information processing device according to the present invention, Fig. 2 is a flowchart showing the processing flow of the information processing device shown in Fig. 1, and Fig. 3 is a system configuration diagram of the information processing device according to the present invention. Figure 4 is a diagram for explaining how to process data when a plurality of single processing systems are installed; FIG. 5 is a schematic configuration diagram of a conventional information processing device. 1... Information processing device, 2... System input queue, 3a to 3m... Single processing system, 4...
...Configuration information storage unit, 5...Data distribution procedure, 6a to 6m...Input queue, 7a to 7m
. . . Input procedure, 8a to 8m . . . Processing unit.
Claims (1)
報処理装置において、該情報処理装置は、マスタ
システムとして動作する１つの処理系システムと
、任意の個数に増減可能であつて前記マスタシス
テムに対してスレーブシステムとして動作する他
の処理系システムとを備え、前記マスタシステム
は、時系列的に発生するデータに対するマスタシ
ステムの処理能力に応じてデータを所定の処理系
システムに分散させる手段を備えていることを特
徴とする情報処理装置。 In an information processing device that sequentially processes data generated in a time-series manner, the information processing device has one processing system that operates as a master system, and a processing system that can be increased or decreased to an arbitrary number for the master system. and another processing system operating as a slave system, and the master system is provided with means for distributing data to predetermined processing systems according to the processing ability of the master system for data generated in time series. An information processing device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7312888U JPH01175347U (en) | 1988-06-01 | 1988-06-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7312888U JPH01175347U (en) | 1988-06-01 | 1988-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01175347U true JPH01175347U (en) | 1989-12-13 |
Family
ID=31298274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7312888U Pending JPH01175347U (en) | 1988-06-01 | 1988-06-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01175347U (en) |
-
1988
- 1988-06-01 JP JP7312888U patent/JPH01175347U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01175347U (en) | ||
| JPH0218146U (en) | ||
| JPH0363253U (en) | ||
| JP2590872B2 (en) | Task scheduling method | |
| JPH01180407U (en) | ||
| JPH01160546U (en) | ||
| JPH01116849U (en) | ||
| JPS6138177U (en) | Production line tracking device | |
| JPS6316351U (en) | ||
| JPH0444790U (en) | ||
| JPS59159057U (en) | Slave station status monitoring device | |
| KRIESEL et al. | Synthesis and realization of multidimensional controllers | |
| JPS62169851U (en) | ||
| JPH0273245U (en) | ||
| JPH0462599U (en) | ||
| JPS61196348U (en) | ||
| JPH0263115U (en) | ||
| JPH0321138U (en) | ||
| JPS6427749U (en) | ||
| JPS5881657U (en) | Abnormality detection device for computer systems | |
| JPS6491273A (en) | Memory access control system | |
| JPS60123051U (en) | shared memory controller | |
| JPS5832543U (en) | shared storage | |
| JPH03127907U (en) | ||
| JPH01162474U (en) |