JPH01175335A - Driver circuit - Google Patents
Driver circuitInfo
- Publication number
- JPH01175335A JPH01175335A JP33314887A JP33314887A JPH01175335A JP H01175335 A JPH01175335 A JP H01175335A JP 33314887 A JP33314887 A JP 33314887A JP 33314887 A JP33314887 A JP 33314887A JP H01175335 A JPH01175335 A JP H01175335A
- Authority
- JP
- Japan
- Prior art keywords
- mos
- power source
- power supply
- circuit
- driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 230000000295 complement effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000004804 winding Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- Electronic Switches (AREA)
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はパルスドライバに関し、特に共通回線に複数の
ドライバを接続しユーザが任意のドライバの電源をオフ
しうる伝送形態に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse driver, and particularly to a transmission form in which a plurality of drivers are connected to a common line and a user can turn off the power of any driver.
従来、この種のドライバはトランスの１次側をスイッチ
ング回路で駆動し、回線から侵入するサージから回路を
保護する目的でダイオードブリッジをトランス１次側と
電源端子間に挿入していた。Conventionally, in this type of driver, the primary side of the transformer was driven by a switching circuit, and a diode bridge was inserted between the primary side of the transformer and the power terminal in order to protect the circuit from surges entering from the line.
さらに回路に一般的に用いられている電源パスコンで電
源電圧の変動を抑圧していた。Furthermore, power supply bypass capacitors commonly used in circuits suppressed fluctuations in power supply voltage.
上述した従来のドライバは電源オフ時に電源パスコンが
放電し終え、ダイオードブリッジを交流的に短絡する構
成であるため、ドライバ出力インピーダンスが低下する
欠点がある。なぜならば、共通の１対回線に複数のドラ
イバを接続し任意の１台をＭ動させて使用する形態にお
いて使用していないドライバの電源をオフした場合、上
記理由によりオフしたドライバの出力インピーダンスが
低下し駆動しようとするドライバの負荷が重くなり回線
への送信パルスレベルが低下し受信できなくなるためで
ある。The above-described conventional driver is configured to short-circuit the diode bridge in an alternating current manner after the power bypass capacitor finishes discharging when the power is turned off, and therefore has the disadvantage that the driver output impedance decreases. This is because when multiple drivers are connected to a common pair of lines and any one of them is operated in M mode, when the power is turned off to a driver that is not being used, the output impedance of the driver that is turned off will change due to the above reason. This is because the load on the driver that is trying to drive becomes heavier and the transmission pulse level to the line decreases, making it impossible to receive data.
本発明の目的は前記問題点を解消したドライバ回路を提
供することにある。An object of the present invention is to provide a driver circuit that eliminates the above-mentioned problems.
本発明はＭＯＳのドレインにキャパシタを接続し、該Ｍ
ＯＳの相補型ＭＯＳのドレインに抵抗を接続し、１対の
電源端子間に順方向に並列に挿入して、該相補型ＭＯＳ
のドレインを諌ＭＯＳのゲートに、該相補型ＭＯＳのゲ
ートを、該電源端子間に挿入された直列抵抗の接続点に
それぞれ接続し、さらに、回線に接続されるトランスの
１次側をダイオードブリッジと制御可能なスイッチング
ブリッジとの並列回路を経由して前記電源端子間に接続
したことを特徴とするドライバ回路である。The present invention connects a capacitor to the drain of MOS, and
A resistor is connected to the drain of the complementary MOS of the OS, and inserted in parallel between a pair of power supply terminals in the forward direction.
The drain of the MOS is connected to the gate of the MOS, the gate of the complementary MOS is connected to the connection point of the series resistor inserted between the power supply terminals, and the primary side of the transformer connected to the line is connected to a diode bridge. The driver circuit is characterized in that the driver circuit is connected between the power supply terminals via a parallel circuit including a controllable switching bridge and a controllable switching bridge.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
（実施例１） 第１図は本発明の実施例１を示す回路図である。(Example 1) FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
Ｐ ＭＯＳ ＭＰとキャパシタＣは電源パスコン回路を
構成し、抵抗Ｒ１，Ｒ２，Ｒ３とＮ ＭＯＳ ＭＮとか
らなる回路はバイアス回路を構成する。トランスの１次
側はスイッチング制御可能なスイッチングブリッジＳｌ
。PMOS MP and capacitor C constitute a power supply bypass capacitor circuit, and a circuit consisting of resistors R1, R2, R3 and NMOS MN constitutes a bias circuit. The primary side of the transformer is a switching bridge Sl that can control switching.
.
Ｓ２．Ｓ３．Ｓ４とダイオードブリッジＤｉ、Ｄ２．Ｄ
３．Ｄ４ を経由して正電源端子ＶＯＯと負電源端子Ｖ
Ｓ２間に接続されている。S2. S3. S4 and diode bridges Di, D2. D
3. Positive power supply terminal VOO and negative power supply terminal V via D4
It is connected between S2.
まず、正パルスを送信する場合について説明する。スイ
ッチングブリッジのスイッチング回路ＳＬ。First, the case of transmitting a positive pulse will be explained. Switching circuit SL of switching bridge.
Ｓ４を制御端子Ｃ１，Ｃ４を駆動してオンとしドライブ
電流を、正電源端子ＶＯＯ→スイッチング回路Ｓ１→ト
ランスＴ１次巻線→スイッチング回路Ｓ４→負電源端子
ｖｓｓのルートで流し回線をＩＦｊＡ動する。S4 is turned on by driving control terminals C1 and C4, and a drive current is passed along the route of positive power supply terminal VOO→switching circuit S1→transformer T primary winding→switching circuit S4→negative power supply terminal vss to operate the line IFjA.
負パルスの場合は制御端子Ｃ２，Ｃ３を駆動し、ドライ
ブ電流を、正電源端子ｖＤＤ→スイッチング回路Ｓ３→
トランスＴ１７！Ａ巻線→スイッチング回路Ｓ２→負電
源端子ＶＳＳのルートで流し回線を駆動する。In the case of a negative pulse, control terminals C2 and C3 are driven, and the drive current is transferred from the positive power supply terminal vDD→switching circuit S3→
Trance T17! The flow line is driven by the route of A winding → switching circuit S2 → negative power supply terminal VSS.
次に電源パスコン回路について説明する。Ｎ ＭＯＳ
ＭＮはゲートが分圧高抵抗Ｒ１，Ｒ２により適当にバイ
アスされオン状態となっておリドレイン電流が流れ抵抗
Ｒ３の電圧降下によりＰ ＭＯＳ ＭＰのゲートをほぼ
負電源′電圧に近いローレベルにバイアスしＰＭＯＳＭ
Ｐを非飽和のオン状態とする。Next, the power bypass capacitor circuit will be explained. NMOS
The gate of MN is suitably biased by voltage dividing high resistors R1 and R2 and turned on, and the drain current flows and due to the voltage drop across resistor R3, the gate of PMOS MP is biased to a low level close to the negative power supply voltage. PMOSM
Let P be in an unsaturated on state.
従ってキャパシタＣはＰ ＭＯＳ ＭＰの小さな等価オ
ン抵抗経由で電源端子間に接続されることとなり電源パ
スコンとして動作する。Ｐ ＭＯＳ ＭＰのドレイン電
位はキャパシタＣへの充電電流でほぼ正電源電圧に近く
なり双方向に電流が流れうる状態となる。Therefore, the capacitor C is connected between the power supply terminals via the small equivalent on-resistance of the PMOS MP, and operates as a power supply bypass capacitor. The drain potential of the PMOS MP becomes close to the positive power supply voltage due to the charging current to the capacitor C, so that current can flow in both directions.
さてユーザが電源スィッチを開いて電源をオフした場合
は次のようになる。Now, if the user opens the power switch to turn off the power, the following happens.
Ｎ ＭＯＳ ＭＮのゲートにもはやバイアスは与えられ
ずＮ ＭＯＳ ＭＮはオフとなり、抵抗Ｒ３の電圧降下
はゼロとなる。従ってＰ ）１０５ ＭＰＩまゲート電
位がソース電位と同電位となり閾値以下となってオフと
なる。The gate of N MOS MN is no longer biased and N MOS MN is turned off, and the voltage drop across resistor R3 becomes zero. Therefore, the gate potential of P)105 MPI becomes the same potential as the source potential, becomes lower than the threshold value, and is turned off.
この状態で同じ回線に接続されている他のドライバから
送信されたパルスがトランスＴ経出で入力したとする。Assume that in this state, a pulse transmitted from another driver connected to the same line is input at the transformer T output.
スイッチングブリッジ（Ｓｌ 、Ｓ２．Ｓ３．Ｓ４）は
電源オフのため遮断状態でありダイオードブリッジは電
源側が高抵抗（旧、Ｒ２）のため微小なリーク電流しか
流れずＮ ＭＯＳ ＭＮをオンするに至らず、出力イン
ピーダンスの低下を起こさない。The switching bridges (Sl, S2.S3.S4) are in a cutoff state because the power is off, and the diode bridge has a high resistance on the power supply side (old, R2), so only a small leakage current flows and is not enough to turn on NMOS MN. , no drop in output impedance occurs.
もし仮に電源パスコン回路として単にキャパシタＣのみ
が電源端子間に接続されているならば、回線から正パル
スが入力したときトランスＴ１次巻線→ダイオードＤ２
→キャパシタＣ→ダイオードＤ４→トランスＴ１次巻線
のルートか、又は負パルス入力時にトランスＴ１次巻線
→ダイオードＤ１→キャパシタＣ→ダイオードＤ３→ト
ランスＴ１次巻線のルートにかなり大きな電流が流れそ
の結果トランス２次側（Ａ、Ｂ端子）からみた出力イン
ピーダンスが低下するという問題が発生するが、本発明
ではそのようなことはない。If only capacitor C is connected between the power supply terminals as a power bypass capacitor circuit, when a positive pulse is input from the line, transformer T primary winding → diode D2
→ Capacitor C → Diode D4 → The route of the transformer T primary winding, or when a negative pulse is input, a fairly large current flows through the transformer T primary winding → Diode D1 → Capacitor C → Diode D3 → The transformer T primary winding route. As a result, a problem arises in that the output impedance seen from the transformer secondary side (terminals A and B) decreases, but this does not occur in the present invention.
第４図は本発明に係るドライバ回路ＤＲＶ １〜ＤＲＶ
ｎを用いたシステム図である。Ａｔ、 Ｂｌ・・・Ａｎ
、 Ｂｎはドライバ出力端子、ＳＷＩ、ＳＷＩ’・・・
ＳＷ口、Ｓｕｎ’は電源スィッチ、Ｅｌ−Ｅｎは電源、
Ｒは終端抵抗、ＲＣＶはレシーバ回路である。FIG. 4 shows driver circuits DRV 1 to DRV according to the present invention.
It is a system diagram using n. At, Bl...An
, Bn is the driver output terminal, SWI, SWI'...
SW port, Sun' is the power switch, El-En is the power supply,
R is a terminating resistor, and RCV is a receiver circuit.
（実施例２） 第２図は本発明の実施例２を示す回路図である。(Example 2) FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
正電源端子ＶＤＤにキャパシタＣとバイアス用ＰＭＯＳ
訂」が接続され、負電源端子ＶＳＳに低等価オン抵抗を
有するＮ ＭＯＳ ＭＮとドレイン抵抗Ｒ３が接続され
ており、回路動作は第１図の相補的な動作を行い同一の
機能を有する。簡単に説明すれば、電源オン時Ｐ ＭＯ
Ｓ ＭＰはゲートを適当にバイアスされオン状態となっ
ており抵抗Ｒ３による電圧降下のため、Ｎ ＭＯＳ Ｍ
Ｎは非飽和状態で双方向にオンしてキャパシタＣを電源
端子間（Ｖｏｏ＋ Ｖｓｓ）に低等価オン抵抗で接続し
電源パスコン回路として動作する。Capacitor C and bias PMOS on positive power supply terminal VDD
An N MOS MN having a low equivalent on-resistance and a drain resistor R3 are connected to the negative power supply terminal VSS, and the circuit operation is complementary to that shown in FIG. 1 and has the same function. To explain briefly, when the power is turned on, P MO
SMP has its gate appropriately biased and is in the on state, and due to the voltage drop due to resistor R3, NMOSM
N is bidirectionally turned on in a non-saturated state, and the capacitor C is connected between the power supply terminals (Voo+Vss) with a low equivalent on-resistance, thereby operating as a power supply bypass capacitor circuit.
第３図はスイッチングブリッジＳＬ、Ｓ２．Ｓ３．Ｓ４
のスイッチング回路を示す一実施例である。スイッチン
グ回路Ｓ１とＳ３、Ｓ２とＳ４は同一回路構成である。FIG. 3 shows switching bridges SL, S2. S3. S4
1 is an example of a switching circuit shown in FIG. The switching circuits S1 and S3, and S2 and S4 have the same circuit configuration.
トランジスタＱ１がスイッチング回路５Ｌ（Ｓ３）に、
トランジスタＱ２がスイッチング回路５４（Ｓ２）に相
当し同時にオン、オフする。トランジスタＱｌ、 Ｑ２
のエミッタがトランスＴの１次巻線に接続される。Transistor Q1 is connected to switching circuit 5L (S3),
Transistor Q2 corresponds to switching circuit 54 (S2) and is turned on and off at the same time. Transistors Ql, Q2
The emitter of T is connected to the primary winding of the transformer T.
以上説明したように本発明はドライバの電源パスコン回
路を電源オフ時に切離しダイオードブリッジによるドラ
イバ出力インピーダンスの低下を防止する効果があり、
従って共通回線に複数のドライバを接続する形態で、使
用していない電源オフのドライバを回線に接続したまま
で他のドライバを使用できる効果がある。As explained above, the present invention has the effect of disconnecting the power supply bypass capacitor circuit of the driver when the power is turned off, thereby preventing a decrease in the driver output impedance due to the diode bridge.
Therefore, in a configuration in which a plurality of drivers are connected to a common line, there is an effect that other drivers can be used while an unused driver whose power is turned off is connected to the line.
第１図は本発明の実施例１を示す回路図、第２図は本発
明の実施例２を示す回路図、第３図は制御可能なスイッ
チングブリッジの半分を示すスイッチング回路ブロック
図、第４図は本発明の一実施例を示すシステム図である
。
ＶＯＯ・・・正電源端子 ＶＳＳ・・・負電源端子
Ｒ１，Ｒ２，Ｒ３・・・抵抗 Ｒ・・・終端抵抗Ｍ
Ｐ・・・Ｐ ＭＯＳ ＭＮ・・・Ｎ ＭＯ
ＳＣ・・・キャパシタ ＣＩ、Ｃ２，Ｃ３，Ｃ４・・
・制御入力端子Ｓｌ、Ｓ２．Ｓ３．Ｓ４・・・スイッチ
ングブリッジを構成するスイッチング回路Ｔ・・・トラ
ンス
Ｄｉ、Ｄ２．Ｄ３．Ｄ４・・・ダイオードブリッジを構
成するダイオードＱｌ 、Ｑ２・・・トランジスタ
Ａ、Ｂ、Ａｌ、Ｂｌ、”’、Ａｎ、Ｂｎ”’ドライバ出
力端子Ｓす１．ＳＷＩ’、−＋Ｓｕｎ、５ｌｉｌｎ’−
電源スイッチＲＣＶ・・・レシーバ ＤＲＶＩ、
・・・、ＤＲＶｎ・・・ドライバＥｌ、・・・、Ｅｎ・
・・電源
Ｃへヤパシタ
ＭＮ：ＮＨＯ２
ＭＰ：ＰＭＯ８
ＲＪ、 Ｒ２，尺３：Ｊ麟九
第１図1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, FIG. 3 is a switching circuit block diagram showing half of a controllable switching bridge, and FIG. The figure is a system diagram showing one embodiment of the present invention. VOO...Positive power supply terminal VSS...Negative power supply terminal R1, R2, R3...Resistor R...Terminal resistor M
P...P MOS MN...N MO
SC...Capacitor CI, C2, C3, C4...
- Control input terminals Sl, S2. S3. S4... Switching circuit T constituting a switching bridge... Transformer Di, D2. D3. D4...Diode Ql constituting a diode bridge, Q2...Transistors A, B, Al, Bl, "', An, Bn"' Driver output terminal S1. SWI', -+Sun, 5liln'-
Power switch RCV...receiver DRVI,
..., DRVn... Driver El, ..., En...
・・Power source C Yapacita MN: NHO2 MP: PMO8 RJ, R2, Shaku 3: J Rinku Figure 1
Claims (1)
Ｓの相補型ＭＯＳのドレインに抵抗を接続し、１対の電
源端子間に順方向に並列に挿入して、該相補型ＭＯＳの
ドレインを該ＭＯＳのゲートに、該相補型ＭＯＳのゲー
トを、該電源端子間に挿入された直列抵抗の接続点にそ
れぞれ接続し、さらに、回線に接続されるトランスの１
次側をダイオードブリッジと制御可能なスイッチングブ
リッジとの並列回路を経由して前記電源端子間に接続し
たことを特徴とするドライバ回路。(1) Connect a capacitor to the drain of the MOS, and
A resistor is connected to the drain of the complementary MOS of S, and inserted in parallel in the forward direction between a pair of power supply terminals, and the drain of the complementary MOS is connected to the gate of the MOS, and the gate of the complementary MOS is connected to the gate of the complementary MOS. connected to the connection points of the series resistors inserted between the power supply terminals, and further connected to one of the transformers connected to the line.
A driver circuit characterized in that the next side is connected between the power supply terminals via a parallel circuit of a diode bridge and a controllable switching bridge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33314887A JPH01175335A (en) | 1987-12-29 | 1987-12-29 | Driver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33314887A JPH01175335A (en) | 1987-12-29 | 1987-12-29 | Driver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01175335A true JPH01175335A (en) | 1989-07-11 |
Family
ID=18262831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33314887A Pending JPH01175335A (en) | 1987-12-29 | 1987-12-29 | Driver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01175335A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012191454A (en) * | 2011-03-10 | 2012-10-04 | Toshiba Corp | Nitride semiconductor device |
-
1987
- 1987-12-29 JP JP33314887A patent/JPH01175335A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012191454A (en) * | 2011-03-10 | 2012-10-04 | Toshiba Corp | Nitride semiconductor device |
| US8624261B2 (en) | 2011-03-10 | 2014-01-07 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
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