JPH01175034A - Register group loading accelerating system - Google Patents

Abstract

PURPOSE:To remove useless load processing time by executing the succeeding register prior to the loading of a general register when an instruction next to a load task instruction does not use the general register or uses an already loaded general register. CONSTITUTION:A register is provided with a flag for displaying the completion of transfer based upon a transfer device. While executing transfer from a main storage device to the general register group, an instruction execution part starts the execution of the succeeding instruction, and at the time of generating the necessity of reference of the general register, refers a flag part corresponding to a register number concerned. When the flag part corresponding to the register number concerned is not loaded yet, its setting is waited, and when it has been already loaded, the execution of the instruction is continued.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a central processing unit in an information processing device.

More specifically, the present invention relates to a new method for loading data into a group of general-purpose registers in a central processing unit that employs a multiple virtual memory method.

2. Description of the Related Art Conventionally, in the central processing unit of an information processing device, for example, “L
An instruction (hereinafter referred to as a load task instruction) indicating a register load such as "DTASK TCBptr" instructs a load operation of a group of general-purpose registers.

This instruction causes the central processing unit to
The contents of the TCB (the contents of the general-purpose register group to be used next) at the address specified by the Bptr pointer operand are transferred to the register group of the central processing unit. In this way, the contents of the general-purpose register are updated.

FIG. 6 is a block diagram schematically showing the configuration of hardware that executes the operations described above.

This system is roughly divided into an instruction execution section and a storage section, and manually entered instructions are sent to an instruction decoding section 101.
The instruction is decoded by the instruction execution i% 103 and once stored in the register 102.

Further, the execution result is temporarily held in the register 102.

On the other hand, the main storage device 106 operates under the control of the main storage device control section 105.

In the device shown in FIG. 6, loading of the general-purpose register group is executed as follows.

First, an instruction (load task instruction) indicating loading of a group of general-purpose registers is decoded by the instruction decoder 10, and the decoded instruction is temporarily stored in the register 102. At this time,
IDUIOI does not preemptively decode the next instruction.

Next, the instruction execution unit 103 understands that it is a load task instruction based on the information in this register 102, and writes the contents of the general-purpose register group to be used next into the main register 1. The main storage controller 105 is instructed to read from the α device 106. Then, the contents of the general-purpose register group read from the main storage device 106 via the operand register 107 are stored in the general-purpose register group in the instruction execution unit 103. Finally, the next instruction to be executed is decoded, executed, and the execution result stored.

Problems to be Solved by the Invention FIG. 7 is a diagram schematically showing the process as described above.

As shown in the figure, it can be seen that there is a wasted period between the execution of the load task instruction and the execution of the next instruction. That is, in the conventional method described above, regardless of whether the next instruction actually uses general-purpose registers, load task instructions for all registers are executed, and then execution of the next instruction is started. ing. For this reason, the execution time of the load task instruction was longer than necessary.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a new register group/load acceleration method that reduces the substantial execution time of a load task instruction and enables more effective use of an information processing device.

Means for Solving the Problems According to the present invention, an information processing device includes a register group consisting of a plurality of registers, an instruction execution unit that executes manually input instructions, and data from a seed storage device to the register group. a transfer device, and further includes a flag indicating that the transfer process by the transfer device is completed, corresponding to each of the registers, and when the transfer device starts the transfer process based on a register replacement instruction. , the instruction execution unit starts executing another instruction following the exchange instruction without waiting for the completion of the transfer process, and when it becomes necessary to refer to a register included in the register group by the other instruction, , refers to the flag corresponding to the register to be referenced, and only when it is detected that the register has not been loaded yet, executes the other instruction while attending to the loading of the register. A method for accelerating the loading of registers is provided.

SeptemberThe register group/load acceleration method according to the present invention is equipped with a flag in the register to indicate that the transfer by the transfer device has been completed, and while the transfer from the main memory device to the general-purpose register group is performed, the instruction execution unit When execution of an instruction following the above instruction starts and it becomes necessary to refer to a general-purpose register in the subsequent instruction, 1 refers to the corresponding register number part of the flag, and if it has not been loaded yet, the flag is The main feature is that the corresponding register number part is set, and if the instruction has already been loaded, the execution of the instruction continues.

That is, in the conventional loading method described above, the next instruction cannot be executed unless the loading of general-purpose registers not required by the next instruction is also completed. In contrast, in the load method according to the present invention, if the next instruction after the load task instruction is an instruction that does not use a general-purpose register or an instruction that uses a general-purpose register that has already been loaded, the execution of the next instruction is transferred to a general-purpose register. By doing this before loading, it is possible to save unnecessary loading processing time.

EXAMPLES The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one example of the present invention and does not limit the technical scope of the present invention in any way. .

Embodiment 1 FIG. 1 is a diagram showing the configuration of a central processing unit in an embodiment of the present invention.

This device consists of an instruction decoding section that decodes instructions;
an instruction execution unit (hereinafter referred to as EXU) 303 equipped with a register (hereinafter referred to as IDQ) 302 for storing decoded instructions (hereinafter referred to as DU) 301; and a main storage control unit (hereinafter referred to as BCU) 306. Main memory with
It mainly includes hardware (hereinafter referred to as MS) 307 and hardware (hereinafter referred to as LDHW) 308 for loading the contents of a group of general-purpose registers. Further, as registers, a register (hereinafter referred to as OPR) 304 for storing operands read from the main memory, a register (hereinafter referred to as OPW) 305 for storing execution results, and a general-purpose register group 309 are provided.

In this embodiment, a pipeline-based advance control method is adopted, and the IDU301, EXU303, main 13
The three stages of the CU 306 are each configured to operate in parallel.

The general-purpose register group in this embodiment is configured as shown in FIG. 3(a). That is, register 0 (hereinafter referred to as R
It has 32 general-purpose registers from register 31 (hereinafter referred to as R31) to register 31 (hereinafter referred to as R31), and data is stored on the main memory in order from the lowest address to ROlRl...R31.

In addition, FIG. 3(b) shows the configuration of the circuit shown in FIG.
FIG. 2 is a block diagram showing more details, particularly focusing on the configuration of registers and buses. In addition, in Fig. 3(b), Oite, I
DU501, EXU515, BCU519, MS5
23, REG530, and LDHW527 are respectively shown in FIG. 1 (7) IDU301, EXU303, and BCU3.
06, MS307, REG309, LDHW308
It corresponds to

Furthermore, each register has the following functions.

That is, a register (hereinafter referred to as BR) 502 is a register that stores the number of a pace register to be read when decoding an instruction, and a register (hereinafter referred to as ■R) 503 is a register that stores the number of an index register to be read when decoding an instruction. register (hereinafter referred to as IDC)
A register (hereinafter referred to as OPW) 510 stores decoded information of the IDU, and a register (hereinafter referred to as OPW) 517 stores the decoded information of the IDU.
The execution result sent by 6 is stored, and the register (hereinafter referred to as
OPR) 520 stores data read from the main memory by the BCU. In addition, the flag register 531
is a collection of flags indicating registers that have been loaded from main memory for the number of general-purpose registers.

On the other hand, the configuration of the bus is as follows.

That is, the bus (hereinafter referred to as ΔREGF) 504 has an ID
Inform the pace register number and index register number from U301, and transfer to the bus (hereinafter referred to as BREGF).
505 is the pace register number L from B R502.
D Inform CHK2O2 and bus (hereinafter referred to as IREGF)
) 506 notifies the LDCHK 507 of the index register number from the IR 503 , the bus 509 sends the decoded information of the IDU to the register IDQ 510 , and the bus (hereinafter referred to as EBUS) 511 sends the contents of the general-purpose register cent 530 is transferred to the IDU/EXU.

Bus 512 sends the decoded information of IDQ 510 to E.
Transfer to X U315. Furthermore, the bus 513 sends the register number of the first operand during execution to EXCHK524.
The bus 514 informs the EX CHK 524 of the register number of the second operand at the time of execution, and the bus 51
6 transfers the execution result to the OP WSi2 and transfers the execution result to the bus 518.
transfers the contents of 0PW517 to main storage control unit B CU3.
The bus 521 transfers the contents of the general-purpose register group read from the main memory, that is, the contents of the OP R520, to the E
The data bus 522 reads/writes data from the main memory, and the bus 526 transfers the contents of the general-purpose register group read from the main memory to the L
The bus 528 is transferred to the LDHW527.
The contents of the general-purpose register group read from the main memory are transferred from the W527 to the general-purpose register group 530.

Furthermore, the hardware (hereinafter referred to as LDCHK)5
07 outputs a wait signal 508 to the IDU 301 when the corresponding part of the loaded register flag 531 of the register of BR 502 and IR 503 is 1''.Hardware (hereinafter referred to as EXCHK) 524
outputs a wait signal 525 to the EXU 515 when the corresponding part of the flag 531 indicating that the register indicated by the bus 513, 514 has been loaded is Bi. Hardware (hereinafter referred to as LDHW) 52
7 transfers the contents of the general-purpose register group read from the main memory to the general-purpose register group 530.

A signal (hereinafter referred to as WAIT IDU) 508 instructs the IDU 301 to suspend/resume instruction decoding, and a signal (hereinafter referred to as WAITEXU)
525 LJ interrupts instruction execution for EXU515/
Instruct to restart.

The process of loading the general-purpose register group in the central processing unit configured as described above is explained in Figures 1 and 3.
This will be explained below with reference to FIGS. In this embodiment, 1. The contents of the general-purpose register group α are called a task. Further, an instruction that instructs to load the contents of a general-purpose register group from the main memory to a general-purpose register group in the central processing unit is called a load task instruction.

When the instruction decoding unit TDU 501 decodes an instruction (load task instruction) that instructs the loading of a group of general-purpose registers, it stores the decoded information in the IDQ 510. Then, it preemptively decodes the next instruction.

The number of the pace register used in decoding the next instruction is stored in the BR 502 through A RE G F2O3.

Similarly, the index register number to be used in the next instruction decoding is sent to I R50 through AREGF504.
Store in 3.

Then, LDCHK507 sets the pace register and index register numbers used in decoding as BR5.
02, I Obtain information on loaded registers from R503 and check whether the pace register and index register have already been loaded, and check whether the pace register and index register are already loaded.
WAIT I DU 508 if not already loaded.
to II OII.

ID 0501 interrupts advance decoding when WAITI DU508 is 1'', and WAITI
When DU508 is '0', advance decoding is restarted.

Understand that it is a load task instruction through E
Through D532, the LDHW527 is instructed to start register loading. Also loaded register flag 53
Initialize all 1 to OII.

E X U 303 finishes executing the load task instruction,
If the next instruction decoding information ID Q510 is valid, execution of the next instruction is started. Then, from IDQ510, the general-purpose register used in the next instruction, register number 0PRI of the first operand, is sent through bus 513 to EX CHK.
524 and register number 0PR2 of the first operand.
is sent through Hass 514 to TeX CHK 524.

EXCHK524 Obtains the register number to be used in the next instruction through the bus 513 and bus 514, and obtains information about the loaded general-purpose register from the loaded register flag 531, checks whether the register has already been loaded, and checks if the register has already been loaded. WAI T if already loaded
Set E

EX U315 fiWA I TEX [52
When 5 is "1", execution of the next instruction is interrupted and WA
When ITEXU515 is "0", execution of the next instruction is resumed.

When EXU executes an instruction, it reads the first operand and second operand from OP R520 and outputs the execution result.
Store in P WSi2.

The LDHW527 receives the register load start instruction LDCMD532 signal from the EXU515 and loads the main memory 5.
TCB at the address indicated by the task register (TR) in 23 (contents of general-purpose register group) 52
6. Transfer to general purpose register group 530 via bus 528. At this time, TR points to the general-purpose register RO, and R
Transfer is performed in the order from O to R31. For the registers that have been transferred, the corresponding bits of the loaded register flags 531 are set to "bi".

FIG. 2 is a load timing diagram of the general-purpose register group in the embodiment of the present invention shown in FIG. 1 and FIG. 3(a), et al.

In FIG. 2, 401 indicates the instruction decoding timing of the IDU, and 402 indicates the instruction execution timing of the EXU.
403 is the timing of BCU operation, 404 is TCB
405 indicates the timing of the operation of L, and 405 indicates the timing of reading/writing from the main memory.

As shown in FIG. 2, in the configuration of this embodiment, the load operation of the general-purpose register group of the load task instruction is delayed;
The execution time of the load task instruction can be shortened by executing the next instruction first and loading the general-purpose register group during operand access of the subsequent instruction.

Example 2 FIG. 4 is a diagram illustrating another aspect of the present invention. That is, in the first embodiment, the loading of the general-purpose register group by the load task instruction was explained, but
This method can also be applied to subroutine calls/returns.

As shown in Figure 5, when calling/returning a subroutine, arguments are written to an area called the stack, and the call instruction writes to the old AP (argument pointer) and old PC (program counter) and branches. . At the branch destination, the general-purpose registers used in this subroutine are bushed and instruction execution begins.

When the execution of this subroutine is completed, the contents of the general-purpose register group bushed in the stack area are loaded into the general-purpose register group in the central processing unit, and the process returns to the main routine.

The general-purpose register group loading method of the first embodiment can also be used to load the general-purpose register group at this time.

Effects of the Invention As detailed above, according to the present invention, the next instruction is executed prior to the completion of the load processing of the general-purpose register group of the load task instruction, and the general-purpose register group is executed during the operand access of the subsequent instruction. Loading a group of registers can be performed to substantially reduce the execution time of a load task instruction.

This also increases the number of general purpose registers. With the recent improvement in the degree of integration of LS2, it is an effective means for configuring a central processing unit having a larger number of general-purpose register groups.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the configuration of a central processing unit capable of implementing the method of the present invention, and FIG. 2 is a general-purpose register group explaining the operation of the device shown in FIG. FIG. 3(a) is a block diagram showing the configuration of the central processing unit shown in FIG. 1 in more detail, especially regarding the configuration of the general-purpose register group; Figure (b) is a block diagram showing the configuration of the central processing unit shown in Figure 1 in more detail, especially regarding the configuration of registers and buses, and Figure 4 is a block diagram showing the general-purpose registers in the device shown in Figure 1. 1 is a block diagram showing the structure of the group in more detail; FIG. 5 is a block diagram showing the structure of the subroutine call/return stack area in another aspect of the present invention; FIG. 7 is a block diagram schematically showing the configuration of hardware that executes the register loading method. FIG. 7 is a diagram schematically showing the operation of the conventional register loading method. [Main reference numbers] 101...Instruction decoding unit (IDU), 102...
...Register, 103...Instruction execution unit, 105...Main storage control unit, 106...Main storage (MS), 302...
・ Register (more Q), 303... Instruction execution unit (EXU), 304... Register (OPR),
305... Register (OPW), 306...
...Main storage unit control unit (BCU), 307...
This is the main memory (MS). 308... Transfer device (LDHW), 309...
... General-purpose register group, 501 ... Instruction decoding unit (IDU), 502 ...
... Register (BR), 503... Register (IR), 504... Bus (AREGF),
505... Bus (BREGF), 506...
... Bus (IREGF), 510 ... Register (tDQ), 511 ... Bus (EB
US), 515... Instruction execution unit (EXU), 51
7... Register (OPW), 519...
・Main storage unit control unit (BCU), 520... Register (OPR), 523... Main storage unit (MS
), 530...General-purpose register group, 531...Flag register

Claims (1)

[Scope of Claims] An information processing device, comprising at least a register group consisting of a plurality of registers, an instruction execution unit for executing an input instruction, and a data transfer device from a seed storage device to the register group, and further comprising: , a flag indicating that the transfer process by the transfer device has been completed is provided corresponding to each of the registers, and when the transfer device starts a transfer process based on a register replacement instruction, the instruction execution unit executes the transfer process by the transfer device. If execution of another instruction following the exchange instruction is started without waiting for the completion of processing, and it becomes necessary to refer to a register included in the register group by the other instruction, the register corresponding to the register to be referenced is generated. 1. A method for accelerating loading of a register group, characterized in that the register is loaded and the other instruction is executed only when it is detected that the register has not been loaded yet by referring to the flag.