JPH01174135A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To detect an error not detected by parity check by adding a simple hardware comprising an FF circuit, a subtractor, an absolute value converting circuit, a code comparator, an error permissible value output device and a comparator. CONSTITUTION:A code inputted to a reception terminal A is latched by an FF circuit 2 and a difference between the existing code from the reception terminal A and a preceding code being an output of the FF circuit 2 is obtained by a subtractor 3. Moreover, the sign of the existing code and the preceding code is compared by a sign comparator 4 and the allowable value of the sign error is outputted from an error permissible value output device 5 based on the said output. The output of the subtractor 3 is supplied to a comparator 6 via an absolute value converting circuit 1, compared with the output of the error permissible value output device 5 to detect whether or not the existing sign has an error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error detection circuit, and more particularly to a circuit for detecting errors in a code as a digital signal that is analog-to-digital converted and transmitted.

[Prior Art] Conventionally, as an error detection circuit for the code of a digital signal that is transmitted after being analog-to-digital converted (A/D converted), a parity check circuit that adds one redundant bit for error correction has been used. There is a circuit.

[Problem that the invention seeks to solve]

The conventional parity check circuit described above can detect odd bit errors, but cannot detect even bit errors. Even-numbered bit errors can be detected by increasing the number of redundant bits for error correction, but this increases the amount of hardware and increases the code length, which poses the problem of requiring a correspondingly larger transmission capacity.

The present invention attempts to solve these problems of the conventional method by adding simple hardware (thereby providing an error correction circuit that can detect errors that cannot be detected even by parity checking). It is.

In the following, [Means for solving the problem] The error detection circuit according to the present invention C2 is applied to an analog signal band-limited at two frequencies fc (H times fc (however, H≧
2) is an error detection circuit for detecting an error in a code as a digital signal obtained by analog-to-digital conversion at the frequency.

a receiving terminal for receiving the code; a flip-flop circuit connected to the receiving terminal for holding the code value; and a flip-flop circuit connected to the receiving terminal and the flip-flop circuit for receiving the current code value from the receiving terminal and the A subtractor for calculating the difference between the previous code value, which is the output of the flip-flop circuit, and the sign of the current code value and the previous code value. a code comparator for comparison; and a code comparator connected to the code comparator to determine the sign relationship between the current code value and the previous code value and the dynamic range M of the analog-to-digital converter and the value of the H value by the output of the code comparator. π M ゛ Two types of sign error tolerance M-stn T+ 2・s
an error tolerance output device that selects and outputs either one of the subtractors; an absolute value conversion circuit that is connected to the subtracter and that determines the absolute value of the difference output from the subtracter; and the error tolerance output device and a comparator that compares the output from the absolute value converter with the absolute value that is the output from the absolute value conversion circuit and detects that the absolute value is larger than the error tolerance (= there is an error in the current code) be done.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the error detection circuit of the present invention, and FIG. 2 is a diagram showing an analog original signal before A/D conversion. In FIG.

A flip-flop circuit 2 is connected to the receiving terminal A, and is used to hold the code connected to the receiving terminal A. 5 is a subtracter connected to the receiving terminal A and the flip-flop circuit 2, and is used to find the difference between the current code value from the receiving terminal A and the previous code value which is the output of the flip-flop circuit 2. be. Similar to the subtracter 5, 4 is connected to the receiving terminal A and the flip-flop circuit 2 (= connected,
This is a code comparator for comparing the signs of the current code value and the previous code value. Reference numeral 5 denotes an error tolerance output device that outputs a tolerance value for code errors based on the output of the code comparator 4. Reference numeral 1 denotes an absolute value conversion circuit connected to the subtracter 3 for determining the absolute value of the difference output from the subtracter 3. 6 is a comparator connected to the absolute value conversion circuit 1 and the error tolerance output device 5, and y (t) in FIG. It's a signal.

First, the codes received at the receiving terminal A in FIG. 1 will be explained with reference to FIG. 2. In addition, the original signal Y shown in Fig. 2
(t) is the frequency f. This is the analog signal after being band-limited. here.

The original signal Y (t) in the same figure is multiplied by H times the frequency fc (however, H
It is assumed that a code sampled at a frequency of ≧2) and subjected to analog-to-digital conversion is received at receiving terminal A in FIG. When analog-to-digital conversion is performed at a sampling frequency that is H times the frequency fc above, the second
The absolute value of the difference between the original signals Yy(ti) and y(ti++) in the figure (2 in the figure) is the dynamic range M of the analog-to-digital converter, and the sample value Y(tz) r
Assuming that the sign of Y(ti++) is f Si + Si+1, there are the following characteristics.

81\S1+1 case 2≦M・8in(-#)・
...(1) When M 2π 51=Si+1 Z≦7− s 1n (T
) - (2) In addition, Fig. 2 shows the frequency fo (however, fo =
fc) sine wave (Y(t) = sin 2 πf□ t
) shows this original signal.

Based on the above characteristics, the present invention attempts to detect even-numbered pit errors that cannot be detected by a parity check circuit using the following procedure.

First, by paying attention to the features shown in equations (1) and (2) regarding the absolute value 2 of the difference between adjacent sample values mentioned above, and using the flip-flop circuit 2 and subtractor 3 shown in FIG. After determining the difference between the value and the current code value, the absolute value conversion circuit 1 determines the absolute value 2.

Furthermore, using the code comparator 4, the codes Si and Si+1 of the previous code value and the current code value are compared, and Si! XSi+1
Then, the error tolerance value output device 5 in the figure outputs the tolerance value Main() added to equation (1), and if 5i=Si+1, then M.

For example, the allowable value B1n2 added to equation (2) from the same output device 5
Output πT. Finally, using the comparator 6, the absolute value 2 of the difference between the previous code value and the current code value obtained by the above-mentioned subtracter 6 and absolute value conversion circuit 1 is outputted from the error tolerance value output device 5. It is determined whether it is larger than the value, and if it is larger, an error signal is output to output terminal B in the figure.

By performing the above processing, even the even-numbered pit errors in the code that cannot be detected by parity checking can be treated as large errors (adjacent sample values The absolute value of the difference is the Zmax
The above errors) can be made detectable.

〔Effect of the invention〕

As explained above, the present invention has the advantage that even errors that cannot be detected by parity checking can be made detectable by adding simple hardware.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the error detection circuit of the present invention, and Fig. 2 shows an analog original signal 2 before A/D conversion with frequency fc and amplitude M (M: A/D dynamic range). It is a diagram. DESCRIPTION OF SYMBOLS 1...Absolute value conversion circuit, 2...Flip-flop circuit, 5...Subtractor, 4...Sign comparator, 5...
Error tolerance value output device, 6... comparator. Figure 1 Figure 2

Claims (1)

[Claims] 1. Error detection circuit for detecting code errors in digital signals obtained by performing analog-to-digital conversion on analog signals band-limited at frequency f_c at a frequency H times f_c (however, H≧2) a receiving terminal for receiving the code; a flip-flop circuit connected to the receiving terminal for holding the code value; and a flip-flop circuit connected to the receiving terminal and the flip-flop circuit for receiving the current from the receiving terminal. a subtracter for finding a difference between a code value and a previous code value that is the output of the flip-flop circuit; a code comparator for comparing the signs of the current code value and the previous code value; Two types of code error tolerance values M・sin(π/ H
), (M/2)・sin(2π/H), and an error tolerance output device that selects and outputs either of them, and is connected to the subtracter to obtain the absolute value of the difference output from the subtracter. The absolute value conversion circuit is connected to the error tolerance value output device and the previous unit absolute value conversion circuit, and the output from the error tolerance value output device is compared with the absolute value that is the output from the absolute value conversion circuit. and a comparator that detects that there is an error in the current code when the value is greater than an error tolerance value.