JPH01300744A - Signal discrimination circuit - Google Patents

Abstract

PURPOSE:To certainly perform A/D conversion by discriminating input analog signals from their different delayed time and, at the same time, outputting the input analog signals in parallel with each other by delaying them to the same overall delayed time so as to make majority decision. CONSTITUTION:Discrimination circuits 111, 112,...,11m are constituted in parallel in (2n+1) stages and delay circuits are respectively connected to the circuits 111, 112,..., 11m in series so that output data can be obtained by taking majority by delaying the discriminating time by one time slot. Intermediate-frequency signals inputted to a demodulator 1 are A/D converted by the 1st, 2nd,..., m-th discriminating sections 11, 12,..., 1m end inputted to a majority circuit 2 after they are discriminated on different time bases and their delayed time is made to equal to each other. Therefore, deterioration of the bit accuracy which occurs when a high speed discrimination circuit is used can be prevented and an error in signal discrimination caused by sparking noises, vibrations, etc., produced from a peripheral device of a receiver.

Description

[Detailed Description of the Invention] [Summary] Regarding the signal identification circuit in the multi-level quadrature amplitude modulation method of the digital wireless system, there is a problem with the bit accuracy that occurs when using a high-speed identification circuit (
The purpose is to prevent errors in signal identification due to spark noise, vibration, etc. generated from around the receiver, and to identify each input analog signal with a different delay time, and to make sure that the total delay time is the same for all input analog signals. a plurality of parallel first, second, . The present invention is configured to include a majority decision circuit that makes a majority decision on signals inputted and identified at different times on the same time axis.

[Industrial application field]

The present invention relates to a signal identification circuit used, for example, in a multilevel orthogonal amplitude modulation method of a digital wireless method.

In recent years, modulation methods in digital radio systems are becoming more multivalued in order to effectively utilize frequencies.

As the number of multi-values increases, the discrimination margin of the demodulated signal becomes more difficult.
Even with a high-performance identification circuit, there is not enough room for multi-level identification, so slight noise or distortion can cause erroneous identification. However, as a standard for large-capacity digital wireless systems, there is almost no error rate in steady state, for example, i
The current situation is that ``o-''> is required.

Therefore, it is necessary to have a circuit that does not operate erroneously even in the presence of spark noise, vibration, etc., for example.

[Conventional technology]

FIG. 3 is a diagram showing the configuration of a conventional embodiment.

In the figure, 21 is a demodulator, and 22 is an identification circuit.

In the conventional method, one demodulator 21 and one identification circuit 22 are provided in series, and an intermediate frequency signal is input to the demodulator 21 and demodulated and converted into a multi-level analog signal, and then the identification circuit 22 converts the intermediate frequency signal into an analog signal. / After performing digital conversion, m-bit digital data output is obtained.

Note that conventionally, an analog/digital converter is used for the identification circuit 22, but there is no high-speed, high-precision converter.
The A/D converter used in 2 is also used at the full capacity of the standard. For this reason, when the identification circuit 22 that performs A/D conversion is used at high speed, the bit accuracy deteriorates, and the bit accuracy of digital data after signal identification deteriorates. For this reason, even if a high-performance A/D converter is used, errors may occur if there is a spark or slight vibration from around the receiver, or if human input is applied to the main body or input terminal of the demodulator 21 or identification circuit 22. was occurring.

[Problem to be solved by the invention]

Therefore, if the A/D converter is used at high speed, the bit accuracy may deteriorate, and there are problems that errors may occur due to the operation of the A/D converter when there is spark noise, vibration, etc. generated from around the receiver. be.

An object of the present invention is to prevent deterioration in bit accuracy that occurs when a high-speed identification circuit is used, and to eliminate errors in signal identification due to spark noise, vibration, etc. generated from around the receiver.

[Means to solve the problem]

FIG. 1 is a block diagram showing an embodiment of the present invention.

11.12,...1m is the first, second,...M-th identification section, which identifies the human analog signals with different delay times, and parallelizes them with delays so that the total delay time is equal for all. Output to.

In the majority circuit 2, the above 11.12,...1m
The outputs of the first, second, .

[Effect]

In the present invention, as shown in FIG.
, . . 11m are arranged in parallel in (2n + 1) stages, and delay circuits are connected in series so that the identification time is shifted by one time slot and a majority vote is taken to obtain output data.

As a result, it is possible to correct the uncertainties of the identification circuits 111, 112, .

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a demodulator and 2 is a majority circuit.

11 is an identification circuit 111 and a delay circuit T12, T
13... is connected in series, and 12 is a delay circuit T21 and an identification circuit 1.
12 and a delay circuit T23 are connected in series, and similarly, 1m is a delay circuit Tml, Tm2.
... and an identification circuit 11m.

As shown in FIG. 1, the intermediate frequency signal input to the demodulator 1 is A/D converted by the first identification section 11, the second identification section 12, and the m-th identification section 1m. The times of the signals input to the m identification circuits 111, 112, . After that, it is input to the majority circuit 2.

FIG. 2 shows the majority table of the majority circuit 2, - for example
is 3, that is, a three-stage configuration.

As shown in the figure, a first identification section 11, a second identification section 12
Since the output of the third identification section 13 takes either "1" or "0", the output of the majority circuit 2 outputs the larger value of "1" or "0°."

Note that the number of bits of 1 or "0" is determined by the number of bits of the identification circuit.

〔Effect of the invention〕

As explained above, according to the present invention, the A/
Since D conversion can be performed reliably, by applying it to a system that requires high-speed, high-precision conversion, it becomes possible to reproduce data with good bit precision.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a majority voting table, and FIG. 3 is a diagram showing the configuration of a conventional embodiment. In the figure, 11 is a first identification section, 12 is a second identification section, 1m is an m-th identification section, and 2 is a majority circuit. Ichimari (on-site)

Claims (1)

[Claims] A plurality of parallel first, second, ..., M-th identifications that identify input analog signals with different delay times, and output the signals after being delayed so that the total delay times are all equal. (11, 12, . . . , 1m); and the plurality of first, second, . . . , M-th identification portions (11, 12, ..., 1m);
12,..., 1m), and a majority circuit (2) that performs a majority decision on signals identified at different times on the same time axis. .