JPH01174078A - Video signal processor - Google Patents

Abstract

PURPOSE:To avoid the deformed pattern by keeping a level of a digital signal value to a level higher than a pedestal level when the level of a digital signal outputted from a bit interleaving circuit is lower than the level in the vicinity of the pedestal level in a video period. CONSTITUTION:When a data outputted from a bit interleaving circuit 6 in the video period is a digital video signal smaller than a prescribed reference value, the signal subject to interleaving is controlled by OR gates 30, 31, AND gates 39-42 and an inverter gate 43. Then let the lowest level of the composite video signal be 0% and the highest level be 100%, the digital video signal in the video period is kept constant when the signal level is 0-25% in the video period range. Then the bit interleaving is applied in the case of a level of 25-100% and the data inputted to a D/A converter 10 does not reach a level lower than 25%. Thus, the deformed screen is avoided.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a video signal processing method that can be used in video tape recorders, television receivers, etc., and can create artistic effects by dropping bits of digital video signals. It is related to the device.

(Prior art) In recent years, with advances in digital technology and memory technology, video signals processed in video tape recorders and television receivers are converted into digital signals and stored in memory, making it possible to convert television broadcast images into still images. , products with functions such as displaying many pictures on one screen have been commercialized.

Among these digital functions, there is a function that creates an oil painting-like image by fixing the lower bits of the digitalized luminance signal to O or 1 and dropping the information (hereinafter abbreviated as art function). ).

FIG. 3 is a block diagram of a conventional video signal processing device having an art function. In the figure, 51 is an input terminal for a composite video signal; 52 is an A/D converter that converts the input video signal into a digital video signal;
53 is a bit dropping circuit that achieves an art function; 54 is a D/A converter that converts a digital video signal into an analog video signal; 55 is an output terminal for the video signal; and 56 is input to the input terminal 51. 57 is a clock generation circuit that generates a clock; 58 is a sync signal separation circuit 56 that detects a sync signal from a video signal;
A video period detection circuit 59 detects the video period excluding the blanking period of the composite video signal from the synchronization signal sent from the synchronization signal sent from the clock generation circuit 57 and the clock sent from the clock generation circuit 57. The setting switch 60 sets the on/off and degree of the art function according to the input of the switch 59, and the bit dropping circuit 5
A control circuit that sends commands to 3.

61 to 66 are signal lines for the digital video signal converted by the A/D converter 52, where 61 is the signal line for the most significant bit, the lower bits are arranged in numerical order, and 66 is the signal line for the least significant bit. Note that although this example is explained using a 6-bit digital signal, any number of bits may be used as long as it is 3 or more bits. 70 to 75 are OR gates, and 76 to 81 are AN
It is a D gate, and 82 to 87 are control lines for controlling the bit dropping circuit 53 from the control circuit 60.

The operation of the conventional video signal processing device having an art function configured as described above will be explained with reference to FIGS. 3 and 4.

FIG. 4 is a diagram showing a video signal using a conventional art function. (h) is an input composite video signal, and (i) is a signal detected by the video period detection circuit 58, in which a low level is a video period and a high level is a blanking period. (j) is an output video signal with the lower 4 bits dropped. The video period detection circuit 58 in FIG. 3 counts the clocks from the clock generation circuit 57 based on the synchronization signal detected by the synchronization signal separation circuit 56, and
The waveform shown in figure (i) is created. A case will be described in which the control circuit 60 is set to a mode in which the lower four bits are dropped by the switch 59. At this time, the control lines 82 and 83 output from the control circuit 60 are at High level.

The lower 4 bits of control lines 84 to 87 are at low level.

However, since the signal output from the video period detection circuit 58 is at a high level during the blanking period as shown in FIG. 4(i), the outputs of the OR gates 70 to 75 are high.
level, and within the video period it is Lo% level, and O
The output of the R gate 70.7 is high level, and the output of the OR gates 72 to 75 is low level.
The output of 1 becomes a Low level output within the video period. The input video signal is processed by the A/D converter 52 as shown in FIG.
As shown in h), the lowest level of the synchronization signal is oooo
In the value of oo, the highest level of the video signal is 111111
The value is converted into a 6-bit digital signal.

When the lower 4 bits of the converted digital video signal are dropped to O and the analog signal is returned by the D/A converter 54, the waveform becomes as shown in FIG. 4(j). As described above, the art function creates a sticky oil painting-like image by fixing the lower bits of the signal to a low level during the video period excluding the blanking period.

(Means for solving the problem) However, with the above configuration, if there is an undershoot in the input video signal as shown in Figure 4k, or if the black level drops to the synchronization signal level, the output There was a drawback that the video signal dropped to the lowest level of the synchronizing signal, as shown by Ω in FIG. 4, and the screen of the television receiver was distorted.

An object of the present invention is to eliminate the conventional drawbacks and maintain a constant value that is lower than a certain reference value within a video period, thereby preventing the synchronization signal from dropping to the lowest level. To provide a video signal processing device which does not cause a screen to be distorted due to bit drop even when input.

(Means for Solving the Problems) The video signal processing device of the present invention includes an A/D converter that converts a composite video signal into an n-bit digital signal, and a D/D converter that converts this digital signal into a composite video signal. A converter and
A synchronization signal separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from a composite video signal, a clock generation circuit that generates a clock, and a video circuit that counts clocks and detects video periods based on the horizontal synchronization signal and vertical synchronization signal. A period detection circuit, a bit dropping circuit that fixes the data value of a specified bit in the digital signal input to the D/A converter to 0 or 1, turning on/off bit dropping, and deciding which bit to drop. It is equipped with a control circuit that instructs the bit drop circuit, and a clamp circuit that holds the output signal of the bit drop circuit at a constant level when it is smaller than a certain reference value within the video period.

Further, the clamp circuit operates even when bits are not dropped.

(Function) According to the present invention, with the above configuration, when the digital signal output from the bit dropping circuit has a signal value lower than the vicinity of the pedestal level within the video period, by holding the digital signal at a signal value higher than the pedestal level, A signal with the same level as the synchronizing signal is no longer output within the video period, and the screen does not warp, which was a drawback of the conventional method.

(Example) An example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a block diagram of a video signal processing device having an art function according to the present invention. In the figure, 1 is an input terminal for a composite video signal, 2 is an A/D converter that converts the input video signal into a digital video signal, and 3 is an A/D converter that converts the input video signal into a digital video signal.
is a synchronization signal separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the input composite video signal; 4 is a clock generation circuit that generates a clock; 5 is a clock generation circuit that counts clocks based on the horizontal synchronization signal and vertical synchronization signal; A video period detection circuit that detects the video period, 6 a bit dropping circuit that achieves the art function, 7 a switch that sets the art function on/off and the degree of the art function, and 8 a switch that controls the art function according to the input of the switch 7. A control circuit that sets ON/OFF and the degree and sends a command to the bit dropping circuit 6 as to which bit to drop. 9 is a clamp circuit that holds the digital video signal at a constant level. IO converts the digital video signal into an analog video signal. 11 is a video signal output terminal, 12 to 17 are signal lines for the digital video signal converted by the D/A converter 10, and 12 is the most significant bit signal. The lines indicate the lower bits in numerical order, and 17 is the signal line for the least significant bit. 18-2
3 is a control line for controlling the bit dropping circuit 6 from the control circuit 8, 24 to 31 are OR gates, and 33 to 42 are AND gates.
The gate 43 is an inverter gate.

The operation of the video signal processing device configured as described above will be explained with reference to FIGS. 1 and 2.

FIG. 2 is a diagram showing a video signal by the art function of the present invention, in which (a) is an input composite video signal, (b) is a signal detected by the video period detection circuit 5, and Lo relevel is a video signal. The high level is the blanking period. (C) is an output video signal with the lower 4 bits dropped. When the control circuit 8 selects a mode in which the lower 4 bits are dropped by the input of the switch 7, the control lines 18 and 19 are outputted as a high level, and the control lines 20 to 23 are outputted as a low level. However, as shown in FIG. 2(b), the output of the video period detection circuit 5 is at a high level during the blanking period, so the outputs of the OR gates 24 to 29 are at a high level, and are at a low level during the video period. Tame OR gate 2
The output of 4°25 is High, the outputs of OR gates 26 to 29 are Low level, and A of the bit dropping circuit 6 is
The ND gates 35 to 38 output low level during the video period. Further, when the data output from the bit drop circuit 6 within the video period is a digital video signal smaller than a certain reference value, the bit dropped signal is transmitted to the OR gate 30, 31, AND gates 39 to 42, and the inverter gate 43. controlled by. The functions of the OR gates 30, 31, AND gates 39-42, and inverter gate 43 are controlled by the output of the AND gate of the bit dropping circuit 6.

Only when the outputs of the AND gates 33 and 34 are low level and the video period detection circuit 5 is low level, the output of the OR gate 31 is high level, and the AND gates 39 to 42
The output of the digital video signal input to the D/A converter 10 is held at 010000 at a low level.

In other words, within the video period, the digital video signal
For oooooo ~ 001111, set the data to 01000
If the lowest level of the composite video signal is 0% and the highest level is 100%, it will be held at a constant value when the signal level is 0 to 25% within the video period range. When the level is between 0 and 25%, it is held at a constant value, and when the level is between 25 and 100%, the bits are dropped and the data input to the D/A converter 10 will never be at a level lower than 25%. 0 In the normal composite video signal, the ratio of the synchronization signal level shown in Fig. 2 d and the video signal level shown in e is d':a = 0.4:l, and the synchronization signal level and the video signal level are According to this embodiment, even if there is a low-level signal as shown in FIG. 2 f during the video period, the signal is maintained near the pedestal level as shown in FIG. 2 g. This can solve the problem of the screen being curved.

In this embodiment, a 6-bit digital signal has been described, but any number of bits may be used as long as it is 3 or more bits. Furthermore, although the case where the lower 4 bits are dropped has been described, if the digital signal is n bits, any number of bits may be dropped as long as it is (n-2) bits or less. Furthermore, in this embodiment, the data value of the digital signal is held at a certain level by the value of the upper two bits of the digital signal, but the data value is compared with the value near the pedestal level, thereby maintaining the data value. It is also possible to have a configuration in which the desired value is determined.

(Effects of the Invention) According to the present invention, by maintaining the digital signal at a certain level depending on the signal level, a stable art effect on the screen can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing a video signal using the art function of the present invention, and FIG. 3 is a block diagram of a conventional video signal processing device. FIG. 4 is a diagram showing a video signal using the conventional art function. 1...Input terminal, 2...A/D converter, 3...
Synchronous signal separation circuit, 4...Clock generation circuit, 5
...Video period detection circuit, 6...Bit dropping circuit, 7...Switch, 8...Control circuit, 9...
・Clamp circuit, 10...D/A converter, 11...
Output terminals, 12-17...Signal lines, 18-23...
Control line, 24-31-OR gate, 33-42-A
ND gate, 43...inverter gate. Figure 2

Claims (2)

[Claims] (1) An A/D converter that converts a composite video signal into an n-bit digital signal (n is a positive integer of 3 or more); a D/A converter that converts the digital signal into a composite video signal; A synchronization signal separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from a video signal, a clock generation circuit that generates a clock, and a video signal that counts clocks and detects video periods based on the horizontal synchronization signal and vertical synchronization signal. A period detection circuit, a bit dropping circuit that fixes the data value of a specified bit to 0 or 1 among the digital signals input to the D/A converter, and a bit dropping circuit that determines whether bit dropping is turned on or off and which bit is dropped. , a video image characterized by comprising a control circuit that instructs the bit drop circuit, and a clamp circuit that holds the output signal of the bit drop circuit at a constant level when it is smaller than a certain reference value within a video period. Signal processing device. (2) The video signal processing device according to claim (1), wherein the clamp circuit operates even when bits are not dropped.