JPH01173493A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a cycle time and to obtain a high-speed action by transferring data at an (n) bit latched with a data latch circuit beforehand to a data shifting circuit after the completion of the output of the data at the (n) bi from the data shifting circuit. CONSTITUTION:The data at the (n) bit read from a memory block MB when the combination of a prescribed row address and a column address is supplied are transferred through the (n) number of respective data latch circuits OL to a data shifting circuit. Next the data at the (n) bit are serially outputted from the data shifting circuit. While the data are outputted form the data shifting circuit, only the column address is changed, the data at the (n) bit are read from the memory block MB, and the data at the (n) bit are once latched to the (n) number of the latch circuits OL. Thereafter, the data at the (n) bit latched by the data latch circuits OL beforehand are transferred to the data shifting circuit, and the data at the (n) bit are serially outputted from the data shifting circuit. Thus, the high-speed action is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory using dynamic memory cells, and particularly to a semiconductor memory suitable for an image field memory.

(Prior Art) Recently, digital processing technology has been introduced into the field of video. The adoption of digital processing makes it easier to achieve no-adjustment and advanced image processing compared to conventional analog processing. In order to perform such digital image processing, a large-capacity memory is required, and memory that handles high-speed serial data, such as image memory, has conventionally been configured as shown in Figure 6 in order to speed up access time. It is configured as shown in the block diagram.

In FIG. 6, MB1 to MBn are dynamic memory cell arrays MAL to M A n, sense amplifiers SAI to SAn, respectively, and column decoders CDI.
It is a dynamic memory block consisting of ~CDn, and RD is a dynamic memory block consisting of each of these n memory blocks MBI~
This is a row decoder provided in common for M B n. The n-bit data read from these n memory blocks MBI-MBn is transferred to n shift registers 5.
Supplied to ORI~5ORn.

In a memory having such a configuration, as shown in the timing chart of FIG. 7, when one read address consisting of a combination of a row address and a column address is first given, one read address is read from each of n memory blocks MBI-MBn. Bit data is read out in parallel. These n
The bit data is taken into n shift registers 5ORI to 5ORn in synchronization with the take-in signal φR, and then
Serial output data OUT is obtained by being output in synchronization with serial clock signal φout. In this way, parallel-to-serial conversion of read data is performed.

FIG. 8 shows the memory shown in FIG. 6 having an 8-bit output, and further includes eight shift registers 5IR for data input.
By adding I-8IR8, 8 input registers ILL-IL8 and data input/output switching circuit 10SI-1088,
9 is a block diagram of a conventional memory capable of double speed reading, and FIG. 9 is a timing chart thereof. 2x speed read means serial input data I
This is to read the serial output data OUT at twice the speed as compared to N, and is used in a high-definition image technique called field double scan of television.

Note that the signal φ1n in FIGS. 8 and 9 is a serial clock signal for transfer to n shift registers 5IRI to 5IR8, and the signal φW is a serial clock signal for transfer to n shift registers 5IRI to 5IR8. This is a take-in signal that is input when transferring input data to n input registers ILL to IL&. Then, the n-bit data taken into the input registers ILI to IL8 is written to eight memory blocks MBI to MBg via the data input/output switching circuits 10SI to 1088, and when reading data, the data input/output switching circuit 10SI ~l0
8I! 8-bit read data is supplied to shift registers 5ORI to 5OR8. Note that tMC in FIG. 9 is the chip enable signal C at the time of reading (data reading) or writing (data writing).
This is the cycle time of E.

By the way, when double-speed reading is performed with a conventional memory having the configuration as shown in FIG. 8, the cycle time tMC of the chip enable signal CE is quite short. For example, in the timing chart of FIG. 9, assuming that the frequency of the serial clock signal φ1n is 13.5 MHz and the frequency of φout is 27 MHz, the cycle time tMC is two times φin, so (1/13.5M
Hz)X2 is approximately 148 nS. This value is not a value that can be easily achieved for a semiconductor memory using dynamic memory cells, and even if it could be achieved, there is a problem that the manufacturing cost would be extremely high.

(Problems to be Solved by the Invention) As described above, when trying to operate a conventional memory at high speed, the cycle time becomes extremely high, and there is a problem in that it is difficult to achieve this easily.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor memory that can reduce cycle time and easily realize high-speed operation.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory of the present invention includes n dynamic memory blocks, n data latch circuits connected to the outputs of each of the memory blocks, and the semiconductor memory described above. and an n-bit data shift circuit connected to the output of the data latch circuit, the n-bit data shift circuit is configured to shift the n-bit data read from the memory block to the n-bit data when a predetermined combination of row address and column address is supplied. transfer the n-bit data to the data shift circuit via each data latch circuit, and serially output these n bits of data from the data shift circuit;
The n-bit data read from the memory block is latched by each of the n data latch circuits by changing only the column address, and after the output of the n-bit data from the data shift circuit is completed, the n-bit data is latched by the data latch circuit in advance. The present invention is characterized in that the n-bit data thus obtained is transferred to the data shift circuit.

(Function) In the semiconductor memory of the present invention, first, when a predetermined combination of row address and column address is supplied, n-bit data read from a memory block is passed through n data latch circuits to the above-mentioned data. Transfer to data shift circuit. Next, these n bits of data are serially outputted from the data shift circuit. Then, while data is being output from the data shift circuit, n-bit data is read from the memory block by changing only the column address, and the n-bit data is once latched by each of the n data latch circuits. After the data output from the data shift circuit is completed, the n-bit data latched in advance by the data latch circuit is transferred to the data shift draw path, and after this, these n-bit data are serially transmitted from the data shift circuit again. Output.

In the conventional memory, two memory cycles were required to obtain two times of n-bit serial output data, but in the memory of the present invention, this can be achieved in one memory cycle.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a semiconductor memory of the present invention. In the figure, MB1 to MB
n is a dynamic memory cell array MAL~M
Each of A n is a dynamic memory block consisting of sense amplifiers SAI to SAn and column decoders CD1=CDn, respectively, and RD is a row decoder provided in common to these n memory blocks MBI to MBn. The n-bit data read from these n memory blocks MBI-MBn is supplied to shift registers 5ORI-5ORn via n data latch circuits OLI-OLn.

Next, the operation of the memory having the above configuration will be explained using the timing chart of FIG. First, when the chip enable signal CE is activated after one read address consisting of a combination of a predetermined row address and column address is given, n memory blocks M B l ” M
One bit of data is read out in parallel from each memory area corresponding to the input address of Bn. During the period when the chip enable signal τ lower is activated, the capture signal φL is set to H level, and the n memory blocks M
The n-bit data read from BI-MBn passes through n data latch circuits OL1-OLn as is and is supplied to shift registers 5ORI-5ORn.

Next, n bits of data are taken into n shift registers 5ORI to 5ORn in synchronization with the take-in signal φR, and then sequentially output as serial output data OUT in synchronization with the serial clock signal φout.

On the other hand, the next read address is given during the same chip enable activation period in which the first read address was given. The way addresses are given at this time is to simply change the column address. In a memory using a dynamic memory cell array, this access method first provides a combination of row address and column address, and then sequentially accesses consecutive address areas by changing only the column address. This is the same as so-called page mode, static column mode, fast page mode, etc.

When the next read address is given, one bit of data is read in parallel from each of the n memory blocks MBI to MBn from the memory area corresponding to the input address in the same manner as described above. Next, at the timing when the take-in signal φL falls from the H level to the L level, n bits of data read from the n memory blocks MBI to MBn are latched by the n data latch circuits OLI to OLn. Then, in advance, shift registers 5OR1 to 5ORn
The previous n bits of data supplied to shift register 5
When the output from ORI~5ORn is finished, n
The n-bit data latched by the data latch circuits 0LI-OLn is taken into the n shift registers 5ORL-5ORn in synchronization with the take-in signal φR, and then serially output again in synchronization with the serial clock signal φout. The data are sequentially output as data OUT.

In this way, in the memory of the above embodiment, n-bit data can be read twice in one memory cycle.

Therefore, the frequency of the serial clock signal φout for extracting serial output data from n shift registers 5OR1=SORn can be made higher than before, and high-speed operation can be easily achieved without shortening the cycle time of the memory cycle. It can be realized.

FIG. 3 shows the memory of the embodiment shown in FIG. 1 having an 8-bit output, and further includes eight shift registers 5IRI to 5IR8 and eight input registers ILL to I for data input.
A block diagram showing the configuration of an applied example of the present invention in which L8 and data input/output switching circuits 10S1 to 1058 are added to enable double-speed reading as in the case of the conventional memory shown in FIG. 8. It is.

The operation of this memory will be explained using the timing chart shown in FIG.

First, serial manual data IN for writing is signal φi
Eight shift registers 5IR1-8IR8 in synchronization with n
are sequentially transferred to When the transfer of 8 bits is completed, the capture signal φW is activated and the contents of the 8 shift registers 5IRI to 5IR8 are transferred to the input registers ILI to ILI.
Incorporated into L8. And these input registers IL
Data in L~ILs is data input/output switching circuit l03I
8 memory blocks MBI~MB via ~1038
During the subsequent write cycle period of the chip enable signal CE, the write address is written into the memory area corresponding to the write address supplied from the outside.

On the other hand, during the read cycle period of the chip enable signal CE, reading of 8-bit data is performed twice in succession in one memory cycle, as in the timing chart of FIG.

Now, when reading at double speed as shown in FIG. 4, the frequency of the serial clock signal φIn is 13.5.
Assuming that the frequencies of MHz and φout are 27 MHz, the cycle time of conventional memory is approximately 148 nS.
On the other hand, the cycle time tMCR in the read cycle is the period of 4.5 signals φ1n, so it is approximately 333 nS at (1/13.5 MHz) x 4.5.
Furthermore, the cycle time tMCW in the write cycle is a period of 3.5 times of the signal φIn, so it is approximately 259 nS (1/13.5 MHz) x 3.5. In this way, the memory shown in Figure 3 can make the cycle time longer than before when reading and writing data, and adopts a memory block that uses dynamic memory cells that are slower and cheaper. be able to. Furthermore, if a memory block with a high-speed cycle time is employed, the frequencies of the serial clock signals φ1n and φout can be increased, so that high-speed operation can be realized in this case.

In this way, the above memory can reduce cycle time,
As a result, high-speed operation can be easily achieved.

FIG. 5 shows each data latch circuit O used in the memory of the embodiment shown in FIG. 1 or the memory of the application example shown in FIG.
FIG. 2 is a circuit diagram showing an example of a specific configuration of L. FIG. This data latch circuit is provided at the front stage of an R/S type flip-flop F1 consisting of two NAND gates G1 and G2, and receives read data from the memory block MB and the signal φL. NAND
It is composed of a gate G3 and a NAND gate G4, which is provided before the flip-flop F, and to which the read data from the memory block MB is directly inputted via the inverter INV, and the signal φL is directly inputted thereto.

In the data latch circuit having such a configuration, the signal φL
When the signal φL is set to H level, the input data is output as is, and when the signal φL falls from the H level to the L level, the data that has been input until now is held by the flip-flop F.

Note that various other configurations can be used as the data latch circuit OL.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory that can reduce cycle time and easily realize high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the memory of the above embodiment, and FIG. 3 is a block diagram showing the structure of a memory according to an application example of the present invention. 4 is a timing chart showing the operation of the memory shown in FIG. 3, and FIG. 5 is a concrete diagram of some circuits used in the embodiment shown in FIG. 1 or the memory of the application example shown in FIG. 3, respectively. Circuit diagram showing the configuration, No. 6
The figure is a block diagram of a conventional memory, FIG. 7 is a timing chart showing the operation of the conventional memory of FIG. 6, FIG. 8 is a block diagram of a conventional memory, and FIG. 9 is a timing chart showing the operation of the conventional memory of FIG. FIG. MB...Dynamic memory block, MA...
Memory cell array, SA... sense amplifier, CD...
・Column decoder, RD...Row decoder, SOR・
...Shift register, OL...Data latch circuit, S
IR...shift register, IL...input register,
IO8...Data input/output switching circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] It is equipped with n dynamic memory blocks, n data latch circuits connected to the outputs of the respective memory blocks, and n-bit data shift circuits connected to the outputs of the data latch circuits. When a combination of a row address and a column address is supplied, n-bit data read from the memory block is transferred to the data shift circuit via each of the n data latch circuits, and these data are transferred from the data shift circuit to the data shift circuit. The n-bit data is serially output, and the n-bit data read from the memory block is latched by each of the n data latch circuits by changing only the column address, and the n-bit data from the data shift circuit is 1. A semiconductor memory characterized in that, after output is completed, n-bit data latched in advance by a data latch circuit is transferred to the data shift circuit.