JPH01171262A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH01171262A
JPH01171262A JP33181287A JP33181287A JPH01171262A JP H01171262 A JPH01171262 A JP H01171262A JP 33181287 A JP33181287 A JP 33181287A JP 33181287 A JP33181287 A JP 33181287A JP H01171262 A JPH01171262 A JP H01171262A
Authority
JP
Japan
Prior art keywords
chip
region
type
diode
junction diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33181287A
Other languages
Japanese (ja)
Other versions
JPH0834287B2 (en
Inventor
Takahiro Koyama
小山 隆弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62331812A priority Critical patent/JPH0834287B2/en
Publication of JPH01171262A publication Critical patent/JPH01171262A/en
Publication of JPH0834287B2 publication Critical patent/JPH0834287B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To utilize the area of a chip effectively, and to improve the function of a protective diode by forming a P-N junction diode by using a beltlike region shaped, circulating the periphery of the chip. CONSTITUTION:Elements including bipolar-transistors are integrated to a chip 4 in which an N-type semiconductor layer is formed onto a P-type semiconductor substrate 8. A P-N junction diode as a protective element is shaped, circulating the periphery of the chip 4. The diode is formed by an N-type beltlike region 5 partitioned by insulating regions 6 (P<+> isolation regions) and P-type regions 3-1... selectively shaped into the beltlike region 5. Accordingly, since the beltlike region is formed while the P-N junction diode is surrounded on the peripheral section of the chip 4, wirings may be simplified, space can be utilized effectively, the areas of the P-type regions 3-1-3-7 are also taken in large values, and a semiconductor integrated circuit can be given capacity sufficient for a protective diode.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に関し、特にバイポーラ・ト
ランジスタを含み静電破壊及び逆バイアス保護手段を備
えた半導体集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a bipolar transistor and equipped with electrostatic damage and reverse bias protection means.

〔従来の技術〕[Conventional technology]

従来、この種の半導体集積回路において、最高電位パッ
ド(以下■ccパッドと呼ぶ)と他のパッドとの間に静
電破壊対策用保護素子としてP−N接合ダイオードが用
いられているが、このP−N接合ダイオードは、第3図
に示すように、絶縁領域(例えば6−5)で区画された
N型半導体層(例えば5−5)/Jに選択的にP型頭域
3を設けた構成になっていて、それぞれのP−N接合ダ
イオードは個別に絶縁領域で区画されていた。
Conventionally, in this type of semiconductor integrated circuit, a P-N junction diode has been used between the highest potential pad (hereinafter referred to as cc pad) and other pads as a protection element to prevent electrostatic damage. As shown in FIG. 3, the P-N junction diode has a P-type head region 3 selectively provided in an N-type semiconductor layer (for example, 5-5)/J divided by an insulating region (for example, 6-5). Each P-N junction diode was separated by an insulating region.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体集積回路は、それぞれ個別に絶縁
領域で区画されたP−N接合ダイオードを保護素子とし
て有しているので、チップサイズが大きい、若くは保護
能力が低いという欠点がある。
The above-mentioned conventional semiconductor integrated circuit has P-N junction diodes each individually partitioned by an insulating region as a protection element, and therefore has drawbacks such as a large chip size and a low protection ability when the circuit is young.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路は、第1導電型半導体基板上に
第2導電型半導体層を設けてなるチップにバイポーラ・
トラジスタを含む素子を集積してなり、前記チップの周
辺部に周回して設けられ絶縁領域で区画された第2導電
型の帯状領域と前記帯状領域に選択的に形成された第1
導電型領域とからなるP、N接合ダイオードを保護素子
として備えているというものである。
The semiconductor integrated circuit of the present invention includes a bipolar chip formed by providing a second conductivity type semiconductor layer on a first conductivity type semiconductor substrate.
A strip region of a second conductivity type which is formed by integrating elements including transistors and is provided around the periphery of the chip and partitioned by an insulating region, and a first strip region selectively formed in the strip region.
A P, N junction diode consisting of a conductivity type region is provided as a protection element.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図及び第2図はそれぞれ本発明の一実施例を示す平
面模式図及び断面図である。
FIG. 1 and FIG. 2 are a schematic plan view and a cross-sectional view, respectively, showing an embodiment of the present invention.

この実施例はP型半導体基板8上にN型半導体層を設け
てなるチップ4にバイポーラ・トラジスタ(図示せず)
を含む素子を集積してなり、チップ4の周辺部に周回し
て設けられ絶縁領域6(P+分離領域)で区画されたN
型の帯状領域5と帯状領域5に選択的に形成されたP型
領域3−1、・・・とからなるP−N接合ダイオードを
保護素子として備えているというものである。
In this embodiment, a bipolar transistor (not shown) is mounted on a chip 4 having an N-type semiconductor layer provided on a P-type semiconductor substrate 8.
It is formed by integrating elements including a
A P-N junction diode consisting of a mold strip region 5 and P-type regions 3-1, . . . selectively formed in the strip region 5 is provided as a protection element.

Vccパッド1−1はN+型領領域2接続され、パッド
1−2〜1−8はそれぞれP型領域3−1〜3−7に接
続されている。各P−N接合ダイオードの陰極はN型半
導体層5、N++埋込層9を共有している。P型領域3
−1〜3−87及びN“型領域2はそれぞれ縦型NPN
トランジスタのペース領域及びエミッタ領域と同一工程
で形成できる。
Vcc pad 1-1 is connected to N+ type region 2, and pads 1-2 to 1-8 are connected to P-type regions 3-1 to 3-7, respectively. The cathodes of each PN junction diode share the N-type semiconductor layer 5 and the N++ buried layer 9. P-type region 3
-1 to 3-87 and N" type region 2 are each vertical NPN
It can be formed in the same process as the pace region and emitter region of the transistor.

従来例のように、P−N接合ダイオードをそれぞれ別々
に絶縁せず、チップ周辺部に周回して帯状領域を設けで
あるので、配線も簡略で済み、スペースを有効に利用で
き、P型領域3−1〜3−7の面積も大きくとれ保護ダ
イオードとして十分な能力をもたせることができる。
Unlike the conventional example, each P-N junction diode is not insulated separately, but a band-shaped region is provided around the chip periphery, so wiring can be simplified, space can be used effectively, and the P-type region The area of 3-1 to 3-7 can also be increased, and they can have sufficient ability as protection diodes.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はチップの周辺部に周回して
設けた帯状領域を利用してP−N接合ダイオードを設け
ることにより、チップ面積の有効活用が企れ、保護ダイ
オードの機能向上が実現できるという効果がある。
As explained above, the present invention aims to effectively utilize the chip area and improve the function of the protection diode by providing a P-N junction diode using the band-shaped area provided around the periphery of the chip. There is an effect that it can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ本発明の一実施例を示す平
面模式図及び断面図、第3図は従来の例を示す平面模式
図である。 1−1・・・VCCバッド、1−2〜1−8・・・パッ
ド、2・・・N+型領領域3−1〜3−7・・・P型領
域、4・・・チップ、5・・・N型の帯状領域、5−1
〜5−7・・・N型半導体層、6.6−5.6−8・・
・絶縁領域、7−1〜7−8・・・配線、8・・・P型
半導体基板、9・・・N++埋込層、10・・・酸化シ
リコン膜。
1 and 2 are a schematic plan view and a sectional view showing an embodiment of the present invention, respectively, and FIG. 3 is a schematic plan view showing a conventional example. 1-1...VCC pad, 1-2 to 1-8...pad, 2...N+ type region 3-1 to 3-7...P type region, 4...chip, 5 ...N-type band-shaped region, 5-1
~5-7...N-type semiconductor layer, 6.6-5.6-8...
- Insulating region, 7-1 to 7-8... Wiring, 8... P-type semiconductor substrate, 9... N++ buried layer, 10... Silicon oxide film.

Claims (1)

【特許請求の範囲】[Claims]  第1導電型半導体基板上に第2導電型半導体層を設け
てなるチップにバイポーラ・トラジスタを含む素子を集
積してなり、前記チップの周辺部に周回して設けられ絶
縁領域で区画された第2導電型の帯状領域と前記帯状領
域に選択的に形成された第1導電型領域とからなるP−
N接合ダイオードを保護素子として備えていることを特
徴とする半導体集積回路。
A chip including a bipolar transistor is integrated into a chip including a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and a transistor including a bipolar transistor is provided around the periphery of the chip and partitioned by an insulating region. P-, which consists of a band-like region of second conductivity type and a region of first conductivity type selectively formed in the band-like region.
A semiconductor integrated circuit comprising an N-junction diode as a protection element.
JP62331812A 1987-12-25 1987-12-25 Semiconductor integrated circuit Expired - Fee Related JPH0834287B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62331812A JPH0834287B2 (en) 1987-12-25 1987-12-25 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62331812A JPH0834287B2 (en) 1987-12-25 1987-12-25 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH01171262A true JPH01171262A (en) 1989-07-06
JPH0834287B2 JPH0834287B2 (en) 1996-03-29

Family

ID=18247922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62331812A Expired - Fee Related JPH0834287B2 (en) 1987-12-25 1987-12-25 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0834287B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0434963A (en) * 1990-05-30 1992-02-05 Nec Ic Microcomput Syst Ltd Semiconductor device
US5212398A (en) * 1989-11-30 1993-05-18 Kabushiki Kaisha Toshiba BiMOS structure having a protective diode
JP2004266044A (en) * 2003-02-28 2004-09-24 Mitsumi Electric Co Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63310134A (en) * 1987-06-12 1988-12-19 Fujitsu Ltd Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63310134A (en) * 1987-06-12 1988-12-19 Fujitsu Ltd Semiconductor integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212398A (en) * 1989-11-30 1993-05-18 Kabushiki Kaisha Toshiba BiMOS structure having a protective diode
JPH0434963A (en) * 1990-05-30 1992-02-05 Nec Ic Microcomput Syst Ltd Semiconductor device
JP2004266044A (en) * 2003-02-28 2004-09-24 Mitsumi Electric Co Ltd Semiconductor device
JP4695823B2 (en) * 2003-02-28 2011-06-08 ミツミ電機株式会社 Semiconductor device

Also Published As

Publication number Publication date
JPH0834287B2 (en) 1996-03-29

Similar Documents

Publication Publication Date Title
US5646433A (en) Pad protection diode structure
US6369424B1 (en) Field effect transistor having high breakdown withstand capacity
US6013941A (en) Bipolar transistor with collector surge voltage protection
JPH01171262A (en) Semiconductor integrated circuit
JP3133524B2 (en) Vertical PNP transistor
JP2978507B2 (en) Semiconductor storage device
JP2501556B2 (en) Optical sensor and manufacturing method thereof
JPS63301555A (en) Semiconductor device
JPH0434963A (en) Semiconductor device
JP3038896B2 (en) Semiconductor device
JPH0555481A (en) Manufacture of semiconductor device
JPH0711474Y2 (en) Semiconductor device
JP2603410Y2 (en) Integrated circuit
JPH10223846A (en) I/o protective circuit
JP2001223277A (en) I/o protective circuit
JPS60113961A (en) Semiconductor integrated circuit device
JPS60254651A (en) Input protection circuit for cmos circuit
JP2509485Y2 (en) Semiconductor integrated circuit
JP3275535B2 (en) Semiconductor device
JPH0525233Y2 (en)
JPH05326568A (en) Compound semiconductor integrated circuit
JPS62165354A (en) Semiconductor integrated circuit device
KR950034757A (en) Semiconductor integrated circuit
JPS6113956U (en) Zener diode incorporated into integrated circuit
JPH0475660B2 (en)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees