JPH01169943A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To form a fuse for redunducy concerning the redundancy design of a DRAM cell, by installing said fuse on a field insulating film, and using the same material as a conductor film to form a gate electrode. CONSTITUTION:A transferring transistor T1 is installed, which is composed of a pair of impurity diffusion layers 23, 24, and gate electrodes WL3, WL4 formed in a region defined by a field insulating film 22. On the upper part of the transistor is formed a storage capacitance C1 composed of a storage electrode 26, a dielectric film 27 and facing electrodes 28. On a field insulating film 22 is installed a fuse 30 which is formed of the same layer conductor film as a conductor film forming the gate electrodes WL3, WL4, and used for constituting a redundant circuit. The fuse 30 is connected electrically to a metal wiring 31.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a structure of a redundant fuse in a redundant design of a semiconductor memory device, particularly a highly integrated, high-performance dynamic random access memory (DRAM), and The purpose is to improve the connection with external metal wiring, ensure redundant switching operation, form the redundant fuse in a process simultaneously with each electrode of the DRAM cell, and improve the production yield. A transfer transistor including a pair of impurity diffusion layers and a gate electrode formed in a region defined by a field vIA edge film, and a storage capacitor including a storage electrode, a dielectric film, and a counter electrode formed above the transfer transistor. In the semiconductor memory device, a redundant circuit configuration fuse is provided on the field insulating film and is formed of a conductive film of the same layer as the conductive film forming the gate electrode, and the fuse is connected to the metal wiring and the electrical conductor film. It consists of the fact that it is connected to the

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly, to a redundant fuse structure related to a redundant design of a highly integrated, high-performance dynamic random access memory (DRAM) cell.

[Conventional technology]

2 and 3 are explanatory diagrams of a semiconductor memory device according to a conventional example, and FIG. 2 shows an explanatory diagram of a DRAM cell according to a conventional example.

FIG. 2(a) is an electrical circuit diagram of a DRAM cell.

In the figure, T is a transfer transistor composed of a MOS transistor or the like that transfers data (charge), C is a storage capacitor that accumulates charge, WL is a word line, and BL is a bit line.

FIG. 2B is a cross-sectional view showing the DRAM cell structure. In the figure, 1 is a Si substrate such as a p-type epitaxial layer, 2 is
is the field oxidation v(
3.4 is an impurity diffusion layer formed by diffusing As'' ions, etc., and is the source or drain of the transfer transistor T. 5 is the gate electrode WL, WL, etc.
It is an insulating film that insulates L, and is a CVD oxide film (SiN4
, or Si0glI2).

Reference numeral 6 denotes an electrode formed by doping a poly-Si film with impurity ions, and is a storage electrode constituting a storage capacitor C. 7
is a dielectric film formed of an insulating film such as a SrO2 film or a SiN film. Reference numeral 8 denotes an electrode formed by doping impurity ions into a poly-Si film, and is a counter electrode constituting the storage capacitor C. 9 is an insulating film that insulates the counter electrode 8, and is a PSG film or the like.

Note that WL and WL are gate electrodes of the transfer transistor T formed of a poly-Si film or the like, and WL and WL2' are word lines formed of aluminum wiring or its alloy wiring. Also, the word lines WL,' and WL4
' is electrically connected to the gate electrode WL and WL. Further, BL is a bit line formed of a poly-Si film or a polycide film doped with impurity ions.

FIG. 3 is a time to explain problems related to the conventional example, and FIG. 3(a) shows an explanatory diagram related to redundant design.

In the figure, 10 is a memory cell array, 11 is a redundant memory cell, 12 is a row decoder, 13 is a column decoder,
14 is a clock generator, 15 is a sense amplifier, 16 is a row address (row), 17 is a column address (column), 18
is a level converter.

Note that R/W is read/write switching data, Din is data input, and Do and Do are non-inverted output data and inverted output data. Further, Cs and Cs are a non-inverted clock and an inverted clock, and V ref is a reference potential.

Further, a shaded area 19 in FIG. 2A is a defective memory cell that has occurred in the memory cell array 10 due to some reason.

Here, it is necessary to replace the defective memory cell 19 with the redundant memory cell 11. Further, a timing signal for redundancy switching and an element for fixing the memory cell array 10 after replacing the defective memory cell 19 with a redundant memory cell are required, and a polysilicon fuse is used for this.

FIG. 4B shows a redundant switching circuit diagram. In the figure, F is a fuse for redundant circuit configuration, and is formed of a polysilicon fuse. In addition, Q and -Q are transistors for redundant switching, Vcc and v$3 are power supply voltages,
Ai is a non-inverted address, At is an inverted address, N1 to N
, is the control line.

Note that, based on the address information of the defective memory cell 19, the fuse F1 is blown by an electrical method or the like. As a result, the address information At and Ai are inverted, and the defective memory cell 19 is replaced with the redundant memory cell 11.

[Problems to be Solved by the Invention] According to conventional examples, as the degree of integration of semiconductor memory devices increases and semiconductor memory elements become smaller, the area of a DRAM cell becomes smaller and smaller.

Therefore, the following problems arise in the redundant design of DRAM cells.

(2) When a redundant fuse is formed in a film above the gate electrode, etching of the contact hole between the metal wiring and the underlying conductive film continues until the bottom film is exposed. As a result, the contact characteristics between the aluminum wiring and the fuse deteriorate due to a reduction in film thickness due to over-etching of the contact hole between the redundant fuse and the metal wiring, and when the fuse is subsequently blown by electrical means, for example, incomplete contact may occur. Electrical interruption makes the redundant switching operation unstable. Therefore, the production yield of DRAM cells decreases due to an increase in the number of defective elements.

(2) If the material of the redundant fuse and the material of each electrode of the DRAM cell are made of different materials, the number of resists will increase and the manufacturing process will become complicated.

The present invention was created in view of the problems of the conventional example, and improves the connection between the redundant fuse and external wiring to ensure redundant switching operation, and connects the redundant fuse to D.
An object of the present invention is to provide a semiconductor memory device that can be formed in a process simultaneously with each electrode of a RAM cell, thereby improving its production yield.

[Means for solving problems]

As shown in FIG. 1, an embodiment of the semiconductor memory device of the present invention includes a pair of impurity diffusion layers 23 and 24 formed in a region defined by a field insulating film 22, and gate electrodes W L z , W. In a semiconductor memory device comprising a transfer transistor T consisting of La, and a storage capacitor C4 formed above it consisting of a storage electrode 26, a dielectric film 27 and a counter electrode 28, on the field insulating film 22, The gate electrode WL3
, a redundant circuit configuration fuse 30 formed of a conductive film of the same layer as the conductive film forming WL4 is provided, and the fuse 30 is electrically connected to a metal wiring 31, Achieve the above objectives.

[Effect]

According to the present invention, the redundant fuse is provided on the field insulating film and made of the same material as the conductive film forming the gate electrode. Therefore, by combining a redundant fuse pattern with a resist mask pattern for forming a gate electrode, it is possible to simultaneously form a redundant fuse using a conductive film such as a polycrystalline semiconductor film containing impurities.

Further, according to the present invention, the lowest layer poly-Si is used as the fuse.
Since a film is used, it is possible to minimize over-etching when forming contact holes with metal wiring, and as a result, good contact characteristics can be achieved.

Therefore, when a fuse is blown by the heat generated by applying a voltage from the outside and flowing a current, the voltage drop outside the fuse part can be sufficiently reduced, and the generated heat can be concentrated in the fuse part, causing it to blow. It becomes possible to complete.

This makes it possible to improve the reliability and stability of the redundant switching operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a structural diagram of a semiconductor memory device according to an embodiment of the present invention, showing a cross-sectional view of a DRAM cell and a redundant fuse.

In the figure, 21 is a p-type Si substrate or a p-type epitaxial layer for forming, for example, an n-channel MOS transistor. 22 selects P type Si substrate 21 etc. LOC
This is a field oxide film formed by the O3 method or the like, and defines the formation region of the transfer transistor T, etc.

23.24 is a p-type Sii plate 21 by ion implantation etc.
This is an n0 impurity diffusion layer formed by selectively implanting impurities such as A s ions into the transfer transistors T,
source or drain of

30 is a redundant fuse, and gate electrode WL3,
A conductor film such as a poly-Si film containing impurity ions forming the WL is formed simultaneously by patterning using the same resist film as a mask. 25 is an insulating film that insulates the gate electrodes WL3, WL and the redundant fuse 30, and is formed by a normal pressure CVD method or the like.
or 5iNn film.

Further, 26 is an electrode formed of a conductive film such as a poly-Si film doped with impurity ions, and is a storage electrode constituting the storage capacitor C1. Reference numeral 27 denotes a dielectric film formed of an insulating film such as SiO□ or 5iNa film, which is obtained by thermally oxidizing the storage electrode 26 in a nitrogen or oxygen atmosphere.

Reference numeral 28 denotes an electrode formed of a conductive film such as poly 5ijp1 doped with impurity ions, and is a counter electrode that constitutes the storage electrode C3 together with the storage electrode 26 and the dielectric film 27. 29 is an insulating film that insulates the counter electrode 28, and PS
It is formed from a G film or the like.

Reference numeral 31 denotes an A2 wiring that connects the redundant fuse 30 and the word line WL,' or WL,' of the transfer transistor TI.

Note that WL and WL are the gate electrodes of the transfer transistor T formed of a conductive film such as a poly-Si film doped with impurity ions, and WL,' and WL,' are aluminum interconnects or their alloys. This is a word line formed by wiring. In addition, word lines WL, l and WL,' are gate electrodes W
It is electrically connected to L and WL. The contact hole is opened by anisotropic etching such as RIE using the PSG film 29 as a resist mask.

Further, a contact hole for electrically connecting the redundant fuse 30 and the aluminum wiring 31 is also opened by anisotropic etching such as the RIB method using the same resist as a mask.

Note that BL is a bit line formed of a conductive film such as a poly-Si film doped with impurity ions or a polycide film.

These constitute a semiconductor memory device.

In this way, the redundant fuse 3o is provided on the field insulating film 22 and made of the same material as the semiconductor film forming the gate electrodes WL3, wL4. For this reason,
By merging a redundant fuse pattern with the resist mask pattern forming the gate electrodes WL's and WL4, the redundant fuse 30 can be simultaneously formed using a conductive film such as a poly-Si film containing impurity ions. It becomes possible.

Further, according to this embodiment, the depth of the contact hole that connects the redundant fuse 3° and the aluminum wiring 31 is the same as that of the gate electrode WL3 or WL4 and the word line WL of the DRAM cell.
Since it is formed to the same depth as the contact hole connecting s', WL,', it is possible to prevent the reduction of the film due to over-etching, and to obtain sufficient contact between the redundant fuse 3o and the aluminum wiring fI31. As a result, contact characteristics are improved.

Therefore, when a voltage is applied to the redundant fuse 30 from the outside to flow a current, and when it blows due to the heat generated at that time, it is possible to prevent a voltage drop in parts other than the fuse. Heat can be generated and complete electrical isolation characteristics can be obtained.

This makes it possible to improve the reliability and stability of the redundant switching operation.

〔Effect of the invention〕

As described above, according to the present invention, a redundant fuse related to a redundant design of a DRAM cell can be formed at the same time as the gate electrode of a transfer transistor, and good contact with external metal wiring can be obtained. Therefore, it is possible to stabilize the fusing characteristics of the redundant fuse and stabilize the production yield.

This makes it possible to manufacture semiconductor devices such as DRAM cells that are increasingly fine, highly integrated, and have high performance.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a DRAM cell according to a conventional example, and FIG. 3 is a diagram illustrating problems associated with the conventional example. (Explanation of symbols) T, T+...transfer transistor, C, C,...
...Storage capacitance, 1.21...Si substrate, 2.22...Field oxide film (field insulating film)
, 3.23...Drain (impurity diffusion layer), 4.24.
...Source (impurity diffusion N), 5.25...340g
Film (insulating film), 6.26...Storage electrode, 7.27...Dielectric film, 8.28...Counter electrode, 9.29...PSC film (insulating film), F3, 30 ... Redundant fuse (fuse for redundant circuit configuration), 31... Aluminum wiring (metal wiring), 10... Memory cell array, 11... Redundant memory cell, 12... Row decoder, 13 ...Column decoder, 14...Clock generation section, 15...Sense amplifier, 16...Row address (row), 17...Column address (column), 18...Level converter, R/ W...Read/write switching data, Din.
...Data input, Do, Do...Non-inverted data output 2-inverted data output, Cs, Cs...Non-inverted clock, inverted clock, Ai
, Ai...non-inverted address, inverted address, N1 to N
,...signal line, Vcc, Vss...power supply voltage, WL, ~WL,
...Gate electrode (conductor layer), WL,'~WL,'・
...word line, BL...bit line, Q1-Q7...-transistor.

Claims (1)

[Claims] A transfer transistor (T_1) consisting of a pair of impurity diffusion layers (23, 24) and gate electrodes (WL_3, WL_4) formed in a region defined by a field insulating film (22); Storage electrode (26) formed on top
, a storage capacitor (C_1) consisting of a dielectric film (27) and a counter electrode (28), wherein the gate electrode (C_1) is provided on the field insulating film (22).
Fuses for redundant circuit configuration (3
0), and the fuse (30) is electrically connected to a metal wiring (31).