JPH01169944A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To form a fuse for redunducy at the same time with a storage electrode, by installing said fuse on an insulating film to insulate a gate electrode on a field insulating film, and using the same material as a conductor film to form a storage electrode. CONSTITUTION:A transferring transistor T1 is installed which is composed of a pair of impurity diffusion layers 23, 24, and gate electrodes WL3, WL4 formed in a region defined by a field insulating film 22. On the upper part of the transistor is formed a storage capacitance C1 composed of a storage electrode 26, a dielectric film 27 and facing electrodes 28. On an insulating film 25 to insulate the gate electrodes WL3, WL4, is installed a fuse 30 for redundancy which is composed of the same layer conductor film as a conductor film to form the storage electrode 26. Further the fuse 30 for redundancy is connected electrically to a metal wiring 31.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a structure of a redundant fuse in a redundant design of a semiconductor memory device, particularly a highly integrated, high-performance dynamic random access memory (DRAM), and The purpose is to improve the connection with external metal wiring, ensure redundant switching operation, form the redundant fuse in a process simultaneously with each electrode of the DRAM cell, and improve the production yield. A transfer transistor including a pair of impurity diffusion layers and a gate electrode formed in a region defined by a field insulating film, and an M-volume capacitor including a storage electrode, a dielectric film, and a counter electrode formed above the transfer transistor. In the semiconductor memory device, a fuse for a redundant circuit configuration is provided on an insulating film that insulates the gate electrode, and is formed of a conductive film of the same layer as a conductive film forming the storage electrode, and the redundant circuit The configuration includes a configuration fuse electrically connected to metal wiring.

[Industrial Application Field] The present invention relates to a semiconductor memory device, and more specifically, to a structure of a redundant fuse in a redundant design of a highly integrated, high-performance dynamic random access memory (DRAM) cell. It is.

[Conventional technology]

2.3 is an explanatory diagram of a semiconductor memory device according to a conventional example, and FIG. 2 is an explanatory diagram of a DRAM cell according to a conventional example.

Figure (a) shows an electrical circuit of a DRAM cell.

In the figure, T is a transfer transistor composed of a MOS transistor or the like that transfers data (charge), C is a storage capacitor that accumulates charge, WL is a word line, and BL is a bit line.

FIG. 2B is a cross-sectional view showing the DRAM cell structure. In the figure, 1 is a Si substrate such as a p-type epitaxial layer, 2 is
is a field oxide film (
3.4 is an impurity diffusion layer formed by diffusing As'' ions, etc., and is the source or drain of the transfer transistor T.

5 is an insulating film that insulates the gate electrodes WL and WL;
A CVD oxide film (SiNa, SiO, WX), etc. is used. Reference numeral 6 denotes an electrode formed by doping a poly-Si film with impurity ions, and is a storage electrode constituting a storage capacitor C. 7 is a dielectric film formed of an insulating film such as a Si0g film or a 5iNa film. 8 is an electrode formed by doping poly 5iljJ with impurity ions, and the storage capacitance C
This is the counter electrode that constitutes the. 9 is an insulating film that insulates the counter electrode 8, and is a PSG film or the like.

Note that WL and WLt are the gate electrodes of the transfer transistor T formed of a polycide film, and WL +
', WL, ' are word lines formed by aluminum wiring or aluminum wiring. Furthermore, the word lines WL,' and WL,' are electrically connected to the gate electrodes W L + and WL2. Further, BL is a bit line formed of a poly-Si film or a polycide film doped with impurity ions.

FIG. 3 is a diagram illustrating problems related to the conventional example, and FIG. 3(a) shows an explanatory diagram related to redundant design.

In the figure, 10 is a memory cell array, 11 is a redundant memory cell, 12 is a row decoder, 13 is a column decoder,
14 is a clock generator, 15 is a sense amplifier, 16 is a row address (row), 17 is a column address (column), 18
is a level converter.

Note that R/W is read/write switching data, Din is data input, and Do and Do are non-inverted output data and inverted output data. Further, Cs and Cs are a non-inverted clock and an inverted clock, and V r*f is a reference potential.

Further, a shaded area 19 in FIG. 2A is a defective memory cell that has occurred in the memory cell array 10 due to some reason.

Here, it is necessary to replace the defective memory cell 19 with the redundant memory cell 11. Further, a timing signal for redundancy switching and an element for fixing the memory cell array IO after replacing the defective memory cell 19 with a redundant memory cell are required, and a polysilicon fuse is used for this.

FIG. 4B shows a redundant switching circuit diagram. In the figure, Fl is a fuse for redundant circuit configuration, and is formed of a polysilicon fuse. In addition, Q1 to Q are redundant switching transistors, vCCr VS2 is a power supply voltage, Ai is a non-inverted address, Ai is an inverted address, and N1
~N3 is a control line.

Note that, depending on the address information of the defective memory cell 19, the fuse F1 is blown by a laser beam or the like. As a result, the address information Ai and A+ are inverted, and the defective memory cell 19 is replaced with the redundant memory cell 11.

[Problems to be Solved by the Invention] According to the conventional example, as the degree of integration of semiconductor memory devices increases and semiconductor memory elements become smaller, the area of a DRAM cell becomes smaller and smaller.

Therefore, the following problems arise in the redundant design of DRAM cells.

■The formation position of the redundant fuse, the reduction of the film due to over-etching when forming the contact hole, and the contact characteristics between the aluminum wiring and the fuse deteriorate, resulting in incomplete fuse blowing when the fuse is blown by electrical methods, etc. Electrical interruption makes the redundant switching operation unstable. Therefore, the production yield of DRAM cells decreases.

(2) If the material of the redundant fuse and the material of each electrode of the DRAM cell are made of different materials, the number of resists will increase and the manufacturing process will become complicated.

The present invention was created in view of the problems of the conventional example, and improves the connection between the redundant fuse and external wiring to ensure redundant switching operation, and connects the redundant fuse to D.
An object of the present invention is to provide a semiconductor memory device that can be formed in a process simultaneously with each electrode of a RAM cell, thereby improving its production yield.

[Means for solving problems]

As shown in FIG. 1, an embodiment of the semiconductor memory device of the present invention includes a pair of impurity diffusions N23 and N24 formed in a region defined by a field insulating film 22, and gate electrodes WL, , WL. a transfer transistor T1 consisting of;
In a semiconductor memory device comprising a storage capacitor C1 formed on the storage electrode 26, a dielectric film 27, and a counter electrode 28, an insulating film 25 insulating the gate electrodes WL3 and WL.
A redundant fuse 30 made of a conductive film forming the storage electrode 26 is provided above the storage electrode 26, and the redundant fuse 30 is electrically connected to the metal wiring 31. Achieve your purpose.

[Effect]

According to the present invention, the redundant fuse is provided on the insulating film that insulates the gate electrode on the field insulating film and is made of the same material as the conductive film forming the storage electrode.

Therefore, by combining a redundant fuse pattern with a resist mask pattern forming a storage electrode, it is possible to simultaneously form a redundant fuse using a conductive film such as a polycrystalline semiconductor film containing impurities.

Furthermore, according to the present invention, since the lowest layer polycrystalline semiconductor film is used as the redundant fuse, overetching when forming a contact hole connecting the metal wiring and the redundant fuse can be minimized. It becomes possible to
As a result, sufficient contact characteristics can be achieved.

This allows voltage to be applied externally to the redundant fuse,
When a redundant fuse is cut by the heat generated by the current flowing at that time, the voltage drop outside the fuse part can be sufficiently reduced, the generated heat can be concentrated in the fuse part, and the fuse can be completely blown out. becomes possible.

This makes it possible to improve the reliability and stability of the redundant switching operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a structural diagram of a semiconductor memory device according to an embodiment of the present invention, showing a cross-sectional view of a DRAM cell and a redundant fuse.

In the figure, 21 is a p-type St substrate or a p-type epitaxial layer for forming, for example, an n-channel MOS transistor. Reference numeral 22 denotes a field oxide film formed on a p-type Si substrate 2I or the like by selective LOCOS method or the like, and defines the formation region of the transfer transistor T1.

23.24 is a p-type Si substrate 21 by ion implantation etc.
This is an n' impurity diffusion layer formed by selectively implanting impurities such as As'' ions into the transfer transistor T, and is the source or drain of the transfer transistor T.

25 is an insulating film for insulating the gate electrodes WL, , WL and the redundant fuse 30, and is a SiO□ or SiN4 film formed by atmospheric pressure CVD or the like.

Further, 26 is an electrode formed of a conductive film such as a poly-Si film doped with impurity ions, and is a storage electrode constituting the storage capacitor C1. Reference numeral 27 denotes a dielectric film formed of an insulating film such as a 5iO1 or 5iNa film obtained by thermally oxidizing the storage electrode 26 in a nitrogen or oxygen atmosphere.

30 is a redundant fuse, which is made of poly 5iII! containing impurity ions forming the storage electrode 26. Conductor films such as J are formed simultaneously by patterning using the same resist film as a mask.

Note that 30a is StO□ formed at the same time as the conductor film 26.
It is a membrane.

Reference numeral 28 denotes an electrode formed of a conductive film such as a poly-Si film doped with impurity ions, and is a counter electrode that constitutes the storage electrode CI together with the storage electrode 26 and the dielectric film 27.

An insulating film 29 insulates the counter electrode 28 and the redundant fuse 30, and is formed of a PSG film or the like.

31 is an AI connected to the redundant fuse 30 and the word line WLs' or WL,' of the transfer transistor T1, etc.
This is l wiring.

Note that WL and WLa are the gate electrodes of the transfer transistor T1 formed of a conductive film such as a polycide film doped with impurity ions, and WL3' and WL,' are gate electrodes of the transfer transistor T1 formed of a conductive film such as a polycide film doped with impurity ions, and WL3' and WL,' are formed of aluminum wiring or its alloy wiring. This is a word line formed. Further, word lines WL,' and WL,' are gate electrodes WL, and WL.

electrically connected to. The contact hole was made by RIE using PSGIIW29 as a mask.
The openings are made by anisotropic etching such as the method. Further, the contact hole for electrically connecting the redundant fuse 30 and the aluminum wiring 31 was also made using the same resist as a mask.
The opening is made by anisotropic etching such as the E method.

Note that BL is a focus line formed by a conductive film such as a poly-Si film doped with impurity ions or a polycide film.

These constitute a semiconductor memory device.

In this way, the redundant fuse 30 is placed on the SiQ□ff125 that insulates the gate electrodes W L s and W La on the field oxide film 22, and the stored electric current t! 1x
The conductor film 26 is made of the same material as the conductor film forming the conductor film 26.

Therefore, by merging a redundant fuse pattern with the resist mask pattern forming the storage electrode 26, it is possible to simultaneously form the redundant fuse 30 using a conductive film such as a poly-Si film containing impurities. Become.

Further, according to the present invention, since the lowest layer poly-Si film is used as the redundant fuse 30, over-etching when forming a contact hole connecting the AI wiring 31 and the redundant fuse 30 can be minimized. As a result, sufficient contact characteristics can be achieved.

As a result, when a voltage is applied to the redundant fuse 30 from the outside and the redundant fuse 30 is cut by the heat generated by the current flowing at that time, the voltage drop at parts other than the fuse 30 can be sufficiently reduced. The generated heat can be concentrated in the 30 parts of the fuse, making it possible to complete the blowout.

This makes it possible to improve the reliability and stability of the redundant switching operation.

〔Effect of the invention〕

As described above, according to the present invention, a fuse for a redundant circuit configuration related to a redundant design of a DRAM cell can be formed at the same time as the gate electrode of a transfer transistor, and good contact with external metal wiring can be obtained.

Therefore, it is possible to stabilize the fusing characteristics of the fuse for the redundant circuit configuration and stabilize the production yield.

This makes it possible to manufacture a semiconductor memory device such as a DRAM cell with a highly reliable redundant switching operation, a highly stable redundant design, and an ultra-fine, highly integrated, high-performance DRAM cell.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a DRAM cell according to a conventional example, and FIG. 3 is a diagram illustrating problems associated with the conventional example. (Explanation of symbols) T, TI...Transfer transistor, C, C,...Storage capacitor, 1.21...St substrate, 2.22...Field oxide film (field insulating film)
, 3.23...Drain (impurity diffusion layer), 4.24.
... Source (impurity diffusion layer), 5, 25. 30 a
-5iOt film (insulating film), 6.26...Storage electrode (conductor film), 7.27...Dielectric film, 8.28...Counter electrode, 9.29-PSGffl (insulating WX) ,F,,30...
- Redundant fuse (fuse for redundant circuit configuration), 31... Aluminum wiring (metal wiring), 10... Memory cell array, 11... Redundant memory cell, 12... Row decoder, 13...・Column decoder, 14... Clock generation section, 15... Sense amplifier, 16... Row address (row), 17... Column address (column), 18... Level converter, R/W.・Read/@write switching data, D3, ・
...Data input, Do, Do...Non-inverted data output, inverted data output, Cs, Cs...Non-inverted clock, inverted clock, W
L l-W L a...gate electrode, WL,'~WL
,'...word line, BL...bit line, Ai, Ai...non-inverted address, inverted address, N,
~N3...Signal line, V (e+ vss...Power supply voltage, Q1~Q,...Transistor. 17 Column address CFD (a) Diagram explaining problems related to the conventional example. Figure 3 (Part 1) ) Figure 3 (Part 2) explaining the problems related to the conventional example

Claims (1)

[Claims] A transfer transistor (T_1) consisting of a pair of impurity diffusion layers (23, 24) and gate electrodes (WL_3, WL_4) formed in a region defined by a field insulating film (22); Storage electrode (26) formed on top
, a storage capacitor (C_1) comprising a dielectric film (27) and a counter electrode (28), wherein the storage capacitor (C_1) is provided on an insulating film (25) that insulates the gate electrodes (WL_3, WL_4). A fuse (30) for redundant circuit configuration is provided, which is formed of a conductive film of the same layer as the conductive film forming the electrode (26), and the fuse (30) for redundant circuit configuration is connected to metal wiring (31). A semiconductor memory device characterized by being electrically connected to.