JPH01166539A - Method and apparatus for dry etching at low temperature - Google Patents
Method and apparatus for dry etching at low temperatureInfo
- Publication number
- JPH01166539A JPH01166539A JP32410387A JP32410387A JPH01166539A JP H01166539 A JPH01166539 A JP H01166539A JP 32410387 A JP32410387 A JP 32410387A JP 32410387 A JP32410387 A JP 32410387A JP H01166539 A JPH01166539 A JP H01166539A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- wiring layer
- wsi
- layer
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001312 dry etching Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229910016006 MoSi Inorganic materials 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims 2
- 229910052721 tungsten Inorganic materials 0.000 claims 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000007795 chemical reaction product Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910009257 Y—Si Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は低温ドライエツチング方法およびそれに用いる
エツチング装置に係り、特に材質の異なる２層からなる
配線層を高精度に異方性ドライエツチングするのに好適
な低温エツチング方法およびそれに用いる低温ドライエ
ツチング装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a low-temperature dry etching method and an etching apparatus used therein, and in particular, to anisotropic dry etching with high precision of a wiring layer consisting of two layers of different materials. The present invention relates to a low-temperature etching method suitable for use in, and a low-temperature dry etching device used therefor.
従来の２層膜のドライエツチング、たとえば。 Dry etching of conventional two-layer films, e.g.
ソリッド・ステート・テクノロジー、１９８４年、４月
号、２３５頁（Ｓｏｌｉｄ ５ｔａｔｅ Ｔｅｃｈｎｏ
ｌｏｇｙ／Ａｐｒｉｌ １９８４ ｐ２３５）に記載
されているようなＰｏｌｙ−Ｓｉ（ポリシリコン）上に
、ＷＳｉ（タングステンシリサイド）が形成されている
２層膜のドライエツチングにおいては、形状制御が非常
に難しい問題があった。特に、第２図に示したように下
層のＰｏｌｙ−Ｓｉがサイドエツチングを生じやすく、
逆テーパー状の形状になっていた。このサイドエツチン
グを防止するため、たとえばＣ２Ｆ６ＣＱ等の堆積膜を
生じやすいガスを添加していた。Solid State Technology, April 1984, page 235
In the dry etching of a two-layer film in which WSi (tungsten silicide) is formed on Poly-Si (polysilicon) as described in ``April 1984 p235'', shape control is extremely difficult. there were. In particular, as shown in Figure 2, the underlying Poly-Si layer is prone to side etching.
It had a reverse tapered shape. In order to prevent this side etching, a gas such as C2F6CQ which tends to form a deposited film is added.
上記従来技術は、堆積膜による汚染の問題について配慮
されておらず、ＬＳＩの信頼性や後処理等の点で問題が
あった。The above-mentioned conventional technology does not take into consideration the problem of contamination due to deposited films, and has problems in terms of LSI reliability, post-processing, and the like.
本発明の目的は、堆積膜による汚染の問題のない清浄な
２層配線構造のドライエツチング技術を提供するること
にある。SUMMARY OF THE INVENTION An object of the present invention is to provide a dry etching technique for a clean two-layer wiring structure without the problem of contamination due to deposited films.
上記目的は、第１の配線層をドライエツチングする時の
基板温度と第２の配線層をドライエツチングする時の基
板温度を異なるようにすることによって達成される。設
定すべき基板温度は第１層と第２層の配線材料によって
異なるが、たとえば第１層がＰｏｌｙ−Ｓｉ、第２層が
ＷＳｉのポリサイド配線を例にして以下に述べる。The above object is achieved by making the substrate temperature when dry etching the first wiring layer different from the substrate temperature when dry etching the second wiring layer. The substrate temperature to be set varies depending on the wiring materials of the first layer and the second layer, but will be described below using a polycide wiring in which the first layer is Poly-Si and the second layer is WSi.
フッ素系ガスを用いてエツチングした場合の試料温度と
Ｐｏｌｙ−５ｉおよびＷＳｉのサイドエツチング量の関
係を第３図に、エツチング速度との関係を第４図に示し
た。Ｐｏｌｙ−Ｓｉではある程度のエツチング速度で異
方性が得られる温度は、約−１１０〜−１５０℃の間で
あり、ＷＳｉの場合には、約−６０〜−１００℃の間で
ある。FIG. 3 shows the relationship between the sample temperature and the amount of side etching of Poly-5i and WSi when etching is performed using a fluorine gas, and FIG. 4 shows the relationship between the etching rate and the sample temperature. For Poly-Si, the temperature at which anisotropy can be obtained at a certain etching rate is between about -110 and -150°C, and for WSi, it is between about -60 and -100°C.
したがって、たとえば第２層のＷＳｉを一８０℃でドラ
イエツチングし、第１層のＰｏｌｙ−Ｓｉを一１３０℃
でドライエツチングすることによって、第１図に示すよ
うな異方性エツチングを達成することができる。Therefore, for example, the second layer of WSi is dry etched at -80°C, and the first layer of Poly-Si is dry etched at -130°C.
Anisotropic etching as shown in FIG. 1 can be achieved by dry etching.
上記の最適試料温度は、ガス圧力や、入力パワー等のエ
ツチング条件によって変化するが、いずれの場合も、Ｐ
ｏｌｙ−Ｓｉ工ツチング時の温度がＷＳｉエツチング時
の温度よりも低くすることにより良好な異方性が得られ
るということは同様である。The optimum sample temperature mentioned above varies depending on etching conditions such as gas pressure and input power, but in any case, P
Similarly, good anisotropy can be obtained by setting the temperature during oly-Si etching to be lower than the temperature during WSi etching.
上記作用は、Ｐｏｌｙ−ＳｉとＷＳｉのエツチング反応
生成物の蒸気圧の違いにもとづく。すなわち、Ｐｏｌｙ
−ＳｉおよびＷＳｊエツチング時の主反応生成物はそれ
ぞれＳ ｉ ＦａおよびＷ Ｅ ａであるが、５ｉＦａ
よりＷＦｅの方が蒸気圧が低い、そのため、Ｐｏｌｙ−
Ｓｉの方がＷＳｉより低い温度でエツチング側面の反応
が抑制され、異方性エツチングになる。The above action is based on the difference in vapor pressure between the etching reaction products of Poly-Si and WSi. That is, Poly
-The main reaction products during Si and WSj etching are SiFa and WEa, respectively, but 5iFa
WFe has a lower vapor pressure than Poly-
At a lower temperature than WSi, the reaction on the etching side surface is suppressed, resulting in anisotropic etching.
このように、第１の配線層の上に第２の配線層が形成さ
れている２層配線のドライエツチングにおいて、エツチ
ングガスと配線材料との反応生成物の蒸気圧が、第１層
より第２層において、低い場合に、第２層エツチング時
より第１Ｊｊ！Ｊエツチング時の基板温度を下げること
によって、第１層、第２層ともにサイドエツチングのな
い異方性エツチングが達成される。In this way, in dry etching of a two-layer wiring in which the second wiring layer is formed on the first wiring layer, the vapor pressure of the reaction product between the etching gas and the wiring material is lower than that of the first wiring layer. In the second layer, if it is low, the first Jj! By lowering the substrate temperature during J etching, anisotropic etching without side etching can be achieved for both the first and second layers.
以下１本発明の詳細な説明する。 The present invention will be explained in detail below.
［実施例］
Ｓｉ基板上に酸化シリコン層を形成し、その上にＰｏｌ
ｙ−Ｓｉを３００ｎｍ、ＷＳｉを３００ｎｍの順に形成
し、次いでエツチングマスクをパターニングした。その
後、ＳＦｇガスを用いて、ガス圧力８０ｍＴｏｒｒ、の
もとに平行平板型反応性プラズマエツチング装置によっ
て該２層配線のドライエツチングを行った。はじめに、
基板温度−８０℃の条件でＷＳｉを異方性エツチングし
、次いで、Ｐｏｌｙ−Ｓｉを一１３０℃の条件でエツチ
ングした。この時、プラズマ放電条件は全く変化させず
、基板温度のみを変化させた。エツチング速度は、Ｐｏ
ｌｙ−Ｓｉが約１ μｍ１０＋ｉｎ 。[Example] A silicon oxide layer is formed on a Si substrate, and Pol
Y-Si was formed to a thickness of 300 nm and WSi to a thickness of 300 nm, and then an etching mask was patterned. Thereafter, the two-layer wiring was dry etched using SFg gas at a gas pressure of 80 mTorr using a parallel plate reactive plasma etching apparatus. Introduction,
WSi was anisotropically etched at a substrate temperature of -80°C, and then Poly-Si was etched at -130°C. At this time, the plasma discharge conditions were not changed at all, and only the substrate temperature was changed. The etching speed is Po
ly-Si is approximately 1 μm10+in.
ＷＳｉが約８００ ｎ ｍ／ｌｌｌ１ｎであり、２層と
もすイドエツチングのほとんどない異方性エツチングを
達成した。WSi was approximately 800 nm/llll1n, and anisotropic etching with almost no side etching was achieved for both layers.
また、Ｐｏｌｙ−Ｓｉ上にＷの２層配線、Ｗ Ｓ ｉ上
にＷの２層配線についても、同様に基板温度を変える方
法で異方性エツチングを達成した。Furthermore, anisotropic etching was also achieved for two-layer wiring of W on Poly-Si and two-layer wiring of W on WSi by the same method of changing the substrate temperature.
さらに、上記ＷおよびＷＳｉがＭｏおよびＭｏＳｉにそ
れぞれ置き換えられた２層配線構造においても同様の効
果を得た。Furthermore, similar effects were obtained in a two-layer wiring structure in which W and WSi were replaced with Mo and MoSi, respectively.
装置としては、平行平板型反応性スパッタ装置以外にも
マイクロ波プラズマエツチング装置等に適用可能である
。また、基板温度は１つの電極上で変化させることがで
きるが、２つの温度の異なる電極上に試料を移動させる
ことによっても可能である。As an apparatus, it is applicable to a microwave plasma etching apparatus and the like in addition to a parallel plate type reactive sputtering apparatus. Further, although the substrate temperature can be changed on one electrode, it is also possible to change the substrate temperature by moving the sample onto two electrodes having different temperatures.
本発明によれば、従来高精度加工の難しかった材質の異
なる積層配線を、基板温度を変化させるだけで高精度異
方性エツチングできる効果がある。According to the present invention, it is possible to perform high-precision anisotropic etching of laminated wiring made of different materials, which has conventionally been difficult to process with high precision, simply by changing the substrate temperature.
上記積層配線は２層以上の多層でも可能であり、各層の
材料に適応した試料温度を多段に設定することによって
異方性エツチングを達成できる。The above-mentioned laminated wiring can be made of two or more layers, and anisotropic etching can be achieved by setting the sample temperature in multiple stages to suit the material of each layer.
第１図は本発明によるエツチング形状断面図、第２図は
、２層ポリサイド構造の従来法によるエツチング形状断
面図、第３図および第４図は試料温度とサイドエツチン
グ量およびエツチング速度との関係をそれぞれ示すグラ
フである。
１．１′・・・エツチングマスク、２．２′・・・タン
グステンシリサイド（ＷＳｉ） 、３，３’・・・ポリ
シ第 １ 図
￥Ｊ ２ 図
１．１′ マスク
２．２′り＞７°スデニンリサイト
３．３′ ポリシリコン
４．４′ 藤イ乙シリコン
￥Ｊ ３ 図
第 ｄ 口
紙Ｍ温膚Figure 1 is a cross-sectional view of the etching shape according to the present invention, Figure 2 is a cross-sectional view of the etching shape of a two-layer polycide structure according to the conventional method, and Figures 3 and 4 are the relationship between sample temperature, side etching amount, and etching rate. This is a graph showing each. 1.1'... Etching mask, 2.2'... Tungsten silicide (WSi), 3,3'... Policy No. 1 Figure ￥J 2 Figure 1.1' Mask 2.2'Ri>7 °Sudenine ricyte 3.3' Polysilicon 4.4' Fujii Otsu silicon ￥J 3 Figure d Opening paper M warm skin
Claims (1)
層を形成した後、該第２の配線層上にエッチングマスク
を所望のパターンに形成し、第２の配線層、第１の配線
層の順にドライエッチングする方法において、第２の配
線層をエッチングする時の基板温度より低い基板温度で
第１の配線層をドライエッチングする低温ドライエッチ
ング法。 ２、上記第１の配線層がＰｏｌｙ−Ｓｉであり、上記第
２の配線層がＷＳｉ（タングステンシリサイド）、もし
くはＭｏＳｉ（モリブデンシリサイド）であることを特
徴とする特許請求の範囲第１項記載の低温ドライエッチ
ング法。 ３、上記第１の配線層がＰｏｌｙ−Ｓｉであり、上記第
２の配線層がＷ、もしくはＭｏであることを特徴とする
特許請求の範囲第１項記載の低温ドライエッチング方法
。 ４、上記第１の配線層がＷＳｉもしくはＭｏＳｉであり
、上記第２の配線層がＷもしくはＭｏであることを特徴
とする特許請求の範囲第１項記載の低温ドライエッチン
グ法。 ５、エッチング中の試料の温度モニター、および温調を
行う機能を有し、さらに、エッチング経過時間とともに
試料の設定温度を変化せしめるようにエッチングのシー
ケンスをプログラムする機能を有することを特徴とする
低温ドライエッチング装置。[Claims] 1. After forming a first wiring layer on a substrate and then forming a second wiring layer, an etching mask is formed in a desired pattern on the second wiring layer, and a second wiring layer is formed on the substrate. A low-temperature dry etching method in which the first wiring layer is dry-etched at a substrate temperature lower than the substrate temperature when etching the second wiring layer, in a method of dry etching the second wiring layer and the first wiring layer in this order. 2. The method according to claim 1, wherein the first wiring layer is made of Poly-Si, and the second wiring layer is made of WSi (tungsten silicide) or MoSi (molybdenum silicide). Low temperature dry etching method. 3. The low temperature dry etching method according to claim 1, wherein the first wiring layer is made of Poly-Si, and the second wiring layer is made of W or Mo. 4. The low temperature dry etching method according to claim 1, wherein the first wiring layer is WSi or MoSi, and the second wiring layer is W or Mo. 5. A low-temperature device having a function of monitoring and controlling the temperature of the sample during etching, and further having a function of programming the etching sequence so as to change the set temperature of the sample with the elapsed etching time. Dry etching equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32410387A JPH01166539A (en) | 1987-12-23 | 1987-12-23 | Method and apparatus for dry etching at low temperature |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32410387A JPH01166539A (en) | 1987-12-23 | 1987-12-23 | Method and apparatus for dry etching at low temperature |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01166539A true JPH01166539A (en) | 1989-06-30 |
Family
ID=18162195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32410387A Pending JPH01166539A (en) | 1987-12-23 | 1987-12-23 | Method and apparatus for dry etching at low temperature |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01166539A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314576A (en) * | 1992-06-09 | 1994-05-24 | Sony Corporation | Dry etching method using (SN)x protective layer |
| US5368686A (en) * | 1991-06-18 | 1994-11-29 | Sony Corporation | Dry etching method for W polycide using sulfur deposition |
| US5391244A (en) * | 1992-02-14 | 1995-02-21 | Sony Corporation | Dry etching method |
| US5397431A (en) * | 1992-07-24 | 1995-03-14 | Sony Corporation | Dry etching method |
-
1987
- 1987-12-23 JP JP32410387A patent/JPH01166539A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5368686A (en) * | 1991-06-18 | 1994-11-29 | Sony Corporation | Dry etching method for W polycide using sulfur deposition |
| US5391244A (en) * | 1992-02-14 | 1995-02-21 | Sony Corporation | Dry etching method |
| US5314576A (en) * | 1992-06-09 | 1994-05-24 | Sony Corporation | Dry etching method using (SN)x protective layer |
| US5397431A (en) * | 1992-07-24 | 1995-03-14 | Sony Corporation | Dry etching method |
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