JPH01161181A - Selective signal generator - Google Patents

Abstract

PURPOSE:To decide the staggering time and non-staggering time only with the input of a transmitting cycle signal and a constant cycle triggering signal by using a switching signal generating circuit consisting of a stagger deciding circuit, a non-stagger deciding circuit and an FF circuit. CONSTITUTION:A stagger deciding circuit 4 inputs a transmitting cycle trigger signal 51 and a constant cycle synchronization triggering signal 52, decides a triggering signal cycle from the difference of the cycles of the both triggering signals 51 and 52, and generates a deciding signal at the time of a staggering- triggering time. A non-stagger deciding circuit 5 inputs a processing signal in a circuit 4 and the signal 52, decides the triggering cycle, and generates the deciding signal at the time of a non-staggering-triggering time. A cycle selector circuit 6 inputs the signal 52, the deciding signal of the circuit 4 and the deciding signal of the circuit 5, and generates a selective signal by the presence and absence of the deciding signal of the both circuits 4 and 5. With this constitution, only by inputting the signals 51 and 52, the staggering time and the non-staggering time can be decided, and switching is attained without using a switching control signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a selection signal generator, and relates to a selection signal generator in which the transmission trigger period of a pulse radar device is either a constant period (non-staggered trigger type) or a selection signal generator with adjacent periods having different periods (non-staggered trigger type). The present invention relates to a selection signal generator that determines whether a staggered trigger (one-way type) or not (one-sided type) without a switching control signal and generates a selection signal.

[Conventional technology]

Conventionally, in pulse radar equipment, the Doppler effect is used to select moving targets and fixed targets, but a canceler using a phase detector-delay circuit is used to detect only moving targets. Moving Target Indicator (Moving Target Indicator)
It is. Since the moving target display bag [1/() has the characteristic that when the transmission period is constant (when not staggered trigger), the eraser loses its gain at a frequency that is an integer multiple of the reciprocal of the transmission period. , a moving target signal having a Doppler frequency that is an integer multiple of the reciprocal of the transmission period may be removed as a fixed target by the canceler.

For this reason, in the pulse radar device, adjacent transmission periods are different, so that the frequency at which the gain of the eraser becomes 0 at the time of stagger triggering is raised to a level that does not cause any practical problems.

In order to increase the detection rate of moving targets, a staggered trigger type is usually used, but it is difficult to remove low Doppler frequency signals from unwanted moving targets (rain, clouds, etc.), or when the signal exceeds the transmission cycle interval. If there is a signal from a distant fixed target that is received by the target, the transmission cycle is different each time, so the signal may be received at a specific position each time and not removed as a moving target (secondary echo). For this reason, it is also necessary to use one type of non-staggered trigger, and the pulse radar device has both one type of staggered trigger and one type of non-staggered trigger, which are switched and used depending on the 9VC.

Whether the staggered trigger type or non-staggered trigger type is selected is determined by the changeover switch on the operation panel according to the operator's selection. The signal is sent to each device, and depending on the presence or absence of the switching control signal, each device determines whether it is a staggered trigger type or a non-staggered trigger type, and switches its internal circuit.

[Problem that the invention seeks to solve]

Conventionally, switching between the one-sided staggered trigger type and the one-sided non-staggered trigger type described above was normally achieved by transmitting a switching control signal through a control cable separate from the trigger signal by operating a switch, etc., and then controlling the switching control signal in the input device. Depending on the signal, it is determined whether it is a staggered trigger type or a non-staggered trigger type, and all the circuits to be used are selected. For this reason, a control cable and input/output circuit are required for the switching control signal, which is separate from the trigger signal, so if the wire is disconnected, the control signal will be fixed to one of the methods and will not work properly. Blame the flaws.

Therefore, in contrast to the method of transmitting a periodic switching signal as a control signal, the present invention utilizes the trigger signal +''3 (transmission periodic trigger signal and synchronous trigger signal) instead of transmitting the switching control signal. This provides a selection signal generator capable of switching between a staggered trigger type and a non-staggered trigger type using the trigger signal itself without requiring a switching control signal.

[Failure to solve the problem]

The selection signal generator of the present invention has a stagger determination circuit that inputs a transmission period trigger signal and a synchronous trigger signal of a constant period, determines the trigger signal period based on the difference in the periods of both trigger signals, and generates a determination signal at the time of a stagger trigger. , a non-stagger determination circuit that inputs the processed signal of the stagger determination circuit and the synchronous trigger signal, determines the trigger signal period, and generates a determination signal at the time of a non-stagger trigger; and the synchronous trigger signal and the determination signal of the stagger determination circuit. and a judgment signal of a non-stagger judgment circuit, and a period selection circuit that generates a selection signal depending on the presence or absence of a signal for judgment of the image circuit.

[Real part example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention.
This is an example of one type of pulse φ stagger.

FIGS. 2(a) and 2(b) are timing diagrams of the first embodiment of the present invention, with FIG. 2(a) showing the staggered trigger and FIG. 2(b) showing the non-staggered trigger.

First, the transmission cycle trigger signal 51 is input to the input terminal 1 and is connected to the set terminal of the next-stage flip-flop circuit 11 and the AND gate 12 .

On the other hand, the input terminal 2 has a basic trigger signal 52 with a constant period.
is input and connected to the reset terminal of the next-stage flip-flop circuit 11, the AND gate 13, and the buffer 17 for adjusting delay time.

The output Q53 of the clip-flop circuit 11 is connected to AND gates 12 and 13. In the AND gate 12,
When the output logic of the flip-flop circuit J1 is "1", the transmission cycle trigger signal 54 is sent to the next stage flip-flop circuit 1.
It outputs to the set terminal of 4 and the OR gate 15. on the other hand,
In the AND gate 13, the Q of the flip-flop circuit 11 is
When the output 53 is at logic "1", the basic trigger signal 55 is output to the reset terminal of the next-stage flip-flop circuit 14 and the clock terminal of the counter circuit 16.

The clear terminal of the counter circuit 16 has an OR gate 15
is connected, and when the output of the AND gate 12 is logic "1" and the output of the AND gate 19 is logic 1, it outputs logic "1'" to the counter circuit 16, Reset the color/color circuit 16. The counter circuit 16 counts the signal input to the clock terminal, and the first stage output is outputted to QA+57, the second stage output is outputted to QB+58, and the third stage output is outputted to QC+59.When counted four times, the output is outputted to QC159. The logic W I Jl is outputted to the AND gate 19 at the next stage.

In the AND gate 19, when the Qc1 output 59 of the counter circuit 16 is logic "1", the basic trigger signal delayed by the buffer 17 is sent to the next stage flip-flop circuit 2.
It is sent to the reset terminal of 0 and the OR gate (15).

On the other hand, a basic trigger signal delayed by the buffer 17 is output from the AND gate 18 to the set terminal of the flip-flop circuit 20 when the output 56 of the flip-flop circuit 14 is at logic "1".

The flip-flop 20 has a logic value gate 18 of logic "1".
'' (i.e., during stagger trigger), it is set and outputs all logic ``1'' as output signal 60, and when AND gate 19 is logic ``1'' (i.e., when non-stagger trigger), it is reset. It outputs a logic "0" and is sent to the output terminal 3.

Here, referring to FIG. 2(a), if we consider, for example, four different transmission cycles at the time of stagger trigger, the transmission cycle of the transmission cycle trigger signal 51 is Tl - T2 ・T.
3 ・T4, T t < T 3 < T 2
If < T 4 and Σ T1-4 To (To is the period of the basic trigger signal i prize 152), the four transmission periods will be called one frame because it is repeated every four transmission periods.

At this time, a trigger signal is output to the output 54 of the AND gate 12 once per frame, and a trigger signal is output to the output 55 of the AND gate 13 three times per frame. As a result, the clear terminal (CL
R) [ is applied with a trigger signal once every l frame, and the clock terminal receives a trigger signal three times per frame, resulting in logic "0", and the output of AND gate 19 becomes logic "0°". On the other hand, the flip-flop circuit 14 is triggered by the trigger signal of the AND gate 12.
Since it is set and reset by the trigger signal of the AND gate 13, a gate signal K1 times per frame is outputted to the output 56, and a basic trigger Vc once per frame is outputted from the AND gate 18. In the flip-flop circuit 20, the output of the AND gate 19 is a logic par 0''', and when set by the basic trigger of the AND gate 18, it is held and output terminal 3 receives a stagger trigger signal. An output signal 60 of logic "P1" shown in FIG.

Next, considering the non-staggered trigger, Fig. 2(b)
As can be seen, the output 54 of the AND gate 12 is a logic "0"
On the other hand, a trigger signal is outputted four times in one frame to the output 55 of the logic fall gate 13. This results in
The counter circuit 16 performs counting because there is no trigger signal from the AND gate 12, and after counting four times, logic "1" is output to the output Qc+59, and the AND gate 12 counts.
At 9, a trigger signal is output. This trigger signal is sent to the OR gate 15 and the flip-flop circuit, and the output of the OR gate 5 becomes logic "1'" due to the trigger signal, thereby resetting the counter circuit 16.

On the other hand, the output 56 of the flip-flop circuit 14 is not set because the output 54 of the AND gate 12 is a logic N O++.

Therefore, the output of the AND gate 18 also becomes logic "0". The flip-flop circuit 20 is not set because the output of the AND gate 10--gate 18 is logic "0".
Since the selection reset is performed by the trigger signal output of the AND gate 9, the output 60 becomes a logic "0", and the output terminal 3 outputs a logic "0" indicating a non-stagger trigger.

FIG. 3 is a circuit diagram showing the configuration 2 of the second embodiment of the present invention,
This is an example in which a counter circuit is used as a stagger determination circuit. 4(a) and 4(b) are timing diagrams of the second embodiment of the present invention, with FIG. 2(a) showing the staggered trigger and FIG. 2(b) showing the non-staggered trigger. show.

In the second embodiment, the flip-flop circuits 11 and 14 used in the first actual case and the AND gate 1
2.130 part, color/recircuit 21 and AND gate 2
The transmission cycle trigger signal 51 inputted from the input terminal 1 is inputted to the clock terminal of the counter circuit 21 and counted. On the other hand, the basic trigger signal 52 input from the input terminal 2 is connected to the clear terminal of the counter circuit 21, the AND gate 22, and the buffer 17.

The counter circuit 21 resets the count value to all 0 every time the trigger signal is input to the clear terminal, and outputs the logic N II+ to the AND gate 22 after counting one double period trigger signal 51 . On the other hand, the output QBZ62 outputs logic "1" to the AND gate 18 and the OR gate 15 when two items are counted.
The basic trigger signal 52 that is input to the other side when
is output to the counter circuit 16.

The count value of the counter circuit 16 is reset to O by the trigger signal output of the OR gate 15, and the AND gate 22
The output trigger signal 64 is counted. Counter circuit 16
The output Qct59 is connected to the AND gate 19, and when the output QC159 is at logic "1", a trigger signal is output from the AND gate 19. The output QB 262 of the counter circuit 21 is connected to the AND gate 18, and when the output QB 262 is logic n 1u, the AND gate 18
A trigger signal 63 is output from.

The flip-flop circuit 20 is set when the trigger signal 63 of the AND gate 18 is logic 1°, outputs a logic 1 pass indicating stagger triggering as the output signal 60, and the output of the AND gate 9 is set to logic 1°. ″、When ++,
Reset to logic ``0'' to indicate non-staggered trigger
” is output to output terminal 3.

Now, looking at FIG. 4(a), when considering the stagger trigger as in the first embodiment, the output Q of the counter circuit 21 is
Az61iC outputs three gate signals in one frame. On the other hand, the output QB262 outputs a VC gate signal once per frame. Output QA of counter circuit 21
262 is connected to the AND gate 22, performs an AND operation with the basic trigger (i 52), and outputs the trigger signal 64 twice in the ■ frame.
6, the count value is set OVcIJ by the output signal of the output QB 262 of the color counter circuit 21, and the trigger signal 64 of the AND gate 22 is counted. The output of the AND gate 22 is 1
Since the trigger Shingetsu 64 is output only twice in a frame, the output QC159 of the counter circuit ]6 is always logic ``0''.
", and the output of the AND gate 19 is always logic "0". On the other hand, the output QB262 of the counter circuit 21 is connected to the AND gate 18, and the output 63 of the AND gate 18 has a logic "0". times trigger signal is output.

The flip-flop circuit 20 is set to logic "1" by the trigger signal output 63 of the AND gate J8, and the output terminal 3 outputs a logic "1" signal 60 indicating stagger triggering.

Also, considering the non-staggered trigger, the counter circuit 2
A gate signal is outputted to the output QA261 of 1 four times in one frame, while the output QB262 becomes logic "0". The output QA261 of the counter circuit 2 is connected to the AND game 221/i, and is subjected to a logical calculation with the basic trigger signal 52, so that a trigger signal is output four times in one frame. In the counter circuit 16, the output QB262 of the counter circuit 21 is logic "0", the count value is not reset, and the trigger signal output 6 of the AND gate 22
4 is counted. Since the output 64 of the logic gate 22 outputs a trigger signal four times in one frame, the output QC159 of the counter circuit 16 outputs the logic "J" once in one frame.
So, the output of AND gate 19 is!・Output the rigger signal once per frame. The trigger signal output from the AND gate 19 is input to the OR gate 15, and the trigger signal is output from the OR gate 15 to reset the count value of the counter circuit J6. Since the output QB262 of the counter circuit 21 is logic 00'', the AND gate 18
The output of 63 becomes logic "0". The flip-flop circuit 20 is reset to logic "0" by the trigger signal output from the AND gate 9, and the output terminal 3 outputs a logic "0" signal 60 indicating a non-stagger trigger.

〔Effect of the invention〕

As explained above, the present invention includes a stagger judgment circuit made up of a gate circuit and a noritoflop circuit or a counter circuit, a non-stagger judgment circuit made up of a counter circuit, and a switching signal generation circuit made up of a flip-flop circuit. By using this, it is possible to determine whether a stagger trigger is occurring or not when a stagger trigger is occurring, simply by inputting a transmission periodic trigger signal and a periodic trigger signal with a fixed period.
This has the advantage that switching can be performed without requiring a switching control signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIGS. 2(a) and (b) are timing diagrams of the first embodiment of the present invention, and FIG. 3 is a circuit diagram showing the configuration of the first embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of the second embodiment, and FIG. 4 is a timing diagram of the second embodiment of the present invention. ■・2...Input terminal, 3...Output terminal, 4...Stagger judgment circuit, 5...Non-stagger judgment circuit, 6... ...Period selection circuit.

Claims (1)

[Claims] A stagger determination circuit receives a transmission cycle trigger signal and a synchronous trigger signal of a constant cycle, determines the trigger signal cycle based on the difference in the cycle of both trigger signals, and generates a determination signal at the time of a stagger trigger, and a processed signal in the stagger determination circuit. and a non-stagger determination circuit that inputs the synchronous trigger signal, determines the trigger signal period, and generates a determination signal in the event of a non-stagger trigger; and the synchronous trigger signal, the determination signal of the stagger determination circuit, and the determination signal of the non-stagger determination circuit and a cycle selection circuit that generates a selection signal depending on the presence or absence of determination signals from both circuits.