JPH01160056A - Manufacture of thin-film field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the stepped section of a gate electrode disposed onto the surface of an insulating film by removing a protruding section on all amorphous silicon layer appearing at a time when the insulating film coating the amorphous silicon layer on a drain electrode and a source electrode is formed through etching and smoothing the surface of the insulating film. CONSTITUTION:A film is shaped to a glass substrate 1 through a sputtering method from metal chromium, and machined to specified shapes through photolithographic-etching, thus forming a drain electrode 2 and a source electrode 3. A film is shaped through a plasma CVD method from an amorphous silicon film, and machined to a specified shape through photolithographic-etching, and an amorphous silicon layer 4 is formed onto the drain electrode 2 and the source electrode 3. A film is shaped through the sputtering method from a silicon oxide film, a resist is applied onto the film and patterned, and the protruding section of the surface of the silicon oxide film on the amorphous silicon layer 4 is etched to form a smooth section 10. A film is shaped through the sputtering method from metal chromium, and machined to a specified shape through photolithographic-etching, thus forming a gate electrode 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film field effect transistor used in an active matrix liquid crystal display, and particularly relates to the structure of the intersection of a drain electrode, a source electrode, and a gate electrode. .

[Conventional technology]

Since metal films and silicon oxide films can be easily formed by sputtering, and silicon nitride films and amorphous silicon films can be formed by plasma CVD on glass substrates, thin-film field-effect transistors using these films ( T P
T) is being developed and put into practical use for active matrix liquid crystal displays.

FIG. 3 shows a sectional view of an example of a conventional TPT.

In the figure, a drain electrode 2 and a source electrode 3 are provided on the surface of a glass substrate 1, and a semiconductor amorphous silicon layer 4 is deposited to connect the drain electrode 2 and source electrode 3. An insulating film 15 made of silicon nitride or the like is formed to cover.

Furthermore, a gate electrode 16 is arranged on the surface.

This TPT structure is called a staggered structure, in which a linear drain electrode 2 and a source electrode 3 with a line width of 10 to 15 μm are located at the bottom layer, and an amorphous layer between the drain electrode 2 and the source electrode 3 is located at the bottom layer. There is an insulating film 15 covering the silicon layer 4, and a linear gate electrode 16 with a line width of 10 to 15 μm is formed on the surface of the insulating film 15, and a drain electrode 2 and a source electrode 3 are formed on the surface of the insulating film 15.
It is arranged to intersect with the

[Problem that the invention seeks to solve]

At the intersection of this drain electrode 2 and gate electrode 16,
The film thickness of the drain electrode 2 and source electrode 3 is 1500 mm,
Due to the deposition of the amorphous silicon layer 4 with a thickness of 3,000 layers and the deposition of the insulating film 15 with a thickness of 3,000 layers, a step is created in the gate electrode of the uppermost layer. This step has the disadvantage that when forming the gate electrode 16, a step breakage may occur due to insufficient film formation or abnormal etching, or even if a step breakage does not occur, the resistance becomes high.

As a result, when you display the manufactured liquid crystal display,
Linear defects and display unevenness occurred, significantly impairing display quality.

[Means for solving problems]

In contrast to the conventional TPT manufacturing method described above, the present invention etches the protrusions on the amorphous silicon layer that appear when forming an insulating film covering the amorphous silicon layer on the drain and source electrodes. By removing the insulating film and smoothing the surface of the insulating film, it is possible to reduce the step difference in the gate electrode disposed on the surface of the insulating film, and also to make contact with external wiring highly reliable. Therefore, even if the thickness of the drain electrode is increased, the step difference will not increase due to the increase in the thickness.

〔Example〕

Next, the present invention will be explained by examples.

FIG. 1 is a sectional view for explaining Embodiment 1 of the present invention. In FIG. 1, first, metal chromium is deposited on a glass substrate 1 by sputtering to a thickness of 1,500 mm, and then processed into a predetermined shape by photolithography and etching to form a drain electrode 2 and a source electrode 3. . Next, an amorphous silicon film was formed to a thickness of 3,000 yen by plasma CVD, and then processed into a predetermined shape by photolithography and etching to form drain electrode 2 and source electrode 3.
An amorphous silicon layer 4 is formed thereon. Next, a silicon oxide film was formed to a thickness of 7,500 mm by sputtering, and a resist was applied and patterned on this to form a 450 mm thick silicon oxide film on the amorphous silicon layer 4.
A smooth part 10 is obtained by etching. Furthermore, a 1500 mm thick film of metallic chromium is formed by sputtering and processed into a predetermined shape by photolithography and etching to form the gate electrode 6, thereby completing the TPT.

FIG. 2 is a sectional view for explaining Example 2 of the present invention. In FIG. 2, first, metallic chromium is deposited on a glass substrate 1 to a thickness of 1500 mm by sputtering, and then processed into a predetermined shape by photolithography and etching to form a drain electrode 2 and a source electrode 3. Next, an amorphous silicon film was formed with a thickness of 3000 using plasma CVD method.
After the film is formed, it is processed into a predetermined shape by photolithography and etching to form an amorphous silicon layer on the drain electrode 2 and source electrode 3. Next, a silicon nitride film 7 was deposited to a thickness of 2,000 yen by plasma CVD, and a silicon oxide film 8 was deposited to a thickness of 5,500 yen by sputtering to form a double insulating film, and a resist was applied thereon. After patterning, the convex portions on the surface of the silicon oxide film 8 on the amorphous silicon layer 4 are etched to a thickness of 4,500 mm to form a smooth portion 10. Further, metallic chromium is deposited to a thickness of 1,500 mm by sputtering and patterned to form the gate electrode 6, completing the TPT.

〔Effect of the invention〕

As explained above, according to the present invention, the protrusions caused by the film thickness that appear on the surface of the insulating film on the drain electrode, source electrode, and amorphous silicon layer are smoothed by photolithography etching. There is no step break in the gate electrode formed on top of the gate electrode, and even if the drain electrode is made thicker in order to make good contact with external wiring, the increase in film thickness will cause The difference in steps will never be large. Therefore, the manufactured liquid crystal display has high wiring reliability and no display unevenness, so it can provide an excellent display quality.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of TPT according to Example 1 of the present invention, and FIG.
The figure is a sectional view of a TPT according to a second embodiment of the present invention, and FIG. 3 is a sectional view of a conventional TPT. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Drain electrode, 3... Source electrode, 4... Amorphous silicon layer, 5... Insulating film, 6...gate electrode, 7...silicon nitride film, 8...
...Silicon oxide film, 10...Smooth part. Agent Patent Attorney Otokiku Uchihara 2 Mikiku 5 Diagram

Claims (1)

[Claims] A drain electrode and a source electrode are formed on an insulating substrate, an amorphous silicon layer is deposited to connect the drain electrode and the source electrode, and an insulating film is formed to cover this amorphous silicon layer. , in a method of manufacturing a thin film field effect transistor including forming a gate electrode on the insulating film, a convex portion appearing on the surface of the insulating film covering the amorphous silicon layer is removed by etching. A method for manufacturing a thin film field effect transistor, which comprises forming a gate electrode after smoothing the surface of an insulating film.