JPH01159867A - Control information extractor - Google Patents

Abstract

PURPOSE:To extract a frame address with a high reliability by counting the number of control information pieces extracted for the contents of the control information, comparing the degrees of counting values, holding the control information corresponding to the maximum counting value and outputting it. CONSTITUTION:The number of the reproduced control information pieces are counted by N-number of counting means 20, 21... for the kind of the control information, and the values are held by N-number of counting value holding means 24, 25.... The degrees of respective counting values are detected by a comparing means 31 to compare them, the control information corresponding to the maximum counting value is held in an extracted control information holding means 32, and a majority extraction is executed. In such a way, by majority-extracting the control information, which is added to a PCM signal several times at the time of recording, at the time of reproducing, the control information with a high reliability can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a control information extraction device that extracts control information added to a PCM signal when decoding the PCM signal.

BACKGROUND OF THE INVENTION In recent years, the digitization of signals in the audio and video fields has progressed rapidly, and digital audio discs (CDs),
Audio PCM broadcasting using digital audio tape recorders (DAT) and broadcasting satellites has been realized.

Among these, digital audio tape recorders have been put into practical use as rotary head digital audio tape recorders (R-DAT) because of their high recording density and easy access.

R-DAT that records/plays digital audio signals
As shown in Figure 3, the synchronization signal (SYNC)
6. [D code (Wl)7. Block address (W2)
8. Parity (P)9. Data 10 is treated as 1 block data, and is recorded on tape 1 in a track configuration of 128 blocks in PCM area 2 and 16 blocks in subcode area 3 during the track.

In the data structure of one block, parity (P
) is determined and recorded by exclusive OR operation of the ID code (Wl) and block address (W2). That is, between parity (P), ID code (Wl), and block address (W2), P-Wl■W2 ・
...The relationship of +11 is established. At the time of playback, a parity check is performed based on the above formula ( ]), and Wl, which is control information.

W2. Detect an error in P.

Figure 4 shows the ID code (Wl) of the PCM area.

The data structure of block address (W2) is shown.

The R-DAT has two magnetic heads (one is called the A head) attached to opposite positions on the cylinder.

As shown in FIG. 3, alternating tracks A and B are formed diagonally on the tape 1 (the track recorded by the A head is A track 4).
．． The track recorded by 8 heads is B track 5.
), but the block address 12 indicates the position occupied by the block in the trunk.

11 is pcM=D, and the upper 4 bits 1D-1 to I
D-8 is control information regarding audio data (for example, sampling frequency information).

Quantization information, emphasis information, etc.) 1 The upper 4 bits of the frame address are 0000 (21 to 1
111. This is address information that is added sequentially up to f2). Therefore, within one frame consisting of a pair of tracks A and B, the same value is repeatedly recorded for the frame address, and the same value is recorded within the i frame for ID-1 to ID-10-8 as well.

Now, during playback, a control information extraction device is required that detects errors in PCM-lo (Wl), block address (W2), and parity (P) by parity check and extracts correct control information.

FIG. 5 shows a block diagram of a frame address extraction circuit as an example of a conventional control information extraction device in R-DAT. 13 is a parity check circuit, which checks the reproduced control information W1. W2. Detect an error in P. 14 is a latch pulse generation circuit, and the parity check circuit 13 ensures that there is no error (hereinafter, parity check is OK).
A pulse is generated when it is determined that the A data launch 15 holds a frame address using a pulse generated by the launch pulse generation circuit 14. 1
Reference numeral 6 denotes an extracted frame address holding device which takes in and holds the frame address held in the data latch 15 in response to the trunk switching pulse 17. Here, the track switching pulse changes from A track to B track, and B
This is the pulse generated when switching from the trunk to the A track.

According to the above configuration, while the same one track is being reproduced, each time it is determined that there is no error in the parity check (parity check OK), the frame address is rewritten and held in the data latch 15, and finally during the open-l track. The last reproduced parity checker 7 OK frame address is held in the extracted frame address holding device 16.

Problems to be Solved by the Invention As described above, according to the conventional control information extraction device in R-DAT, the control information of the last reproduced parity check OK in one track is extracted. Wl, W2. If two of P are incorrect, the error cannot be detected.

There was a problem of often extracting incorrect control information.

Furthermore, if one of the magnetic heads becomes clogged with magnetic powder, dust, etc. during recording and recording becomes impossible, tracks recorded before that recording remain, and errors cannot be detected by parity check during reproduction.

Regarding the frame address in R-DAT,
Continuity, A track within the same frame.

Based on the bare property that the same value is recorded on the B track, it is used to determine whether or not there is a data abnormality. Depending on the result of this determination, processing such as performing interpolation playback using one of the tracks A and B) or applying muting is executed to prevent abnormal noise from occurring. Therefore, high reliability is required for frame address extraction.

Means for Solving Problems Control information added to the PCM signal includes a finite number (N) of multiple types of information, and control information in which the same information is added multiple times (for example, as shown in Figure 4). PCM-ID) in the R-DAT shown above is the PCM-ID after the control information is added.
In a control information extraction device that extracts from a signal, N counting means count the number of reproduced control information for each type of control information, and N counting values that hold the values counted by the counting means. a holding means, a comparison means for comparing the magnitude of each count value held by the N count value holding means, and extraction control information holding for holding control information corresponding to the maximum count value detected by the comparison means. and means for extracting control information by majority vote.

According to the present invention, highly reliable control information can be obtained by extracting control information that is added multiple times to a PCM signal during recording using the above-described configuration during reproduction.

Embodiment Below, a frame address extraction circuit of an R-DAT, which is an embodiment of the present invention, will be explained with reference to the drawings.

In FIG. 1, 18 is a parity check circuit;
PCM-ID (Wl) shown in FIG.

19 is a counting pulse generation circuit that takes in the block address (W2) and parity (P) and performs a parity check.
The lower 4 bits of M-ID are the frame address), and the value is OOOO (21 to 1111 (21
It determines which value it is among 16 types, and generates a pulse at the terminal corresponding to the value. 20 is a terminal. . . . Then, the parity check is OK by the counting pulse generation circuit 19.
A pulse is output when the current frame address is determined to be 0000. 21 is a terminal. . . 1, a pulse is output when the counting pulse generating circuit 19 determines that the frame address is 0001 when the parity check is OK. Similarly, the terminals are terminal 1□1, up to 1
Six of them are provided, and a pulse is outputted in accordance with the value of the frame address when the parity check is OK. 22 is a counter.

000, and when the parity check is OK, the frame address 0000 is determined by the counting pulse generating circuit 19 at the terminal.

The pulse output to o020 is counted as a clock. 23 is a counter. . 01 and parity check O
The number of times frame address 0001 at time K has been reproduced is determined by the counting pulse generating circuit 19 at the terminal.

. . 121 is counted as a clock. Similarly, the counters are 1 up to counter 1□1□.
Six units are provided, and the number of times each frame address is reproduced is counted according to the value of the frame address when the parity check is OK. Lunch on the 24th. . . . and the counter. . . . The number of reproductions of frame address 0000 such as parity check OK counted by 22 is
It is captured and held by the track switching pulse 26. 2
5 is a latch. . .

1, and the counter. . . Frame address 0001 when parity check is OK counted by 123
The number of reproductions is captured and held by the trunk switching pulse 2G. Similarly, 16 launches are provided including latches 11□1, and the number of reproductions of each frame address when the parity check is OK is captured and held at the timing of the track switching pulse 26. Here, the trunk switching pulse 26 is a pulse generated when switching from the A track to the B track and from the B track to the A trunk. A timing generator 27 delays the track switching pulse 26 and generates a maximum value detection start pulse 28, an extraction frame address latch pulse 29, and a counter clear pulse 30. Figure 2 +al~Fd
1 is a timing diagram of the maximum value detection start pulse 2 days, the extraction frame address launch pulse 29, the counter clear pulse 30, and the track switching pulse 26. 31 is a maximum value detection circuit, which launches when the maximum value detection start pulse 28 is input.

The count value of the number of reproductions of each frame address during the parity check circuit held in non-launch □ 11 is taken in, the maximum count value is determined, and the frame address with the maximum count value is detected.

Reference numeral 32 denotes an extracted frame address holding device, which captures and holds the frame address with the maximum reproduction count detected by the maximum value detection circuit 31 at the timing of the extracted frame address launch pulse 29.

Effects of the Invention According to the above configuration, when one track is played back, 64 frame addresses are played back (as shown in FIG. 4, the frame addresses are recorded in even-numbered blocks among the 128 blocks in the PCM area). However, all of the frame addresses for which the parity check is OK are extracted, and the frame address that has been reproduced the most can be adopted from among them, making it possible to extract frame addresses with extremely high reliability.

In the above embodiment, the present invention was implemented in a frame address extraction circuit in R-DAT, but there are a finite number of multiple types of information in the control information added to the PCM signal, and the same information The present invention can be applied to a control information extraction device that extracts control information that is added multiple times from a PCM signal after the control information has been added, making it possible to extract control information with high reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an R-DAT frame address extraction device which is an embodiment of the present invention, FIG. 2 is a timing diagram of the present invention, FIG. 3 is an explanatory diagram of the R-DAT block format, and FIG. This figure is an explanatory diagram of the frame address recording formant of R-DAT, and FIG. 5 is a block diagram of a conventional frame address extracting device in R-DAT. 18... Parity check circuit, 19...
...Counting pulse generation circuit, 20... terminal. . . . , 21...terminal. . . 1.22...
counter. . . . , 23... Counter. . . 1
,24...Lunch. . oo125...Lunch. . . 1.26...Track switching pulse, 27...Timing generator, 28...Maximum value detection start pulse, 29...Extraction frame address latch pulse, 3o... ...Counter clear pulse, 31...
...Maximum value detection circuit, 32...Extraction frame address holding bag;. Name of agent: Patent attorney Toshio Nakao (1 person)
Co c> 0 to N 4 0)

Claims (1)

[Claims] In a control information extraction device that extracts control information added to a PCM signal, in which information with the same content is added multiple times, from a PCM signal after the control information has been added, for each content of control information, A counting means for counting the number of extracted control information and holding the counted value, a comparing means for comparing the magnitude of the counted value held by the counting means, and a maximum counted value detected by the comparing means. What is claimed is: 1. A control information extracting device, comprising: extraction control information holding means for holding and outputting control information, and extracting highly reliable control information.