JPH01159686A - Display control circuit in interlaced scanning system - Google Patents

Abstract

PURPOSE: To read two kinds of information out of a display memory and make a divisional display on an interlaced scanning type CRT possible by adequately supplying a display memory with a display address outputted from a display control signal generating circuit and the contents of a 2nd address counter. CONSTITUTION: When the count value of a line counter 7 reaches a value corresponding to a division position, a buffer 3 stops the display address outputted from the display control signal generating circuit (CRTC) 2 from being supplied to the display memory 4. Further, a display cycle signal is supplied to a 1st address counter 9 and a 2nd address counter 10, and the contents of the 2nd address counter 10 are supplied to the display memory 14. Consequently, the simple circuit constitution of the CRTC 2 and 2nd address counter 10 generates the display address matching an interlaced scanning type CRT independently to make a divisional display.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a display control circuit in an interlaced scanning method, and particularly to an address generation circuit for a display memory.

(B) Conventional technology In recent years, display devices used in information processing devices such as personal computers and information file systems have icons that display icon information such as processing modes to instruct the operator on operations. Is it possible to split the display into a display area and an image display area that displays image information?
Alternatively, the structure is such that different image information can be divided and displayed in different areas, and in these cases, a plurality of address generation circuits are provided to address each of the plurality of areas of the display memory (for example, 13671
For details on the publication).

(c) Problems to be Solved by the Invention Most importantly, the above-mentioned prior art does not provide an interlaced scanning type display control circuit.

Therefore, the present invention provides a simple display control circuit for performing split display in an interlace scanning display.

(D) Means for Solving Problem 1 The present invention is a display control circuit for displaying at least 2m types of information in a display memory on an interlaced scanning CRT. a display control signal generation circuit that outputs a horizontal synchronization signal, a display cycle signal, and a first/second field identification signal; a latch that holds a dividing line value that divides the screen of the CRT into at least two display areas; Load the divided line value from the latch in synchronization with synchronization number 46, and then load the divided line value into a line counter that counts the horizontal synchronization signal and one of the divided lines based on the state of the first/second field identification signal. 1st display area
The first address counter, which loads the first address of the line or the first address of the second column in synchronization with the vertical synchronizing signal and counts up by two by applying the display cycle No. 8, and the horizontal synchronizing signal. A second address counter that synchronously loads the contents of the first address counter and counts up by one by applying the display cycle signal, and selectively displays the display address output from the display control signal generation circuit. and a buffer configured to supply the display address outputted from the display control signal generation circuit to the display memory until the counted value of the line counter reaches a value corresponding to the division position. , when the count value of the line counter reaches a value corresponding to the division position, the buffer prevents the display address output from the display control signal generation circuit from being applied to the display memory, and also prevents the display cycle signal from being applied to the display memory. is applied to the first address counter and the second address counter, and the contents of the first address counter are applied to the display memory.

(E) Function According to the present invention, two types of information in the display memory are read out by appropriately providing the display address output from the display control signal generation circuit and the contents of the second address counter to the display memory; It is possible to display the image dividedly on an interlaced scanning CRT.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. (
1) is a control circuit (hereinafter referred to as CPU) that outputs various data necessary for the display format, and (2) is a control circuit that outputs various data necessary for the display format.
signal>, the horizontal synchronization signal (signal on the line), the display cycle signal (5pcyc signal) which is the output timing signal for the display address of one line of information, and the VSYNC signal, which alternately changes to a high state and a low state. A general-purpose display control signal generation circuit (hereinafter referred to as CRTC) that outputs the first/second field identification signal (ODD/EVEN signal)
, (3) is a buffer that controls the output of the display address from the CRTC (2), and (4) is a display memory that stores information on the dot pattern to be displayed on the CRT (5). The memory (4) stores image information displayed in the image display area of the CRT (5) and icon information displayed in the icon display area of the CRT (5).

(6) is a latch that holds the value of the first display line of the icon display area in CRT (5), and <7) loads the value held in latch (6) in synchronization with the VSYNC Kungo.
After that, it is a line counter that performs a countdown operation for each H5YNC signal, and when this line counter (7) reaches 0, it outputs a division permission signal (DVEN signal).
Thereafter, the 0VEN signal is output and the count-up operation is stopped until the VSYNC signal is applied. (
8) inputs the DSPCYC signal and DVEN signal, and (9) inputs the ODD/EVEN signal, which outputs the divided display cycle signal (DDCYC signal). The display address value of the display memory (4) in which the first icon information displayed on the first line of the display area is stored, and the second line of the icon display area when the ODD/EVEN signal is low. This is a first address counter that loads the display address value of the display memory (4) in which the first icon information to be displayed is stored, respectively, in synchronization with the VSYNC signal, and after such loading, A count-up operation is performed by two in response to the falling edge of the signal.

10) is a second address counter that loads the contents of the first address counter 9) in synchronization with the H5YNCfK signal. After a negative load, it performs a count-up operation by 1 at the rising edge of the DDCYC signal, and ,
When the DDCYC signal is low, the contents are output. (
11) is an impark that inverts the DDCYC signal and applies it to the buffer (3), and the DDC signal is inverted from the inverter (11).
When the inverted signal of the YC signal is applied to the buffer (3),
Buffer (3) is output from CRTC (2).

application of the display address to the display memory (4).

Below, before explaining the operation of this embodiment in detail, it will be briefly explained. The CRT (5) has a screen size of X (horizontal direction>
) line to the y-th line, the CRTC ( The address output from 2) is given to the display memory (4) via the buffer (3). At this time, the value of n indicating the boundary line of the display area is determined by the CPU.
It is given from (1) to the latch (6) and is further loaded into the line counter (7), and the line counter (7) detects whether the display address instruction has reached the boundary line. . When the boundary line is reached, the display address for reading out the second information to be displayed on the (n+1)th line to the yth line from the display memory (4) is output from the CRTC (2). Instead of the address output from the second address counter (10), the address output from the second address counter (10) is given to the display memory (4).

At this time, CRTC (2) is an interlaced scanning CR
The addresses of all odd lines and the addresses of all even lines are output alternately in accordance with T(5).

Therefore, the second address counter (10) also outputs addresses one line apart, and the first address counter (9) outputs addresses on all odd lines and addresses on all even lines alternately. controls the counting operation of the second address counter (10).

In this way, the CRTC (2) and the second address counter (
10), a display address is selectively given to the display memory (4).

The operation of the block diagram in FIG. 1 will be explained in more detail below. In this case, as a specific example, the CRT (5) has a screen size of 400 dots (horizontal direction) and xaoo lines (vertical direction), the 1st line to the 400th line is the image display area, and the 401st line to the The 600 lines are the icon display area. The display memory (4) stores image information from address 1 to address 5ooo, and icon information from address 50001 to the final address, and stores one line of information for each 50 addresses. shall be.

FIG. 2 is a signal waveform diagram of the main part of the above block diagram,
The time shown in FIG. 5(b) is longer than that in FIG. 3(a), and the time shown in FIG. The operation of this embodiment will be explained with reference to such a signal waveform diagram. It is assumed that image information and icon information are already stored in the display memory (4) in the state described above.

The CPU (1) gives a display command signal to the CRTC (2) and sets a value of 400, which is the boundary line between the two display areas, in the latch (6).

As a result, the CRTC (2) sets the ODD/IJ signal to a high state, and the
Output a signal. In synchronization with the VSYNC signal, the line counter (7) loads the value 400 in the latch (6), and at the same time the first address counter (9) loads address 50001, which is the starting address of the first line of icon information. do. The loading of the first address counter (9) is C
It may be done from the PU (1), or it may be done automatically by using the first address counter (9) as a programmable counter.Furthermore, the CRTC (2) responds to the timing of the DSPCYC signal it outputs, and
The display addresses of the display memory (4) where the information displayed on the odd numbered lines of T(5) is stored are set as the start address of address 1 to address 500, address 101 to address 150, etc., with address 1 as the start address. Output to. Currently, the line counter (7) is not performing a predetermined count-up operation (400 count-up operations in this embodiment) in synchronization with the HSYNC signal, so the display address output from the CRTC (2) is not in the buffer. Through (3), the address of the odd line of information to be applied to the display memory (4) and displayed in the image display area of the CRT<5 is designated.

In this way, the display address instruction from the CRTC (2) to the display memory (4) progresses, and the line counter (7)
) counts down to 400 by the countdown operation synchronized with the H8YNC signal, then the line counter (7)
outputs the DVEN signal and stops the subsequent countdown operation.

Due to the DVEN signal, the DSPCYC signal output from the CRTC (2) is sent to the DSPCYC signal via the Nant gate (8).
The DCYCM signal is applied to the first address counter (9) and the second address counter (10) (see FIG. 2(b)). As a result, as shown in FIG. 2(C),
The first address counter (9) starts from address 5ooot, which has been fully loaded, and counts up by two at the rising edge of the DDCYC signal. At the same time, the second address counter (10) starts from address 50001 loaded from the first address counter (9) and counts up by 1 at the rising edge of the DDCYC signal, and then the DDCYC signal goes low. Output this content when At this time, D
The DCYC signal is sent to the buffer (
3), and the display address output from the CRTC (2) is blocked by the buffer (3). Therefore, addresses 50001, 50002, . . . output from the second address counter (10) are given to the display memory (4) as display addresses. Then, when the second address counter (10) counts up to address 5ooso and all the addresses of the display memory (4) in which the information to be displayed on the 401st line of the CRT (5) is stored are specified, The first address counter (9) performs a count-up operation up to address 50101. At this point, the second address counter (10
) is the content of @1 address counter (9) 5010
1 address is loaded, and then the second address counter (10) is loaded with 50 in synchronization with the DDCYC signal in the same manner as described above.
From address 101 to address 50102, address 50103...
and performs a count-up operation, and these addresses are C
This is specified to the display memory (4) as the display address of the display memory (4) where the information to be displayed on the 403rd line of RT(5) is stored.

In this way, when the line counter (7) counts 400, instead of the display address output from the CRTC (2), the second address counter (10) outputs the odd line of the CRT (5). The display address is given to the display memory <4), and the address of the odd line of icon information to be displayed in the icon display area is designated.

Next, when the CRTC (2) outputs a 600-pulse HSYNC signal, it sets the ODD signal to a low state and Y
Gives a SYNC signal. In synchronization with such VSYNC signal,
The increment counter (7) reloads the value 400 in the latch (6), and the first address counter (9) loads 50051, which is the starting address of the second line of icon information.
Load the street address. And CRTC(2) is DSPC
At the timing in response to the YC signal, display addresses (i.e., addresses 51 to 100, addresses 151 to 20) where information to be displayed on even-numbered lines of the CRT (5) are fully stored are selected.
By sequentially outputting addresses 0, . . . ), these display addresses are given to the display memory (4) via the buffer (3), and the even-numbered lines of information displayed in the image display area of the CRT (5) are An address will be specified.

The subsequent operation is similar to the above case, when the line counter (7) counts 400, the CRTC (
The display address output from the second address counter (10) is blocked by the buffer (3) and the display address output from the second address counter (10) is applied to the display memory (4) instead. Here, the difference from the above case is that the value first loaded into the first address counter (9) is address 50051, which causes the second address counter (1
0) is address 50051 to address 50100, 50151
CRT (5) in order from address to address 50200, etc.
Outputs the display address where the information displayed on even-numbered lines in the icon display area is stored.

As described above, the image information displayed in the image display area of the CRT (5) is displayed in the icon display area of the CRT (5) according to the display address instruction from the CRTC (2) to the display memory (4). The icon information to be displayed is read out from the display memory (4) alternately for odd and even lines according to the display address instruction from the second address counter (10) to the display memory (4). displayed in each area.

Note that the information displayed on the CRT (5) is not limited to the above example; 2! ! It may also be a combination of similar image information, one image information and its partial enlargement information, etc.Also, latch (6), line counter (7), Nantes gate (8)
, a first address counter (9), and a second address counter (10), it is possible to display not only the above-mentioned two-split display but also three or more splits.

(g) Effects of the Invention According to the present invention, a simple circuit configuration consisting of a CRTC and a second address counter independently generates display addresses suitable for an interlaced scanning type CRT and performs divided display. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram showing main signals in the block diagram. (2)...CRTC, (3)...buffer, (4)
...Display memo, (6)...Latch, (7)...
- Line counter, (9)...first address counter, (10)...second address counter.

Claims (1)

[Claims] (1) A display control circuit that displays at least two types of information in a display memory on an interlaced scanning CRT, including a display address, a vertical synchronization signal, a horizontal synchronization signal, a display cycle signal, and a first/second field. a display control signal generation circuit that outputs an identification signal; a latch that holds a division line value that divides the CRT screen into at least two display areas; and a division line value that is loaded from the latch in synchronization with the vertical synchronization signal. After that, a line counter for counting the horizontal synchronizing signal and a starting address of the first line or the second line of the one divided display area based on the state of the first/second field identification signal are used. A first address counter that loads the first address of the line in synchronization with the vertical synchronization signal and counts up by two by applying the display cycle signal, and loads the contents of the first address counter in synchronization with the horizontal synchronization signal. and a second address counter that counts up by one in response to the application of the display cycle signal, and a buffer that selectively supplies the display address output from the display control signal generation circuit to the display memory; Until the count value reaches a value corresponding to the division position, the buffer causes the display address outputted from the display control signal generation circuit to be given to the display memory, and the count value of the line counter reaches the division position. When the corresponding value is reached, the buffer prevents the display address outputted from the display control signal generation circuit from being applied to the display memory and sends the display cycle signal to the first address counter and the second address counter. A display control circuit in an interlaced scanning system, characterized in that the display control circuit is configured to supply the contents of the second address counter to the display memory.