JPH01158813A - Fm demodulation circuit - Google Patents

Fm demodulation circuit

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Publication number
JPH01158813A
JPH01158813A JP62317120A JP31712087A JPH01158813A JP H01158813 A JPH01158813 A JP H01158813A JP 62317120 A JP62317120 A JP 62317120A JP 31712087 A JP31712087 A JP 31712087A JP H01158813 A JPH01158813 A JP H01158813A
Authority
JP
Japan
Prior art keywords
circuit
output
equalizer
delay
demodulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62317120A
Other languages
Japanese (ja)
Inventor
Youchiyou Sou
曜暢 荘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP62317120A priority Critical patent/JPH01158813A/en
Publication of JPH01158813A publication Critical patent/JPH01158813A/en
Pending legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Television Signal Processing For Recording (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To realize FM one side band demodulation with no group delay caused therein within a required FM band by adopting the transversal equalizer+double limiter constitution so as to prevent inversion while applying FM equalization. CONSTITUTION:An equalizer circuit 8 consists of delay circuits 11, 12, adder circuits 9, 16, attenuators 13, 14, and a subtraction circuit 15. The delay is made constant in all frequency bands in the equalizer circuit 8 and FM equalization is applied without group delay. Then a high frequency component (k) extracted by the subtraction circuit 15 (cos equalizer) and passing through the 1st limiter circuit 3 and a low frequency component l extracted by the adder circuit 16 (-cos equalizer) and an LPF 5 are summed by an adder circuit 6, and the output signal (m) being the result of addition is given to the 2nd limiter circuit 7 to obtain an FM demodulation signal (n) with frequency equalization without any group delay. Thus, the group delay distortion in a required FM band is decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はFM復調回路に係り、特に、片サイドバンド復
調に効果的なFM復調回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM demodulation circuit, and particularly to an FM demodulation circuit that is effective for single-sideband demodulation.

〔従来の技術〕[Conventional technology]

VTR(ビデオチープレコータ)等の磁気記録再生装置
に備えられている従来のFM復調回路の信号処理におい
ては、磁気ヘッドにより磁気記録媒体から読み取られた
再生FM信号の上下側帯波にアンバランスがあると、ビ
デオ信号の黒から白への急激な立上がりのある高周波成
分の多い部分のFM信号波形は、その一部が0レベルに
達しないで振動するように歪んでしまう。これをそのま
まリミッタにかけると、情報を持ったゼロクロス点が欠
落して等価的に黒レベルに落ち込んだ波形として復調さ
れてしまう。これを「反転現象」と呼んでおり、以下そ
の発生の原理について第3図を参照しながら説明する。
In the signal processing of conventional FM demodulation circuits installed in magnetic recording and reproducing devices such as VTRs (video recorders), there is an imbalance between the upper and lower sidebands of the reproduced FM signal read from the magnetic recording medium by the magnetic head. If this happens, the FM signal waveform of a portion of the video signal with many high-frequency components, where there is a sudden rise from black to white, will be distorted so that part of it does not reach the 0 level and oscillates. If this is applied to a limiter as it is, the zero-crossing points that carry information will be missing and the waveform will be demodulated as equivalently falling to the black level. This is called a "reversal phenomenon," and the principle of its occurrence will be explained below with reference to FIG.

第3図(^)の波形aは入力ビデオ信号で、黒から白へ
急激に変化している部分を示している。これをビデオエ
ンファシス回路(図示せず)にかけると、波形の立上が
り部分(ここに高周波成分が集中している)に、同図(
B)に示すようなスパイク(オーバーシュート)を生じ
る。このような波形a′のFM変調器出力は同図(D)
に示すように、スパイク部分のゼロクロス点の間隔が急
に狭くなった波形pとなる。これを磁気テープ等の磁気
記録媒体に記録した後再生すると、記録、再生のメカニ
ズムにより、再生波形は同図(E)に示すように歪んで
しまう。これは記録、再生の過程で下側帯波成分が強調
されるのに対し、上側帯波成分は抑圧されるために起こ
るもので、時には図示の如く波形qの一部がゼロレベル
に達しないで振動するように歪むこともある。これをそ
のitリミッタにかけると、情報を持ったゼロクロス点
が欠落して、見かけ上ゼロクロス点の間隔が拡がったよ
うになるので、復調後の波形はa′のようにはならず、
同図(C)に示すように本来白レベルであるべき所か黒
レベルに落ち込んでしまい、反転現象を起こすわけであ
る。
Waveform a in FIG. 3(^) is the input video signal and shows a portion where there is a sudden change from black to white. When this is applied to a video emphasis circuit (not shown), the rising part of the waveform (where high frequency components are concentrated) is
A spike (overshoot) as shown in B) occurs. The FM modulator output of such a waveform a' is shown in the same figure (D).
As shown in the figure, the waveform p becomes such that the interval between the zero crossing points of the spike portion suddenly becomes narrower. If this is recorded on a magnetic recording medium such as a magnetic tape and then reproduced, the reproduced waveform will be distorted as shown in FIG. 3(E) due to the recording and reproduction mechanism. This occurs because the lower sideband components are emphasized during the recording and playback process, while the upper sideband components are suppressed. Sometimes, as shown in the figure, part of the waveform q does not reach the zero level. It can also become distorted, like it vibrates. When this is applied to the IT limiter, zero-crossing points with information are lost, and the interval between the zero-crossing points appears to be widened, so the waveform after demodulation will not be like a'.
As shown in FIG. 3C, the white level falls to the black level where it should be, causing an inversion phenomenon.

特に、ビデオエンファシスをかけた場合には、波形の立
上がり部分にスパイクを生じる(同図(B)参照)ので
、この現象が生じ易くなる。そこで、最近の家庭用VT
R装置ではエンファシス量を大きくしても反転現象を起
こさないようにする対策が種々(例えばDL−FM方方
式及反転防止路。
In particular, when video emphasis is applied, a spike occurs at the rising edge of the waveform (see (B) in the same figure), so this phenomenon is likely to occur. Therefore, recent home VT
In the R device, there are various measures to prevent the reversal phenomenon even if the emphasis amount is increased (for example, the DL-FM method and the reversal prevention path).

ノンリニアエンファシス(non−linear en
phasis)方式等)考えられている。
non-linear emphasis
phasis method, etc.) are being considered.

DL−FM方式の“’DL”はダブルリミッタ(Dou
ble Lin+1ter) ノ略で、リミッタを二重
ニかけることにより反転現象を防ぎ、ビデオエンファシ
スを充分に行なってSN比を改善しようというものであ
る。DL−FMM式FM復調回路1の具体的な回路ブロ
ック図は第2図に示す如きものであり、この図において
2はHPF (高域濾波器)、4は位相補正回路、3及
び7は夫々第1.第2のリミッタ回路、5はLPF (
低域濾波器)、6は加算回路である。
“'DL” in the DL-FM system is a double limiter (Dou
This is an abbreviation for ble Lin+1ter), which aims to prevent the reversal phenomenon by applying a double limiter and improve the SN ratio by sufficiently applying video emphasis. A specific circuit block diagram of the DL-FMM type FM demodulation circuit 1 is as shown in FIG. 2, in which 2 is an HPF (high pass filter), 4 is a phase correction circuit, and 3 and 7 are respectively 1st. The second limiter circuit, 5 is an LPF (
6 is an adder circuit.

前置増幅器(図示せず)より入力端子Inに供給された
波形qの如き再生FM信号は、HPF2により映像信号
の中域から高域に相当する下側帯波の成分を除去するこ
とによって、波形r(第3図(G)参照)のようなゼロ
クロス点の欠落しない波形にした後、第1リミッタ回路
3で振幅を揃えた(搬送波近傍のノイズを除去した)波
形S(同図(H)参照)にする。次にHPF2による位
相歪を位相補正回路4で補正し、これにLPF5の出力
信号である下側帯波U(同図(F)参照)を加算回路6
において加えることにより歪を除いたFM信号t(同図
(1)参照)として復元し、これを第2のリミッタ回路
7に通してFM復調している。このような信号処理を行
なうことにより、SN比を3dB以上改善できる。
The reproduced FM signal with waveform q supplied from the preamplifier (not shown) to the input terminal In is converted into a waveform by removing the lower sideband component corresponding to the middle to high range of the video signal by the HPF2. After creating a waveform with no missing zero-crossing points like r (see Figure 3 (G)), the first limiter circuit 3 equalizes the amplitude (removes noise near the carrier wave) and creates a waveform S (see Figure 3 (H)). ). Next, the phase distortion caused by the HPF 2 is corrected by the phase correction circuit 4, and the lower sideband wave U (see (F) in the same figure) which is the output signal of the LPF 5 is added to this by the addition circuit
The signal is added to the FM signal t to restore the distortion-free FM signal t (see (1) in the same figure), which is then passed through the second limiter circuit 7 for FM demodulation. By performing such signal processing, the SN ratio can be improved by 3 dB or more.

C本発明が解決しようとする問題点〕 斜上の如き従来回路1においては、HPF2とLPF5
を用いて周波数分割を行なっているので、クロスポイン
トの群遅延歪を押さえるために位相補正回路4が必要で
あり、所要帯域全体に亙って遅延歪を押さえるのは困難
である6又、HPF2゜LPF5各々のロールオフ特性
が異なっていると、クロスポイント近辺での周波数特性
に歪が発生するという問題がある。
C Problems to be Solved by the Present Invention] In the conventional circuit 1 as shown above, HPF2 and LPF5
Since frequency division is performed using If the roll-off characteristics of each of the LPFs 5 are different, there is a problem that distortion occurs in the frequency characteristics near the cross point.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記諸問題点を解消するために、入力信号を
所定の時間遅延させる第1の遅、延回路と。
In order to solve the above-mentioned problems, the present invention provides a first delay circuit that delays an input signal by a predetermined time.

第1の遅延回路の出力信号を更に同一遅延時間遅延させ
る第2の遅延回路と、第2の遅延回路の出力信号と上記
入力信号とを混合する第1の加算回路と、第1の加算回
路の出力を所定量減衰させる第1の減衰器と、第1の遅
延回路の出力より第1の減衰器の出力を減算する減算回
路とにより−cosイコライザを構成して入力信号をF
M等化し、同様に第1の加算回路の出力を所定量減衰さ
せる第2の減衰器と、第1の遅延回路の出力より第2の
減衰器の出力を加算する第2の加算回路とによりcos
イコライザを構成して入力信号をFM等化し、上記−c
osイコライザの出力の振幅を制限する第1のリミッタ
回路と、cosイコライザの出力信号のうち低域成分の
みを通過させる低域−波器と、低域濾波器及び第1のリ
ミッタ回路の出力を混合する第3の加算回路と、第3の
加算回路の出力の振幅を制限する第2のリミッタ回路と
を更に具備するく即ちトランスバーサルイコライザ+ダ
ブルリミッタとする)ことによって、FM所要帯域内に
おいて群遅延歪を押さえて反転を防止した片サイドバン
ド復調を実現するよう構成した。
a second delay circuit that further delays the output signal of the first delay circuit by the same delay time; a first addition circuit that mixes the output signal of the second delay circuit with the input signal; and a first addition circuit. A -cos equalizer is configured by a first attenuator that attenuates the output of F by a predetermined amount, and a subtraction circuit that subtracts the output of the first attenuator from the output of the first delay circuit.
M equalization, and a second attenuator that similarly attenuates the output of the first addition circuit by a predetermined amount, and a second addition circuit that adds the output of the second attenuator to the output of the first delay circuit. cos
Configure an equalizer to FM equalize the input signal, and -c
A first limiter circuit that limits the amplitude of the output of the OS equalizer, a low-frequency filter that passes only low-frequency components of the output signal of the COS equalizer, a low-pass filter, and the output of the first limiter circuit. By further comprising a third adder circuit for mixing and a second limiter circuit for limiting the amplitude of the output of the third adder circuit (i.e., transversal equalizer + double limiter), within the required FM band. It is configured to realize single sideband demodulation that suppresses group delay distortion and prevents inversion.

〔実施例〕〔Example〕

本発明のFM復調回路においては、上述の如くトランス
バーサルイコライザ士ダブルリミッタなる構成にし、F
M等化をしながら反転を防止し、群遅延の生じないFM
片ササイドバンド復調所要FMM域内で実現したもので
あり、以下第1図を参照しながら、本発明のFM復調回
路の一実施例について説明する。第1図は本発明のFM
復調回路10の主要部のブロック構成図である。この図
において、第2図に示した従来例と同一構成要素には同
一符号を付して、その詳細な説明を省略する。図中、1
1.12は遅延回路、9及び16は加算回路、13.1
4は減衰器、15は減算回路であり、以上の構成により
イコライザ回路8を構成している。
The FM demodulation circuit of the present invention has a transversal equalizer and double limiter configuration as described above, and
FM that prevents inversion while performing M equalization and does not cause group delay.
This is realized within the FMM range required for one sideband demodulation, and an embodiment of the FM demodulation circuit of the present invention will be described below with reference to FIG. Figure 1 shows the FM of the present invention.
1 is a block configuration diagram of the main parts of a demodulation circuit 10. FIG. In this figure, the same components as those in the conventional example shown in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted. In the figure, 1
1.12 is a delay circuit, 9 and 16 are adder circuits, 13.1
4 is an attenuator, 15 is a subtraction circuit, and the above configuration constitutes the equalizer circuit 8.

次に、FM復調回路10の動作原理について、第1図及
び第4図以降を併せ参照しながら説明する。FM復調回
路10の入力端子Inに供給されるWt 入力信号aを a=E e   、遅延回路11.12
の遅延時間をτとすると、遅延回路11.12の出力信
号す、cは、夫々 b=Ee”  (を十τ) 、 C−E e jW(t
+2τ)で表される。従って、加算回路9の出力dはd
=a十c=E(6十ejW(t+2r)。
Next, the principle of operation of the FM demodulation circuit 10 will be explained with reference to FIG. 1 and FIGS. 4 onwards. The Wt input signal a supplied to the input terminal In of the FM demodulation circuit 10 is a=E e , and the delay circuit 11.12
Assuming that the delay time of
+2τ). Therefore, the output d of the adder circuit 9 is d
=a0c=E(60ejW(t+2r).

wt =E e jW (を十τ )       −jwτ
    JWτ +(e    十e =2EejvI”” Gos wτ・・・・・・・・・
・・・・・・・・・(1)となる。
wt = E e jW (10τ) −jwτ
JWτ + (e 10e = 2EejvI”” Gos wτ・・・・・・・・・
......(1).

減衰器13.14の減衰率を夫々α、β(通常α、β≦
寺)とすれば出力elfは e=2aEe jw ”十τ ) cos  w v 
−0−−0−−−−11,−(2)f=2βE e j
w(t+f)CO8w τ−−−−−−−−−−−−−
−−(3)となるので、減算回路15及び加算回路16
の出力g、hは夫々 g=b−e=Ee”(t″″) 一2aEe””τ)cosw’r =E (1−2a C03wτ) e”(t+”−(4
)h=b+t=Eejv4(t+f) +2βE e ” (t+” )CO8Wτ=F、(1
+2βcoswτl e jW4(j ” r ) +
++ (1)となるわけである、第(4)式から減算回
路15の出力信号に関して次のことがわかる。
The attenuation factors of attenuators 13 and 14 are α and β (usually α, β≦
temple), then the output elf is e=2aEe jw ”10τ) cos w v
−0−−0−−−−11,−(2)f=2βE e j
w(t+f)CO8w τ−−−−−−−−−−−−
--(3), so the subtraction circuit 15 and the addition circuit 16
The outputs g and h of are respectively g=be-e=Ee"(t"")-2aEe""τ)cosw'r=E (1-2a C03wτ) e"(t+"-(4
) h=b+t=Eejv4(t+f) +2βE e ” (t+” )CO8Wτ=F, (1
+2βcoswτl e jW4(j ” r ) +
++ (1) From equation (4), the following can be seen regarding the output signal of the subtraction circuit 15.

O出力信号は入力信号に対して時間遅れを持つが位相歪
は全くない。
Although the O output signal has a time delay with respect to the input signal, there is no phase distortion at all.

0振幅(ゲイン)についての周波数特性は第4図のよう
になる。
The frequency characteristics for zero amplitude (gain) are as shown in FIG.

このような特性をcos (コサイン)特性と呼ぶ。Such characteristics are called cos (cosine) characteristics.

同様に第(0式からは、加算回路16の出力信号も入力
信号に対して時間遅れをつが位相歪は全くなく、振幅に
ついての周波数特性は第5図のような−cos特性とな
る。
Similarly, from equation (0), the output signal of the adder circuit 16 also has a time delay with respect to the input signal, but there is no phase distortion at all, and the frequency characteristic with respect to amplitude becomes a -cos characteristic as shown in FIG.

遅延時間がτのイコライザの中心周波数チ。(W=2π
チC)は チ。=1/2τで表わされる。このイコライ
ザ回路8においては、遅延は全周波数帯域とも一定とな
り、群遅延なくFM等化できるわけである。減算回路1
5の出力信号、即ちイコライズされたFM波の特性は、
前述の如く第4図のようになるので、伝達関数は y1=−αχ(1+zド’)+2ZT−’)より、 Hl(jω)= (1−2acosθ)ε−jθ・・・
■但し、zT−’ = 1 / 2 fc (遅延量)
θ =  2  x  f  /  2  fc −π
 f /チC第■式から明瞭な如く、振幅(1−2αc
osθ)及び位相ε−joより群遅延なく チ。を中心
周波数とした一cos等化カーブとなり、かかる波形の
信号gが第1リミッタ回路3に供給される。持ち上げ量
は減衰器13の利得(ゲイン)αによって制御され、こ
れが高域成分加算量となる。
Center frequency chi of an equalizer with delay time τ. (W=2π
ChiC) is Chi. =1/2τ. In this equalizer circuit 8, the delay is constant over the entire frequency band, and FM equalization can be performed without group delay. Subtraction circuit 1
The characteristics of the output signal of No. 5, that is, the equalized FM wave, are:
As mentioned above, the transfer function is as shown in Figure 4, so from y1=-αχ(1+zdo')+2ZT-'), Hl(jω)=(1-2acosθ)ε-jθ...
■However, zT-' = 1/2 fc (delay amount)
θ = 2 x f / 2 fc - π
As is clear from the formula (■), the amplitude (1-2αc
osθ) and phase ε-jo, there is no group delay. A signal g having such a waveform is supplied to the first limiter circuit 3. The amount of lift is controlled by the gain α of the attenuator 13, and this becomes the amount of high-frequency component addition.

また、加算回路16の出力信号(FM波)hの特性は第
5図のようになる。即ちその伝達関数はy2=βx (
1+ZT−’ ) +x Z7−’ )より、 H2(jω)=(1+2βcosθ)ε−jθ・・・■
但し、θ−πf/f。
Further, the characteristics of the output signal (FM wave) h of the adder circuit 16 are as shown in FIG. That is, the transfer function is y2=βx (
1+ZT-') +x Z7-'), H2(jω)=(1+2βcosθ)ε-jθ...■
However, θ−πf/f.

第■式から明白な如く、振幅(1+2βcosθ)及び
位相ε−joより群遅延なく  f、を中心周波数とし
なcos等化カーブとなり、かかる波形の出力信号りを
、周波数t0をカットオフポイントとする通過帯域内で
群遅延補正されたLPF5を通すことにより、第6図の
曲線Eの如き周波数特性として(曲線Bは第4図と同じ
もの)低域成分となる。
As is clear from equation (2), the amplitude (1+2β cos θ) and the phase ε-jo result in a cos equalization curve with the center frequency set at f without group delay, and the output signal of such a waveform is set at the frequency t0 as the cutoff point. By passing the signal through the LPF 5 which has undergone group delay correction within the pass band, it becomes a low-frequency component with frequency characteristics as shown by curve E in FIG. 6 (curve B is the same as in FIG. 4).

なお、低域成分加算量は、減衰器14における利得βに
よって制御される。即ち、減算回路15(cosイコラ
イザ)によって抽出されたのち第1リミッタ回路3を通
過した高域成分にと、加算回路16(−cosイコライ
ザ)と周波数t。をカットオフポイントとするLPF5
によって抽出されな低域成分iとを加算回路6にて加え
合わせ、加算回路6の出力信号mを更に第2リミッタ回
路7を通すことによって、周波数等化された群遅延の無
いFM復復調信号炉得られ、後段のFM検波器(図示せ
ず)等に出力される。このように、周波数等化された群
遅延の無いダブルリミッタ回路を、所要FM帯域内で構
成できるものである。
Note that the amount of low-frequency component addition is controlled by the gain β in the attenuator 14. That is, the high-frequency component extracted by the subtraction circuit 15 (cos equalizer) and passed through the first limiter circuit 3, the addition circuit 16 (-cos equalizer), and the frequency t. LPF5 with cutoff point
The adder circuit 6 adds the low-frequency components i extracted by The signal is obtained from the furnace and outputted to a downstream FM detector (not shown) or the like. In this way, a frequency-equalized double limiter circuit without group delay can be constructed within the required FM band.

〔効 果〕〔effect〕

本発明のFM復調回路は以上詳細に説明したように構成
したので、次のような種々の実用的効果を有する。
Since the FM demodulation circuit of the present invention is constructed as described in detail above, it has various practical effects as described below.

■従来のFM復調回路では困難であった、所要FM帯域
内での群遅延歪を小さくすることが可能になった。
■It has become possible to reduce group delay distortion within the required FM band, which was difficult with conventional FM demodulation circuits.

■従来のFM復調回路では、高域成分と低域成分とのク
ロスポイント付近で周波数歪及び群遅延歪を小さくする
ことが困難であったが、本発明回路で可能になった。
(2) In conventional FM demodulation circuits, it was difficult to reduce frequency distortion and group delay distortion near the cross point between high and low frequency components, but this has become possible with the circuit of the present invention.

■トランスバーサルイコライザ+ダブルリミッタ構成と
することにより、回路の簡素化が図れた。
■The circuit can be simplified by using a transversal equalizer + double limiter configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のFM復調回路の主要部のブロック構成
図、第2図は従来の回路図、第3図は従来回路の動作説
明用信号波形図、第4図乃至第6図は本発明回路の動作
説明用信号波形図である。 3・・・第1リミッタ回路、5・・・LPF、6.9゜
16・・・加算回路、7・・・第2リミッタ回路、8・
・・イコライザ回路、10・・・FM復調回路、11.
12・・・遅延回路、13.14・・・減衰器、15・
・・減算回路。 特許出願人  日本ビクター株式会社 = 13− 星3図 第今図 品用図 第6図 手続補正書
Fig. 1 is a block diagram of the main parts of the FM demodulation circuit of the present invention, Fig. 2 is a conventional circuit diagram, Fig. 3 is a signal waveform diagram for explaining the operation of the conventional circuit, and Figs. FIG. 3 is a signal waveform diagram for explaining the operation of the inventive circuit. 3... First limiter circuit, 5... LPF, 6.9°16... Adder circuit, 7... Second limiter circuit, 8...
. . . Equalizer circuit, 10 . . . FM demodulation circuit, 11.
12...Delay circuit, 13.14...Attenuator, 15.
...Subtraction circuit. Patent Applicant: Victor Company of Japan = 13- Star 3 Diagram Current Illustration 6 Procedural Amendment

Claims (1)

【特許請求の範囲】[Claims]  FM変調信号を復調するFM復調回路において、入力
信号を所定の時間遅延させる第1の遅延回路と、該第1
の遅延回路の出力信号を更に同一遅延時間遅延させる第
2の遅延回路と、該第2の遅延回路の出力信号と上記入
力信号とを混合する第1の加算回路と、該第1の加算回
路の出力を所定量減衰させる第1の減衰器と、上記第1
の遅延回路の出力より該第1の減衰器の出力を減算する
減算回路とにより−cosイコライザを構成して上記入
力信号をFM等化し、同様に上記第1の加算回路の出力
を所望の量だけ減衰させる第2の減衰器と、上記第1の
遅延回路の出力より該第2の減衰器の出力を加算する第
2の加算回路とによりcosイコライザを構成して上記
入力信号をFM等化し、上記−cosイコライザの出力
の振幅を制限する第1のリミッタ回路と、上記cosイ
コライザの出力信号のうち低域成分のみを通過させる低
域濾波器と、該低域濾波器及び上記第1のリミッタ回路
の出力を混合する第3の加算回路と、該第3の加算回路
の出力の振幅を制限する第2のリミッタ回路とを更に具
備することによって、FM所要帯域内において群遅延歪
を押さえて反転を防止した片サイドバンド復調を実現す
るよう構成したことを特徴とするFM復調回路。
An FM demodulation circuit that demodulates an FM modulation signal includes a first delay circuit that delays an input signal by a predetermined time;
a second delay circuit that further delays the output signal of the delay circuit by the same delay time; a first addition circuit that mixes the output signal of the second delay circuit with the input signal; and the first addition circuit. a first attenuator that attenuates the output of the first attenuator by a predetermined amount;
A subtraction circuit that subtracts the output of the first attenuator from the output of the delay circuit constitutes a -cos equalizer to FM equalize the input signal, and similarly adjusts the output of the first addition circuit to a desired amount. A cos equalizer is configured by a second attenuator that attenuates the input signal by a second attenuator, and a second addition circuit that adds the output of the second attenuator to the output of the first delay circuit to FM equalize the input signal. , a first limiter circuit that limits the amplitude of the output of the -cos equalizer; a low-pass filter that passes only low-frequency components of the output signal of the cos equalizer; By further comprising a third adder circuit that mixes the output of the limiter circuit and a second limiter circuit that limits the amplitude of the output of the third adder circuit, group delay distortion can be suppressed within the required FM band. An FM demodulation circuit characterized in that the FM demodulation circuit is configured to realize one sideband demodulation that prevents inversion.
JP62317120A 1987-12-15 1987-12-15 Fm demodulation circuit Pending JPH01158813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62317120A JPH01158813A (en) 1987-12-15 1987-12-15 Fm demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62317120A JPH01158813A (en) 1987-12-15 1987-12-15 Fm demodulation circuit

Publications (1)

Publication Number Publication Date
JPH01158813A true JPH01158813A (en) 1989-06-21

Family

ID=18084659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62317120A Pending JPH01158813A (en) 1987-12-15 1987-12-15 Fm demodulation circuit

Country Status (1)

Country Link
JP (1) JPH01158813A (en)

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