JPH01155433A - Size comparing circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution, to reduce the quantity of hardware, and to lower a cost by unifying a comparator to check whether or not an inputted unknown number is within a regulated range and a decision circuit. CONSTITUTION:On registers 1 and 3, a lower limit value A of (n) bits and an upper limit value B of the same bits are set, respectively. And on a register 2, an unknown value X of (n) bits is set. Those values A, B, and X are inputted from the registers 1-3 to the decision circuit 8, respectively. Assuming the lower limit value A as A0, A1...An, the upper limit value B as B0, B1...Bn, and the unknown value X as X0, X1...Xn, the circuit 8 executes decision whether all of the high-order bits A0, B0, and X0 are 1s or 0s, whether or not the A0 and X0 are 0s and the B0 is 1, and whether or not the A0 is 0 and the X0 and B0 and 1s by an exclusive NOR and an OR. When all of the A0, X0, and B0 are 1s or 0s, the decision whether all of the A1, X1, and B1 are 1s or 0s, whether or not the A1 and X1 are 0s and the B1 is 1, and whether or not the A1 is 0 and the X1 and B1 are 1s are performed by the exclusive NOR and the OR, and a decision operation of A<X<B is repeated.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a magnitude comparison circuit configured with a small amount of hardware when determining whether an unknown value manually generated is within a predetermined range of magnitude values, which simplifies the circuit configuration. In order to reduce costs and improve reliability, we set a register with a lower limit value A and an upper limit value B consisting of n bits, and an unknown value X consisting of n bits. This is a circuit that compares values that are simultaneously input from registers and determines whether A<X<B, and whether the most significant bits of the upper limit value, lower limit value, and unknown value are all "0" or "1". The lower limit value and unknown value are “
0" and the upper limit is "l", and the lower limit is "0".
” to determine whether the unknown value and the upper limit value are “1” at the same time, and if they are all “0” or “1”, repeat the same determination as above for the next lower bit. , if the lower limit value and unknown value are “0” and the upper limit value is “1”, it is necessary to determine whether the lower limit value and unknown value of the next lower bit are both “0” or “1”, and the lower limit value is “1”. It is determined whether the unknown value is “1” at “0”, and the lower limit is “O” and the unknown value and upper limit are “1”.
”, determine whether the unknown value and upper limit value of the next lower bit are both “O” or “1”, and determine whether the unknown value is “0” and the upper limit value is “1”. The configuration includes a comparison and determination circuit that determines whether A<X<B by repeating the operations to be performed.

[Industrial Application Field] The present invention relates to a magnitude comparison circuit that can be configured with a small amount of hardware when determining whether an input unknown value is within a predetermined range of magnitude values.

In an information processing device, a magnitude comparison circuit is used to check whether an input unknown number is within a specified range. Such a magnitude comparison circuit compares a predetermined upper limit value for -i with an unknown value, further compares a lower limit value with an unknown value,
Based on the results of both comparisons, it is determined whether there is an unknown value within the range indicated by the upper and lower limits.

It is desirable that such a magnitude comparison circuit has a small amount of hardware and high reliability.

[Conventional technology]

FIG. 5 is a block diagram illustrating a conventional technique.

A predetermined lower limit value A is set in register 1, and a predetermined upper limit value B is set in register 3. Then, an unknown value X is set in register 2.

Comparison circuit 4 compares value A of register 1 and value X of register 2, and if value X of register 2 is larger than value A of register 1, it sends out "1", otherwise it sends out "0".

The comparison circuit 5 compares the value B of the register 3 and the value X of the register 2, and if the value X of the register 2 is smaller than the value B of the register 3, it sends out "1", and if it is not smaller, it sends out "0".

The determination circuit 6 sets the flip-flop 7 when both the comparison circuits 4 and 5 send out "1'". Therefore, flip-flop 7 sends out a "1" and sends out the result that A<X<B.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, comparison circuits 4 and 5 with the same content are required, and judgment circuit 6 makes a judgment based on the results of comparison between comparison circuits 4 and 5, resulting in a complex circuit configuration and a large amount of hardware. There are problems in that the cost increases and the reliability decreases.

In view of these problems, the present invention aims to reduce costs and improve reliability by integrating a comparison circuit and a judgment circuit into one, simplifying the circuit configuration and reducing the amount of hardware. The purpose is

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

A predetermined n-bit lower limit value A is set in register l, and a predetermined n-bit upper limit value B is set in register 3. Then, an n-bit unknown value X is set in the register 2, and each value of A, B, and

In this case, the lower limit value A is ^. , A1. 82+ '-9A6
and the upper limit B is Bo, 81. B2.・-・、B、
, and the unknown value X is Xo, L, Xz, ...
,
Determining whether Xo and Bo are all “1” or “0′”, determining whether 80 and xo are “0” and 80 is “1”, and determining whether 80 is “0” and Xo and 80 are Execute exclusive NOR and logical OR to determine whether both are "1", Ao, L.

When Bo is all “1” or “O”, it is determined whether the next bits, namely AI, X, B, are all @1” or “0”, and A1 and XI are “0”. The operation of determining whether B is "1" when A1 is "0" and determining whether both χ1 and B are "1" when A1 is "0" is repeated using exclusive NOR and logical sum.

Also, when 80 and xo are "0" and 80 is 11", use exclusive NOR to determine whether the next bit, ^1.X, is both "1" or O. is “0” and Xl is “1”
Judgment is made using logical product, and the logical sum of these results in 8.

It is determined that 80 is "0" and xo and 80
When both are “1”, determine whether L and B+ are both “1” or “0” using exclusive NOR, and if XI is “0”, 8
Determine whether 1 is "1" by logical product, determine that Xl is smaller than 81 by the logical sum of this, obtain the first magnitude determination result, and if A<X<B, "1" is sent to set the flip-flop 7.

Also, as mentioned above, it is necessary to determine whether AI+ xIn Bl are all "l" or "0", and whether A1 and xl are "0" and B is "1".
”, A is “0” and ×1 and B are both “1”
A1 and Xl are "O" and 8. is “1′”
When , it is determined whether Az and Xz are both "1" or "o", and whether A2 is "0" and X2 is "1", and by the logical sum of these, If 8 is "0" and xl and 81 are both "l", determine whether Xz and Bg are both "1" or "0".
Determine whether X2 is "0" and 82 is "1", and by logical sum of these, determine that X2 is smaller than 82, obtain the next stage size determination result, and if A<X<B Sends "1" and sets the flip-flop 7.

The comparison and determination circuit 8 determines whether the n-bit unknown value X is between the lower limit value A and the upper limit value B by stacking such determination circuits.

The logical formula of the comparison/judgment circuit 8 configured as described above is the second
The result will be as shown in the figure.

In FIG. 2, = indicates exclusive NOR, . indicates logical product, and 10 indicates logical sum. Therefore, for example, Ao=Xo
=Bo is exclusive NOR circuit T: Ao, Xo, B.

It is determined whether each bit is all “O” or “1”.
xo・Bo is an AND circuit with 80 and χ. It is determined whether ``0'' and 80 are ``1'', and Ao''
In the D circuit, 80 is “O” and X. It is determined whether or not Bo is "1".

Each bit of Ao, Xo, Bo is all “0” or “
If 80 and Xo are "0" and 80 is "1" instead of "1", it turns out that xo is smaller than 80. In this case,
^. Since it is impossible for xo and 80 to both be "l" when xo is "0", it is determined whether xo is greater than 80 or not based on the state of the next bit.

That is, whether At and Xl are both "0" or "1", and 8 is "
0" and xl is "1", it becomes clear that A is smaller than X.

That is, in A, −X, ^ is “0” and X is “
If it is 1'', X is larger than A, and the condition of A<X<B is obtained, so 1'' is sent from the AND circuit, and the comparison judgment circuit 8 determines the size at the lowest stage. Sends the judgment result.

At this time, each bit of AI and Xt is “0” or “1”
If so, since it is not possible to judge the size here, the judgment will be made based on the state of the third bit. In other words, i "・Since FL is larger than C, X, and C and the condition of A<X<B is obtained, "1" is sent from the AND circuit.

In this way, judgment is made sequentially based on the state of the lower bits,
Finally, the condition for determining whether each bit of A 6-1, X, etc. is both “0” or “1” is that Afi is “0” and Add a condition for determining whether it exists.

AO+ 〇 is “0” and X. Determine whether both B. and B. are “1”. 8. is “0” and X
If o is "1", xo is 8. Although it is larger than Bo, it is unknown whether it is smaller than Bo, and it is determined based on the state of the next bit.

That is, in TeB1, xl is “0” and 81 is “1”
If so, Xl is smaller than A1, and the condition of A<X<B is obtained, so "1" is sent from the AND circuit, and the comparison judgment circuit 8 sends out the judgment result of size in a small number of steps. do.

However, if each bit of L and B+ is “0′” or “l”
If so, since the magnitude cannot be determined here, the determination will be made based on the state of the third bit. That is, if x2 is "0" and 81 is "1" in X2·B2, xt is B.

Since the condition of A<X<B is obtained, "1" is sent from the AND circuit.

In this way, judgment is made sequentially based on the state of the lower bits,
The last bit is X, , + which is one higher than the least significant bit.

A condition for determining whether x7 is 0 and 87 is 1 is added to the conditions for determining whether each bit of +Bn-1 is both "0" or "1".

^. , Each bit of XI BO is all “0” or 1″
If At
, L, and B+ are all “0” or “1”, and each bit of At, L, and B+ is all “0” or “1”.
If it is not “0” or “1”, judge the size in the same way as above, but if each bit of At, X+, B+ is all “0” or “l”, then the next bit Judgment is made in the state of .However, A q, -1+ Xn-2+
If all bits of 86-t are "0" or 11'", in determining the magnitude of the least significant bit and the next higher bit, the bits of A n- and X.-1 are " 0″
Then, the conditions for determining whether the bit of B f, -1 is "1", the bit of 80 is "0" and the bit of X7 is "l", and the condition that determines whether the bit of B f, -1 is "O" So X9-1 and B. -1 bit is “1” or X7 bit is “0” and 87
This is the condition for determining whether the bit of is “1”.

[Effect]

By configuring as described above, the comparison judgment circuit 8 can judge whether there is an unknown value input from register 2 between the upper limit value and lower limit value input from registers 1 and 3. Therefore, there is no need to use two comparison circuits with the same content, and the circuit configuration can be simplified, cost can be reduced, and reliability can be improved.

〔Example〕

FIG. 3 is a block diagram of a circuit showing one embodiment of the present invention.
FIG. 4 is a diagram illustrating the operational logic of FIG. 3.

FIG. 3 is a detailed block diagram of the comparison/judgment circuit 8 shown in FIG. 1, and shows the case where the n bits are 4 bits. register l
Each bit from 80 to ^3 is connected to terminal 80 to a3, and each bit from register 2 to X0 to X is connected to terminal X.

~x3, each bit of register 3 to 80~B3 is input to terminals b0~b, respectively.

At Ao= shown in FIG. =8. is exclusive NOR circuit 30
A + = X t = [1t is executed in the exclusive NOR circuit 44, At ・Xg ・Rt
'A:I' Xs is NOT circuit 10.12.13
It is executed with AND circuit 11.14°15.17, and
×2・B2・Mo・B, is NOT circuit 16 and AND circuit 1
B, 19, 20. Executed at 25.

Also, the stone ・X+-8+ is executed by AND circuits 27 and 43, and Az=Xz ・A3-X5 0Az-Xz is an exclusive NO
It is executed by the R circuit 21, the AND circuit 23, 20, and the OR circuit 24, and A,・×1・B1 is executed by the NOT circuit 46 and the AND
Executed in circuit 47.50, Xz=Ih ・Xs ・B
3+Xz' Bg is executed by exclusive NOR circuit 22, NOT circuit 16, AND circuit 18, 49, and OR circuit 48.

Also, ■・Otsu・Bo is executed by the NOT circuit 34.35 and the AND circuit 33.36, and 81=XI is executed by the exclusive NOR circuit 44''?Ih=Xz・A3−X3+/
h”L is ORed with exclusive NOR circuit 21 and AND circuit 23
is executed in circuit 24, and At”X+ is executed in NOT circuit 46.
and is executed by the AND circuit 47.

Also, Ao, Xo, and Bo are the NOT circuit 34 and the AND circuit 3.
9.40, X, =B, is executed in the exclusive NOR circuit 44, and Xt=Bz ・X, ・Bi+Xz ・
Ilz is executed by an AND circuit 49 and an OR circuit 48, and χ
1.B.

is executed by the NOT circuit 45 and the AND circuit 43.

Here, for example, the lower limit value A is oooo and the upper limit value B is 00.
11, if the unknown value X is 0001, the terminal ao
, "0" is input to XO+be. Therefore, exclusive NOR circuit 30 sends out "1". Also, AND circuit 3
9 sends out "0", so the AND circuit 40 also sends out "0". Furthermore, the NOT circuits 34 and 35 send out "l", but the AND circuit 36 sends out "0" because "0" is input from the terminal b0. Therefore, the AND circuit 33 also sends out O''.

“O” is input to the terminals aI+XI+bl. Therefore, exclusive NOR circuit 44 sends "l" and N(1)
The T circuit 45 sends out "1", but the AND circuit 43 sends out "0".
''.Also, the N07 circuit 46 sends out "1", but the AND circuit 47 sends out "0", so the AND circuit 5
0 also sends "O".

Terminal a2. "0" is input to xi, and "l" is input to terminal b2. Therefore, NOT circuits 12 and 13 send out "1", and AND circuit 14 sends out "1", so AND circuit 15 also sends "1". ”. Therefore, the OR circuit 48 outputs “1
”.Therefore, the AND circuit 42 outputs an exclusive NOR
Since the circuit 44 is sending out "1", it sends "1" to the AND circuit 40 via the OR circuit 41, but the AND circuit 40 sends out "O" as described above.

Also, since the exclusive NOR circuit 22 sends out "0", the AN
D circuit 49 sends out "0'". Further, the exclusive NOR circuit 21 sends out "1". Also, the AND circuit 20 is “0”.
”, and the AND circuits 19.25 also send out “0”.

Terminal a, "0" is terminal x5. 1” is input to b. Therefore, the NOT circuit 10 sends out “1” and
Circuit 11 sends out "1". However, NOT circuit 16
outputs "0", so the AND circuit 18 outputs "0". AND circuit 17 indicates that AND circuits 11 and 15 are "l".
”, “1′ is sent to the AND circuit 28 via the OR circuit 26. Since the exclusive NOR circuit 44 is sending out "1", the AND circuit 28 outputs "l" to the OR circuit 29.
The signal is then sent to the AND circuit 31. Since the exclusive NOR circuit 30 is sending out "1", the AND circuit 31 is ORed.
It sends "l" through circuit 32.

The AND circuit 23 and the AND circuit 11 are exclusive N.

Since the R circuit 21 sends out "1", it sends out "1" to the AND circuit 27 via the OR circuit 24. However, AND
Since the circuit 43 is sending out "0", it sends out "0".

AND circuit 37 includes exclusive NOR circuit 44 and OR circuit 24
“1” is passed through the OR circuit 38 and AN is sent out.
The signal is sent to the D circuit 33, but as described above, the AND circuit 33 sends "0".

〔Effect of the invention〕

As described above, the present invention can simplify the circuit configuration, reduce the amount of hardware, reduce costs, and improve reliability.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a diagram explaining the invention in detail, Fig. 3 is a block diagram of a circuit showing an embodiment of the present invention, and Fig. 4 is the operation of Fig. 3. FIG. 5 is a block diagram explaining the conventional technology. In the figure, 1.2.3 is a register, 4.5 is a comparison circuit, 6 is a judgment circuit, 7 is a flip-flop, 8 is a comparison judgment circuit, and 21.22.30.44 is an exclusive NOR circuit. Prelude F January! '[Bukuchi・So2Q Tei I Q Kaya 4 Figure

Claims (1)

[Claims] Simultaneously from registers (1) and (3) in which a lower limit value A and an upper limit value B consisting of n bits are set, and register (2) in which an unknown value X consisting of n bits is set. A circuit that compares input values and determines A<X<B, and determines whether the most significant bits of the upper limit value, lower limit value, and unknown value are all “0” or “1”. , determining whether the lower limit value and unknown value of the most significant bit are “0” and the upper limit value is “1”;
It is determined whether the lower limit value of the most significant bit is “0” and the unknown value and upper limit value are “1”.
If it is 0 or 1, the same judgment as above is repeated for each bit of the same order from the upper bit to the lower bit, and the lower limit of the most significant bit is determined. If the value and unknown value are “0” and the upper limit value is “1”, the lower limit value and unknown value of the next lower bit are both “
0” or “1” and whether the lower limit value is “0” and the unknown value is “1”. If the value is “1”, the unknown value of the next lower bit and the upper limit value are both “0” or “1”.
By repeating the operation of determining whether the unknown value is "0" and the upper limit value is "1" from the upper bit to the lower bit for each bit of the same order, A< X
A magnitude comparison circuit characterized in that a comparison determination circuit (8) for determining whether or not <B is provided.