JPH01152868A - Picture processor - Google Patents

Abstract

PURPOSE:To improve the picture quality at the reduction processing by comparing an interleaved line with a preceding or a succeeding line in case of line interleaving and implanting the black data of the interleaved line to the compared line so as to prevent missing of the black data of the interleaved line thereby preventing the missing of thin lines in subscanning direction. CONSTITUTION:A line memory 50 has a capacity storing a picture data by one line at nonmagnification and gives an output sequentially to a subscanning processing circuit 30 via a bus 13, a buffer circuit 40 and a bus 14 from the head picture element data stored in advance when the picture data (picture element data) is received from the subscanning processing circuit 30. In case of applying line interleaving, the subscanning processing circuit 30 outputs the picture data received from the line memory 50 as an output picture data and compares the picture data with the picture data inputted from a main scanning processing circuit 20 to implant the black data on the interleaved line as the picture data of the compared line and stores the picture data subject to implant processing to the line memory 50.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing apparatus, and particularly to an image processing apparatus equipped with an image reduction function.

(Prior Art) In an image processing device, the size of image data changes depending on the intended use of the image data. For example, a facsimile machine that transmits a document as image data and records it on recording paper at the receiving end is limited by the size of the recording paper at the receiving end, and when editing images using a word processor or personal computer, etc. Image data of various sizes are required depending on the editing intention.

Therefore, conventionally, in order to perform image enlargement/reduction processing, 1
In the main scanning direction of the image data for the screen, the pixel data of each line is read repeatedly or thinned out according to the enlargement/reduction ratio, and in the sub-scanning direction, the pixel data of all the lines are read repeatedly or thinned out, and so-called conversion is performed. The above request was met by performing double conversion.

(Problem to be Solved by the Invention) However, in such conventional image processing devices, lines are thinned out in the sub-scanning direction during reduction processing, regardless of the data content of the thinned lines. Therefore, there is a problem in that the image quality deteriorates due to the omission of thin lines in the sub-scanning direction.

(Object of the Invention) Therefore, the present invention eliminates the loss of black data on the thinned out line by comparing the thinned out line with the previous line or the next line and transplanting the black data of the thinned out line to the comparison line. The purpose of this invention is to improve image quality in reduction processing by preventing thin lines and the like from being lost in the sub-scanning direction.

(Structure of the Invention) In order to achieve the above object, the present invention includes pixel thinning means for thinning out pixel data in the main scanning direction, and line thinning means for thinning out lines in the sub-scanning direction, The image processing device performs image reduction processing, wherein the pixel thinning means selects thinned pixel data by comparing it with pixel data before or after the pixel data, and the line thinning means selects thinned pixel data by comparing it with pixel data before or after the pixel data, and the line thinning means selects thinned pixel data by comparing it with pixel data before or after the pixel data. The image processing device is characterized by comparing each pixel data of a line with each pixel data of a line before the line or each pixel data of a line after the line, selecting pixel data to be thinned out, and performing line thinning. It is something to do.

Hereinafter, the present invention will be specifically explained based on examples. 1 to 5 are diagrams showing an embodiment of the present invention, which is applied to a facsimile machine.

In FIG. 1, reference numeral 1 denotes a facsimile machine, and the facsimile machine 1 includes a main body 2, a document table 3 provided above the main body 2 and on which a document is placed, an operating section 4, and a handset 5. The operation unit 4 includes a numeric keypad 4a, operation keys 4b for inputting other commands, and a display unit 40 for displaying input commands and information transmitted from the facsimile machine 1 to the operator. It is set on a mounted installation stand 5a.

The facsimile machine 1 includes an image reduction processing circuit 10 shown in FIG. 2, which includes a main scanning processing circuit 20, a sub-scanning processing circuit 30, and a buffer circuit 1! Ir
40 and a line memory 50.

Image data (input image data) read by the scanner of the facsimile machine 1 and converted into multivalued digital data is input to the main scanning processing circuit 20.
It is manually input as serial data line by line. One line of image data is composed of a predetermined number of pixel data. The image data input to the main scanning processing circuit 20 undergoes reduction processing in the main scanning direction, which will be described later, and is sequentially output to the sub-scanning processing circuit 30 via the bus 11. The image data input to the sub-scanning processing circuit 30 undergoes reduction processing in the sub-scanning direction, which will be described later, and is sequentially stored in the line memory 50 via the bus 12, buffer circuit 40, and bus 13. The buffer circuit 40 is a so-called three-state buffer, and the input/output of image data from the sub-scanning processing circuit 30 and the input/output of image data from the line memory 50 are controlled by an enable signal ( E
NB).

The line memory 50 has a capacity to store one line of image data at the same magnification, and when image data (pixel data) is inputted from the sub-scanning processing circuit 30, the line memory 50 starts from the previously stored first pixel data on the bus 13. , buffer circuit 40 and bus 1
4 to the sub-scanning processing circuit 3°. As will be described later, when performing line thinning, the sub-scanning processing circuit 30 outputs the manually inputted image data from the line memory 50 as output image data, and also outputs the image data and the image input from the main-scanning processing circuit 20. The black data of the thinned out line is transplanted as the image data of the comparison line, and the transplanted image data is stored in the line memory 50.

As shown in FIG. 3, the surface main scanning processing circuit 20 includes flip-flops 21, 22, a multiplexer 23, a comparator 24, a gate 25, and flip-flops 26.
It has 27. The flip-flops 21 and 22 are so-called D flip-flops, and launch input data in synchronization with the basic clock signal CLK input from the control circuit of the facsimile machine 1 (see FIG. 5). The input image data is input to the flip-flop 21, which latches the input image data for each pixel data using the basic clock signal CLK. It is output to multiplexer 23 and comparator 24. Flip-flop 22 latches the image data input from flip-flop 21 in synchronization with basic clock signal CLK, and outputs it to multiplexer 23 and comparator 24.

That is, the flip-flop 22 is the flip-flop 2
The pixel data preceding 1 by one pixel is latched and output to the multiplexer 23 and the comparator 24. The comparator 24 compares the image data (pixel data) input from the flip-flop 21 and the flip-flop 22, and when the image data latched by the flip-flop 21 is larger than the image data latched by the flip-flop 22, it outputs Let be high “I(”. Also, gate 2
A thinning signal RENB indicating the thinning timing is sent from the control circuit of the facsimile machine 1 to the flip-flop 26.5.
27, and the thinning signal RENB is a signal that becomes low "L" at the thinning timing. pretend·
7 Pflosops 26 and 27 are so-called D flip-flops, which operate according to the basic clock signal CLK.

The gate 25 outputs to the multiplexer 23 a select signal SE that becomes "H" when the outputs of the comparator 24 and the flip-flop 27 are both low "L". The multiplexer 23 outputs the image data from the flip-flop 21 to the sub-scanning processing circuit 30 when the select signal SE is low "L", and outputs the image data from the flip-flop 22 to the sub-scanning processing circuit 30 when the select signal SE is high "[■"]. It is output to the scanning processing circuit 30. Therefore, when the thinning signal RENB is high "H" and no thinning is performed, the main scanning processing circuit 20 outputs the image data latched by the flip-flop 2I to the sub-scanning processing circuit 30, and the thinning signal RENB is low. When thinning is performed at "L", the larger image data of the image data latched by the flip-flop 21 and the image data latched by the flip-flop 22, that is, the black image data, is sent to the sub-scanning processing circuit 30. Output.

As shown in FIG. 4, the sub-scanning processing circuit 30 includes flip-flops 31, 32, 33, and
5, a multiplexer 36 and a gate 37. The flip-flop 31 latches the image data input from the main scanning processing circuit 20 based on the scaling clock signal RDCK indicating the pixel thinning timing, and transfers the latched image data to the comparator 35 and the multiplexer 36.
Output to. In other words, the flip-flop 31 converts the image data from the main scanning processing circuit 20 into the variable-magnification clock signal RD.
Performs pixel thinning based on CK and comparator 35
, are output to the multiplexer 36. A buffer circuit 4 is provided in the flip-flop 32 and the flip-flop 33.
Image data in the line memory 50 is input from 0 to 1, and the flip-flops 32 and 33 latch the input image data based on the scaling clock signal RDCK. The flip-flop 32 outputs the latched image data to the flip-flop 34, and the flip-flop 34 latches the input image data based on the scaling clock signal RDCK and outputs it as output image data. The flip-flop 33 outputs the latched image data to a comparator 35 and a multiplexer 36, and the comparator 35 compares the image data input from the flip-flop 31 and the image data input from the flip-flop 33, and compares the image data input from the flip-flop 33. When the image data is larger, a signal that becomes low "L" is output to the gate 37. The gate 37 also receives the line thinning signal RDLN, which becomes low "■," at the line thinning timing, from the control circuit of the facsimile machine 1, and the gate 37 receives the output of the comparator 35 at the line thinning timing. When the select signal SE becomes low 'L', the select signal SE is output to the multiplexer 36. When the select signal SE is low 'L', the multiplexer 36 outputs the image data from the flip-flop 31 to the buffer circuit 40, and selects the When the signal SE is high "H", the image data from the flip-flop 33 is output to the buffer circuit 40.

The line memory 50 writes the image data input from the multiplexer 36 of the sub-scanning processing circuit 30 via the buffer circuit 40 when the basic clock signal CLK (see FIG. 5) is high "I", and when the basic clock signal CLK is high. Read when low “L”. Therefore, the sub-scanning processing circuit 30 thins out the pixels of the image data subjected to the comparison processing in the main-scanning processing circuit 20 using the flip-flop 31, writes the data in duplicate according to the thinning rate, and transplants it to the line memory 50.
The scaling clock signal RDCK is again adjusted according to the thinning rate.
By latching (thinning) and outputting based on
In addition to performing pixel thinning processing, when the pixel data of the line to which line thinning is performed is larger than the pixel data of a subsequent line, it is transferred to the subsequent line, and a so-called comparison processing is performed and output. The output image data from the sub-scanning processing circuit 30 is subjected to a single line thinning process by a line thinning circuit (not shown) to perform line thinning. In this case, line thinning is performed based on the variable scale clock signal RDCK. Therefore, a part of the main scanning processing circuit 20 and the sub-scanning processing circuit 30 constitute a pixel thinning means, and the sub-scanning processing circuit 30 and a line thinning circuit (not shown) constitute a line thinning means.

The basic clock signal CLK, the basic clock signal CLK, the thinning signal RENB, the select signal SE, the scaling clock signal RDCK, and the line thinning signal RDLN are specified by the scaling clock generator, etc. of the control circuit of the facsimile machine l. It is created based on the magnification ratio etc.

Next, the effect will be explained.

The facsimile machine sends original documents set on a document table 3 one by one to a scanner, and performs main scanning and sub-scanning to read images of the original documents. The image data read by the scanner is converted into multivalued digital data and input to the main scanning processing circuit 20 as input image data.

The operation of this image reduction processing circuit 10 will be explained below based on the timing chart shown in FIG.

The image data input to the flip-flop 21 of the main scanning processing circuit 20 is launched based on the basic clock signal CLK, as shown in FIGS. It is output to the comparator 24. Further, the image data input to the flip-flop 22 is launched based on the basic clock signal CLK and output to the multiplexer 23 and the converter 24, as shown in FIGS. The comparator 24 compares the image data from the flip-flop 21 and the image data from the flip-flop 22, and when the image data from the flip-flop 22 is large,
A low "L" signal is output to the gate 25. On the other hand, the thinning signal RENB indicating the pixel thinning timing is low “L”.
When the signal is delayed by the flip-flops 26 and 27 and input to the gate 25 (see FIG. 5(c) and (h)), the image data latched by the flip-flop 22 at this timing is reduced to thinned-out image data. Generally, when the pixel data is larger than the latch image data of the flip-flop 21, which is the subsequent pixel data, the multiplexer 23 outputs the image data of the flip-flop 22 (see FIGS. 5(h) and (i)). Therefore, the main scanning processing circuit 20 converts thinned-out pixel data (D2, D2, D9, DI6 in FIG. 5) to later pixel data (D3, D6, D171.DI? in FIG. 5).
), and when it is larger than the later pixel, that is, when it is black data, replace (transfer) the thinned out pixel with the later pixel.
. The image data that has undergone this comparison processing is transferred to the sub-scanning processing circuit 3.
0 to the flip-flop 31.

The flip-flop 31 launches the image data that has been subjected to the comparison process based on the scaling clock signal RDCK, and outputs it to the comparator 35 and the multiplexer 36.

As shown in FIG. 5(d), this scaling clock signal 1'2DcK is a series of basic clock signals CLK at the thinning timing of pixel data in the main scanning direction, and the launch data of the flip-flop 31 is As shown in FIG. 5(j), the image data is thinned out pixel data (DZ, D5, etc.) (see FIG. 5(i) and (j)).

When it is not the line thinning timing, line thinning signal R
DLN is high "H", and the gate 37 outputs a low "L" select signal SE to the multiplexer 36. Therefore, the multiplexer 36 is connected to the flip-flop 31
outputs the latch data to the buffer circuit 40, and the line memory 50 writes the image data input through the buffer circuit 40 when the basic clock signal CLK is high (FIGS. 5(b) and 5(k)). (See (1)). As a result, the pixel data before the thinned-out pixel data is written twice, and the same number of pixel data as at the same magnification is sequentially written into the line memo 50. Furthermore, the pixel data written in the line memory 50 is as shown in FIG. 5(m).
Read when the basic clock signal CLK is low “L”,
Flip-flops 32 and 33 through the buffer circuit 40
(See Figure 5 (m), (n), and (o)). Therefore, the same number of pixel data is input to the flip-knob flops 32 and 33 as at the same magnification, but the flip-flop 3
2 and the flip-flop 33 receive the variable-magnification clock signal RD.
In order to latch input data based on CK, pixel data from one of the flip-flops 32 and 33 that has been read repeatedly is thinned out. the result,
The flip-flop 32 and the flip-flop 33 output image data that has been subjected to the same thinning process as the image data that has been thinned out by the flip-flop 31.

The latched data of the flip-flop 32 is input to the flip-flop 34, where it is latched based on the variable magnification clock signal RDCK and output as output image data. A line thinning circuit (not shown) performs line thinning processing on this output image data based on the scaling clock signal RDCK, and reduction processing is performed in the main scanning direction and the sub scanning direction.

On the other hand, at the line thinning timing, the line thinning signal RDLN becomes low "L", and the gate 37 changes the select signal SE to high "H" according to the comparison result of the comparator 35.
” or low “L”.

At the thinning timing when the line thinning signal RDLN goes low "L", the image data output from the flip-flop 34 is thinned out for one line. That is, the comparator 35 compares the image data (pixel data) from the flip-flop 31 and the image data (pixel data) from the flip-flop 33, and when the image data from the flip-flop 33 is larger, the output is set to low. ”, and the gate 37 outputs a high “L” select signal SE to the multiplexer 3G. When the select signal SE becomes high "l", the multiplexer 36 outputs the image data from the flip-flop 33 to the buffer circuit 40. Therefore, when the image data of the line to be thinned out is larger than the image data of the next line (black), it is replaced (transplanted) with the image data of the next line and stored in the line memory 50. As a result, even if there are thin lines etc. in the thinning line, the image data is transferred to the image data of the next line,
It is output as output image data without any loss.

In this way, in the reduction process, the pixel data thinned out in the pixel data thinning process in the main scanning direction can be transplanted by the comparison process of the main scanning processing circuit 20, and the pixel data thinned out in the pixel data thinning process in the main scanning direction can be transplanted, and the The pixel data thinned out in the thinning process can be transplanted by the comparison process of the sub-scanning processing circuit 30, and it is possible to prevent black data from being lost. Therefore, it is possible to prevent the loss of thin lines and the like due to reduction processing, and it is possible to improve the image quality.

In the above embodiments, the case where the present invention is applied to a facsimile machine has been described, but the present invention is not limited to this (it can be applied to general image processing apparatuses that perform image processing, such as computers and word processors).

(Effects) According to the present invention, it is possible to prevent the loss of black data in the thinned-out line and to prevent the loss of 1g lines and the like in the sub-scanning direction, and it is possible to improve the image quality in the reduction process.

[Brief explanation of the drawing]

1 to 5 are diagrams showing one embodiment of the image processing device of the present invention, FIG. 1 is a perspective view of a facsimile machine to which the image processing device is applied, and FIG. 2 is a perspective view of the image processing device. FIG. 3 is a main scanning processing circuit diagram, FIG. 4 is a sub-scanning processing circuit diagram, and FIG. 5 is a timing chart showing the operation of the image processing apparatus. 10... Image reduction processing circuit, 20... Main scanning processing circuit (pixel thinning means), 2
1.22...Flip-flop, 23...
...Multiplexer, 24...Comparator, 25...Gate, 26.27...Flip-flop, 30...
... Sub-scanning processing circuit (line thinning means), 31.32
．． 33.34...Flip-flop, 35...
... Comparator, 36 ... Multiplexer, 37 ... Gate, 40 ... Buffer circuit, 50 ... Line memory. Figure 1 Procedural amendment C15 draft

Claims (2)

[Claims] (1) An image processing device that performs image reduction processing, comprising a pixel thinning device that thins out pixel data in the main scanning direction, and a line thinning device that thins out lines in the sub-scanning direction, The pixel thinning means selects thinned pixel data by comparing it with pixel data before or after the pixel data, and the line thinning means selects each pixel data of the thinned line from the pixel data of the line before the line. An image processing device that performs line thinning by selecting thinned-out pixel data by comparing each pixel data or each pixel data of a subsequent line. (2) The line thinning means includes a line memory that stores pixel data for one line, a comparator that compares input pixel data with pixel data from the line memory during thinning, and a line thinning unit that performs thinning based on the comparison result of the comparator. 2. The image processing apparatus according to claim 1, further comprising a selection means for selecting pixel data to be adopted without delay and writing the selected pixel data into the line memory.