JPH01152743A - Standard cell system semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To automate a layout easily by making the flow of each bit in data conform to the longitudinal direction of a cell row in which a plurality of standard cells are aligned. CONSTITUTION:The title semiconductor integrated circuit is constituted so that the flows of each bit in data are conformed to the longitudinal direction of cell rows 60-62 in which a plurality of standard cells 100-102 are aligned. Since the longitudinal direction (the Y direction) of each of the cell rows 60-62 and the direction (the Y direction) of the flowing of data coincide, width conforming sections as seen in conventional devices need not be formed in the cell rows 60-62. Accordingly, the increase of processes can be prevented, thus easily automating the arrangement, a layout, of the standard cells.

Description

[Detailed Description of the Invention] [Summary] With respect to a standard cell type semiconductor integrated circuit having a circuit section having a data bus configuration, the present invention aims to prevent an increase in layout steps and facilitate layout automation. In a standard cell type semiconductor integrated circuit in which a circuit with a data bus configuration that is approximately the same as the data bus and continuously performs multiple processes for each bit is formed, the flow of each bit of data connects multiple standard cells in a line. Configure it so that it matches the longitudinal direction of the arranged cell rows.

[Industrial application field]

The present invention relates to a standard cell type semiconductor integrated circuit,
The present invention relates to a standard cell type semiconductor integrated circuit having a circuit section having a data bus configuration.

When each bit of parallel data is substantially the same in an arithmetic logic unit (ALU), and multiple processes are performed continuously for each bit, a data bus configuration as shown in Figure 4 is used. . In the figure, each bit of parallel data is input to each of terminals 101 to 10Tl. Each bit is subjected to processing 1 in each of blocks 111 to 11TI, then processing 2 is performed in each of blocks 12+ to 12η, and similarly, processing m is performed once in each of blocks 131 to 131, and terminals 14+ to 14Tl are processed respectively. It is output from

There is a demand for efficiently forming a circuit section having the above data bus configuration in a semiconductor integrated circuit in a small area.

[Conventional technology]

In the conventional standard cell type semiconductor integrated circuit, standard cells are arranged in a row to form cell row 1, as shown in Figure 5.
51 to 15 m, respectively, and a wiring channel 16 is formed between the cell rows.

When forming a circuit section with a data bus configuration using this standard cell type semiconductor integrated circuit, for example, each of the standard cells 20+ to 2On of the cell row 151 is connected to the block 11+.
Process 1 is performed corresponding to ~11η, and cell column 1 is similarly
Processing 2 with each of 52 standard cells 21+ to 21T+
and standard cells 221 to 2 in cell row 15m.
Processing m is performed for each of 2Tl.

In other words, the flow of each data is orthogonal to the X direction in the longitudinal direction (Y direction) of the cell rows 151 to 15m.

(Problems to be Solved by the Invention) In a conventional semiconductor integrated circuit, the width dl in the Y direction of the standard cell 20+ to 20η for processing 1, and the width dl in the Y direction for processing 2 (
or standard cells 211 to 21Tl (m)
or 221~22TI) Y direction width d2 (or d3)
are different for each.

Therefore, if d+>d2, in order to make the flow of each data parallel, it is necessary to provide a width matching part 25 between each of the standard cells 21+ to 21π in the cell row 152, and this width matching part 25 There was a problem in that this increased the number of steps to insert cells, which hindered the automation of standard cell layout.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a standard cell type semiconductor integrated circuit that can prevent an increase in the number of layout steps and facilitate automation of layout.

[Means for solving problems]

The standard cell type semiconductor integrated circuit of the present invention is a standard cell type semiconductor integrated circuit in which a circuit having a data bus configuration that is substantially the same for each bit of data and sequentially performs a plurality of processes for each bit is formed. Each bit stream of data is divided into multiple standard cells (100 to 1
02) is configured to coincide with the longitudinal direction of the cell rows (60 to 62) arranged in a row.

[Effect]

In the present invention, since the flow of each bit of data coincides with the longitudinal direction of the cell rows (60 to 62), it is not necessary to provide a width alignment portion in each cell row (60 to 62) as in the conventional case. This prevents an increase in process steps and facilitates layout automation.

〔Example〕

FIG. 1 shows a plan view of an embodiment of the circuit of the present invention.

Before explaining FIG. 1, an ALU having a data bus configuration formed in the circuit of the present invention will be explained with reference to FIG.

FIG. 2 shows a data bus for one bit.

Data A and B enter terminals 30 and 31, respectively, and terminal 3
2 to 38 are signals IOA and Ice.

ADC, ERG, C1, PLO, and IGO each enter.

The data A and B output by the exclusive NOR circuits 39 and 40 of the input buffer section 25 and the signal IO
The calculation signals from each of A and ICB are sent to the NAND circuit 4 of the logic function section 26 via inverters 41 and 42, respectively.
3, an exclusive NOR circuit 44 and an adder 50.

The outputs of the NAND circuit 43 and the exclusive NOR circuit 44 are supplied to the exclusive NOR circuit 47 through transmission gates 45 and 46 controlled by the signals ADC and ERC, respectively.

Adder 50 is also supplied with signal CI, its So terminal output is supplied to exclusive NOR circuit 47 via transmission gate 51 controlled by signal PLO, and co terminal output is output from terminal 52.

The exclusive NOR circuit 47 is supplied with a signal ICO, and its output is output as data Y from a terminal 49 via an inverter 48.

Incidentally, FIG. 3 shows an arithmetic expression for data Y according to the values of signals ICA to ICo. In the figure, "L" is the value "O', rHJ
is the value '1', rXJ is undefined, '△' is AND, rVJ
indicates an or, and "■" indicates an exclusive or.

Referring to FIG. 1, 60, 61, and 62 are cell rows, cell rows 60, 61 are symmetrical with respect to their boundaries, and cell row 62 has the same configuration as cell row 60.

A part of the circuit shown in FIG. 2 is formed for each cell column, and the cell column 60 will be described below.

Polysilicon gate electrodes 65 and 66 shown by solid lines are provided in the rectangular transistor formation regions 63 and 64, respectively. The broken line in the X direction is the first layer wiring, and the signals IOA and IC8 are supplied to the first layer wiring 67 and 68, respectively.
Signal ADC and its inverted signal XAD at layer wiring 69°70
C is supplied, and the signal ERC and its inverted signal XERC are supplied through the first layer wirings 71 and 72.

The dashed line in the Y direction is the second layer wiring, and the second layer wiring 73
．． 74 are supplied with power supplies VDD and VSS, respectively, and second layer wirings 75 and 76 are supplied with data A and 8, respectively.

Note that the circles indicate contacts between the substrate and the first layer wiring, and the marks indicate the contacts between the first layer wiring and the second layer wiring.

Transistor formation regions 63.64.80.81 and 82
．． The exclusive NOR circuit 39 and the inverter 41 are formed in each of the transistor forming regions 84 to 87.
The exclusive NOR circuit 40 and the inverter 42 of the input buffer section 25 are formed by 88 and 89, respectively. The output of the inverters 41 and 42 is the second layer wiring 9
Transistor formation regions 92, 93 and 9 due to 0°91
The signal is supplied to the logic function section 26 formed by sections 4 to 98.

The cell row 61 includes standard cells 100 forming the input buffer section 25, standard cells 100 forming the NAND circuit 43, and the transmission gate 45.
1. The standard cell 102 which constitutes the exclusive NOR circuit 44 and the transmission gate 46, and the cell which constitutes the converter 50 in the lower part of the Y direction in FIG.

In this way, the longitudinal direction of each cell row 60 to 63 (Y direction)
Since the data flow direction (Y direction) coincides with the data flow direction, there is no need to provide a width matching portion in the cell rows 60 to 63 as in the conventional case. Therefore, it is possible to prevent an increase in the number of steps, and it becomes easy to automate the arrangement (standard cell), that is, the layout.

〔Effect of the invention〕

As described above, according to the standard cell type semiconductor integrated circuit of the present invention, it is possible to prevent an increase in the number of layout steps, and it is possible to easily automate the layout, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the standard cell type semiconductor integrated circuit of the present invention, FIG. 2 is a circuit diagram of an embodiment of an ALU, and FIG. 3 is for explaining the calculation operation of the circuit of FIG. 2. FIG. 4 is a diagram for explaining a data bus, and FIG. 5 is a diagram for explaining the configuration of a conventional circuit. In the figure, 60-62 are cell columns, 63.64.80-89.92-98 are transistor formation regions, 65.66 are gate electrodes, 67-72 are first layer wirings, 73-76.90.91 is the second layer wiring, 100 to 102
indicates a standard cell. Patent Applicant: Fujitsu Limited Fujitsu VLSI Ltd. Figure 2 Diagram for configuring data/gusu + Jj Figure 4 Diagram for explaining the configuration of a conventional circuit

Claims (1)

[Scope of Claims] In a standard cell type semiconductor integrated circuit in which a circuit having a data bus configuration is formed that is substantially the same for each bit of data and sequentially performs a plurality of processes for each bit, each bit of data is provided with: The flow of multiple standard cells (
Cell row (60-62) in which cells 100-102) are arranged in a row
1. A standard cell type semiconductor integrated circuit characterized in that the circuit is configured to match the longitudinal direction of the semiconductor integrated circuit.