JPH01150299A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To improve a substitution ratio for a redundancy memory cell by reducing the parasitic capacity value of a digit line in the redundancy memory cell smaller than that of a main memory cell. CONSTITUTION:A memory cell is constituted of a two-divided system by adding Y decoders and sense amplifiers SA to both the sides of the redundancy memory cell. Consequently, the length of the digit line DL goes 1/2 and parasitic capacity can be also set to 1/2. Thus, the substitution ratio for the redundancy memory cell can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and particularly to a semiconductor memory circuit using a redundant circuit.

[Conventional technology]

Conventionally, this type of semiconductor memory is configured as shown in Figure 3, and the length of the digit line of the redundant memory cell and the length of the memory cell normally used for storing information (hereinafter abbreviated as main memory cell) are as follows. Since the lengths of the digit lines were the same (the digit lines were common) or approximately the same, the parasitic capacitances of the digit lines of both memory cells were also approximately the same.

In addition, the configuration of the redundancy decoder is as shown in Figure 4, and if there is no cell defect in the main memory cells, there is no need to use the redundancy circuit, so points P1 to P2 in Figure 4 are used. ．． ．． Leave everything uncut. Therefore, when an address is input, one of Ai and Ai is always high, so the potential of ■ becomes low, thereby activating the X and Y decoders for the main memory cells. The time chart in that case is as shown in FIG.

If there is a cell defect in the main memory cell, when an address for selecting the defective cell is input, the point Pi on the drain side of the transistor that is turned on is turned off in the redundancy decoder. Then, only when that address is input, ■ remains high, so the decoder for the main memory cell is not activated, the redundant decoder is activated, and the word line or digit line of the redundant cell is selected. Ru. The time chart in that case is as shown in FIG.

[Problem that the invention seeks to solve]

In the semiconductor memory including the conventional redundant circuit described above, the parasitic capacitance of the digit line of the redundant memory cell and the parasitic capacitance of the main memory cell are approximately the same. If the parasitic capacitance of the digit line is C9, and the capacitance of the capacitive element (capacitor) that constitutes one memory cell is Cs, then the smaller CD/C9, the larger the difference in potential that enters the sense amplifier.
This makes it easier for data to be output correctly. This reduces the possibility of cell defects. Conventional semiconductor memories including redundant circuits have the above-mentioned configuration, so the possibility of cell defects is the same in redundant cells and main cells, and therefore has the disadvantage of a low replacement rate with redundant circuits. .

[Means for solving problems]

In order to eliminate such conventional drawbacks, the semiconductor memory redundancy circuit of the present invention has means for making the length of the digit line of the redundant memory cell shorter than the length of the digit line of the main memory cell.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an embodiment of the present invention, which is a plan view of a cell array section of a semiconductor memory having redundant memory cells for digits, viewed from above. A Y decoder and a sense amplifier are attached to both sides of the redundant memory cell to divide the memory cell into two. As a result, the length of the digit line becomes 1/2,
Parasitic capacitance can also be reduced to 1/2.

FIG. 2 is a plan view of a second embodiment of the present invention, which is a semiconductor memory having redundant memory cells for words. The main memory cell and the redundant memory cell are divided by inserting a Y decoder between the main memory cell and the redundant memory cell and attaching sense amplifiers to both sides thereof. As a result, the digit line of the redundant memory cell can be made considerably shorter, so that the parasitic capacitance can be made very small.

〔Effect of the invention〕

As explained above, the present invention improves the replacement rate of redundant memory cells by making the parasitic capacitance value of the digit line of the redundant memory cell smaller than the parasitic capacitance of the digit line of the main memory cell. have

[Brief explanation of the drawing]

FIG. 1 is a plan view of a first embodiment of the present invention, FIG. 2 is a plan view of a second embodiment of the present invention, and FIG. 3 is a plan view of an example of the prior art. S, A...Sense Anne 7", D, L...
・Memory cell digit line, Vcc...Power supply voltage, A i, 1 address...Address, ■...
・Decoder activation signal. Agent Patent Attorney Shinguchi Uchihara■ Gough==Kome 1 Figure 2 Figure

Claims (1)

[Claims] In a semiconductor memory having redundant memory cells in addition to memory cells used for information storage, the parasitic capacitance of the digit lines constituting the redundant memory cells is greater than the parasitic capacitance of the digit lines constituting the memory cells. A semiconductor memory circuit characterized by being smaller than its capacity.