JPH01149475A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH01149475A JPH01149475A JP30833887A JP30833887A JPH01149475A JP H01149475 A JPH01149475 A JP H01149475A JP 30833887 A JP30833887 A JP 30833887A JP 30833887 A JP30833887 A JP 30833887A JP H01149475 A JPH01149475 A JP H01149475A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- silicon
- gate insulating
- thin film
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010408 film Substances 0.000 claims abstract description 58
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 21
- 150000001875 compounds Chemical class 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 abstract description 9
- 239000007789 gas Substances 0.000 abstract description 9
- 239000011521 glass Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 5
- 125000004433 nitrogen atom Chemical group N* 0.000 abstract description 3
- 125000004430 oxygen atom Chemical group O* 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 239000001272 nitrous oxide Substances 0.000 abstract 2
- 229910003849 O-Si Inorganic materials 0.000 abstract 1
- 229910003872 O—Si Inorganic materials 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229960001730 nitrous oxide Drugs 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 235000013842 nitrous oxide Nutrition 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、しきい値電圧の制御を低温で、かつ簡便な方
法により実現できる薄膜トランジスタの製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film transistor that can realize threshold voltage control at low temperatures and by a simple method.
（従来技術及び発明が解決しようとする問題点）近年大
面積、高機能なアクティブマトリックス形平面デイスプ
レィ表示パネルの実現を目的として、高速なスイッチン
グ特性を有する薄膜トランジスタの開発が進められてい
る。このアクティブマトリックス形平面デイスプレィ表
示パネルの低価格化を実現するためには、薄膜トランジ
スタを形成する基板として安価なガラスを用いる必要が
あり、そのためには薄膜トランジスタ製造工程における
処理温度を６００℃以下に抑える必要がある。(Prior Art and Problems to be Solved by the Invention) In recent years, thin film transistors having high-speed switching characteristics have been developed with the aim of realizing large-area, high-performance active matrix type flat display panels. In order to reduce the price of this active matrix type flat display panel, it is necessary to use inexpensive glass as a substrate for forming thin film transistors, and to do so, it is necessary to suppress the processing temperature in the thin film transistor manufacturing process to 600 degrees Celsius or less. There is.
一方、アクティブマトリックス形平面デイスプレィ表示
パネルに用いられる薄膜トランジスタにおいては、しき
い値電圧を表示パネルの周辺駆動回路と整合する値に制
御しなければならない。On the other hand, in a thin film transistor used in an active matrix type flat display panel, the threshold voltage must be controlled to a value that matches the peripheral driving circuit of the display panel.
従来のシリコン薄膜トランジスタとその製造方法を第２
図を用いて説明する。まず、第２図Ａに示すように絶縁
基板上２０１にプラズマＣＶＤ法。The second version of the conventional silicon thin film transistor and its manufacturing method.
This will be explained using figures. First, as shown in FIG. 2A, an insulating substrate 201 is formed by plasma CVD.
減圧ＣＶＤ法等の方法でシリコン膜２０２を形成する０
次に第２図Ｂに示すようにイオン注入法によりリン、ボ
ロン、ヒ素等の不純物イオンを打ち込み、９００°Ｃ以
上の温度の熱処理を施して不純物の活性化を行う、しき
い値電圧制御は、該不純物イオンを所望のしきい値電圧
に相当する量だけ注入し、該不純物イオンを高温で活性
化することによりシリコン膜２０２の抵抗を変化させ行
われる０次に第２図Ｃに示すように、酸化シリコン膜や
窒化シリコン膜によるゲート絶縁膜２０３をプラズマＣ
ＶＤ法、減圧ＣＶＤ法等の方法で形成したのちモリブデ
ン等の金属膜あるいは多結晶シリコン膜よりなるゲート
電極２０４を形成する０次に、第２図りに示すように、
イオン注入法によりリン、ボロン、ヒ素等の不純物イオ
ンを打ち込み、９００°Ｃ以上の温度の熱処理を施して
不純物の活性化を行い、ソース２０５．ドレイン２０６
を形成する０次に第２図已に示すように眉間絶縁膜２０
７を堆積したのちソース２０５．ドレイン２０６上のゲ
ート絶縁膜２０３゜層間絶縁膜２０７にそれぞれコンタ
クトホールを開口し、これら開口を通じてソース２０５
．ドレイン２０６とそれぞれ接触した配線２０８を形成
し薄膜トランジスタを完成する。A silicon film 202 is formed by a method such as a low pressure CVD method.
Next, as shown in Figure 2B, impurity ions such as phosphorus, boron, arsenic, etc. are implanted using the ion implantation method, and the impurities are activated by heat treatment at a temperature of 900°C or higher.Threshold voltage control , the impurity ions are implanted in an amount corresponding to a desired threshold voltage, and the resistance of the silicon film 202 is changed by activating the impurity ions at high temperature, as shown in FIG. 2C. Then, a gate insulating film 203 made of a silicon oxide film or a silicon nitride film is coated with plasma C.
After forming the gate electrode 204 by a method such as a VD method or a low pressure CVD method, a gate electrode 204 made of a metal film such as molybdenum or a polycrystalline silicon film is formed. Next, as shown in the second diagram,
Impurity ions such as phosphorus, boron, arsenic, etc. are implanted using an ion implantation method, and heat treatment is performed at a temperature of 900° C. or higher to activate the impurities, thereby forming the source 205. drain 206
As shown in Figure 2, the glabellar insulation film 20 is formed.
After depositing source 205. Contact holes are opened in the gate insulating film 203 and the interlayer insulating film 207 on the drain 206, and the source 205 is connected through these openings.
．． Wirings 208 in contact with the drains 206 are formed to complete the thin film transistor.
このような薄膜トランジスタの製造工程においては、薄
膜トランジスタのしきい値電圧を制御するためにシリコ
ン膜に不純物イオンが注入され、該不純物を活性化する
温度として６００°Ｃ以上が必須であった。このため、
薄膜トランジスタを安価なガラス基板上に形成できない
という問題があった。また、シリコン膜が多結晶シリコ
ン膜やアモルファスシリコン膜である場合、該多結晶シ
リコン膜やアモルファスシリコン膜中に存在する欠陥に
不純物イオンが入り込むため、不純物の活性化が十分行
われない、このため、イオン注入法を用いて該多結晶シ
リコン膜やアモルファスシリコン膜の抵抗を変化させ厳
密にしきい値電圧制御を行うことは困難であった。In the manufacturing process of such thin film transistors, impurity ions are implanted into the silicon film in order to control the threshold voltage of the thin film transistor, and a temperature of 600° C. or higher is essential for activating the impurities. For this reason,
There was a problem in that thin film transistors could not be formed on inexpensive glass substrates. In addition, when the silicon film is a polycrystalline silicon film or an amorphous silicon film, impurity ions enter defects existing in the polycrystalline silicon film or amorphous silicon film, and the impurities are not activated sufficiently. However, it has been difficult to strictly control the threshold voltage by changing the resistance of the polycrystalline silicon film or amorphous silicon film using ion implantation.
（発明の目的）
本発明の目的は、イオン注入法を用いず簡便に行え、か
つ安価なガラスを基板として使用でき、かつしきい値電
圧を自由に制御しうる薄膜トランジスタの製造方法を提
供することにある。(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a thin film transistor that can be easily performed without using ion implantation, can use inexpensive glass as a substrate, and can freely control the threshold voltage. It is in.
（問題点を解決するための手段）
上記の目的を達成するため、本発明は半導体薄膜トラン
ジスタとゲート絶縁膜とゲート電極とソース・ドレイン
電極を具備した薄膜トランジスタにおいて、前記半導体
薄膜としてシリコンを用い、前記ゲート絶縁膜として窒
素と酸素とシリコンの化合物を用い、該化合物に含まれ
る窒素と酸素の割合を任意に変えることにより所望のし
きい値電圧を得ることを特徴とする薄膜トランジスタの
製造方法を発明の要旨とするものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a thin film transistor including a semiconductor thin film transistor, a gate insulating film, a gate electrode, and a source/drain electrode, in which silicon is used as the semiconductor thin film, The present invention provides a method for manufacturing a thin film transistor, characterized in that a compound of nitrogen, oxygen, and silicon is used as a gate insulating film, and a desired threshold voltage is obtained by arbitrarily changing the ratio of nitrogen and oxygen contained in the compound. This is a summary.
しかして本発明の薄膜トランジスタの製造方法は、例え
ばプラズマＣＶＤ法により形成された窒素と酸素とシリ
コンの化合物よりなるゲート絶縁膜において、窒素と酸
素の割合を任意に変えて形成し、薄膜トランジスタのし
きい値電圧を制御することを特徴とする。従来技術とは
、薄膜トランジスタのしきい値電圧制御が低温で、かつ
簡便に行えることが異なる。Therefore, in the method for manufacturing a thin film transistor of the present invention, a gate insulating film made of a compound of nitrogen, oxygen, and silicon is formed by, for example, plasma CVD, and the ratio of nitrogen and oxygen is arbitrarily changed. It is characterized by controlling the value voltage. The difference from the conventional technology is that the threshold voltage of the thin film transistor can be controlled easily and at low temperature.
次に本発明の実施例について説明する。なお、実施例は
一つの例示であって、本発明の精神を逸脱しない範囲で
、種々の変更あるいは改良を行いうることは言うまでも
ない。Next, examples of the present invention will be described. Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
（実施例）
第１図を用いて本発明による薄膜トランジスタの製造方
法の一実施例を示す、まず、第１図Ａに示すようにガラ
ス基板１０１上に多結晶シリコン膜１０２を形成する０
次に第１図Ｂに示すように、文献（例えば論文Ｙ、旧ｒ
ａｔ他 ＾ｐｐ１． Ｐｈｙｓ、 Ｌｅｔｔ４２ （８
）、 Ａｐｒｉｌ １９８３）で示されたようなプラズ
マＣＶＤ法により１８０℃で形成された低抵抗なシリコ
ン膜を用いてソース１０３．ドレイン１０４を形成する
０次に、第１図Ｃに示すように、ゲート絶縁膜１０５と
してプラズマＣＶＤ法により、アンモニアガス、−酸化
二窒素ガスとシランガスを原料ガスとして、３００°Ｃ
の温度で窒素と酸素とシリコンの化合物を堆積する。し
きい値電圧はゲート絶縁膜中の固定電荷の量と、シリコ
ンとゲート絶縁膜との界面準位密度により変化する。固
定電荷量及び界面準位密度はゲート絶縁膜中の窒素原子
と酸素原子の割合を変えれば連続的に変えることができ
る。ゲート絶縁膜中の窒素原子と酸素原子の割合はアン
モニアガスと一酸化二窒素ガスの流量比により変えるこ
とができる。故に本実施例ではアンモニアガスと一酸化
二窒素ガスの流量比によりしきい値電圧の制御を行う０
次に、第１図りに示すように、モリブデン等の金属膜あ
るいは多結晶シリコン膜よりなるゲート電極１０６を形
成し、眉間絶縁膜１０７を堆積したのちソース１０３．
ドレイン１０４上のゲート絶縁膜１０５０層間絶縁膜１
０７にそれぞれコンタクトホールを開口し、これら開口
を通じてソース１０３．ドレイン１０４とそれぞれ接触
した配線１０８を形成し薄膜トランジスタを完成する。(Example) An example of the method for manufacturing a thin film transistor according to the present invention will be described with reference to FIG. 1. First, as shown in FIG.
Next, as shown in Figure 1B, a document (for example, paper Y, old r
at et al. ＾pp1. Phys, Lett42 (8
), April 1983), the source 103. Next, as shown in FIG. 1C, the drain 104 is formed by plasma CVD as the gate insulating film 105 using ammonia gas, dinitrogen oxide gas and silane gas as source gases at 300°C.
Deposit a compound of nitrogen, oxygen and silicon at a temperature of . The threshold voltage varies depending on the amount of fixed charge in the gate insulating film and the density of interface states between silicon and the gate insulating film. The amount of fixed charge and the interface state density can be continuously changed by changing the ratio of nitrogen atoms to oxygen atoms in the gate insulating film. The ratio of nitrogen atoms to oxygen atoms in the gate insulating film can be changed by changing the flow rate ratio of ammonia gas and dinitrogen monoxide gas. Therefore, in this embodiment, the threshold voltage is controlled by the flow rate ratio of ammonia gas and dinitrogen monoxide gas.
Next, as shown in the first diagram, a gate electrode 106 made of a metal film such as molybdenum or a polycrystalline silicon film is formed, and after a glabellar insulating film 107 is deposited, a source 103.
Gate insulating film 1050 on drain 104 Interlayer insulating film 1
07, and the sources 103.07 are connected through these openings. Wirings 108 are formed in contact with the drains 104 to complete the thin film transistor.
以上説明した薄膜トランジスタの製造法によれば、しき
い値電圧制御は、イオン注入法を用いずゲート絶縁膜形
成と同時に行えるため簡便で、かつ安価なガラス基板を
使用できる低温で行うことができる。According to the method for manufacturing a thin film transistor described above, threshold voltage control can be performed simultaneously with gate insulating film formation without using an ion implantation method, and therefore can be performed easily and at a low temperature where an inexpensive glass substrate can be used.
第３図に窒素とシリコンの化合物をゲート絶縁膜とした
薄膜トランジスタａと酸素とシリコンの化合物をゲート
絶縁膜とした薄膜トランジスタｂのゲート電圧−相互コ
ンダクタンス特性を示す。FIG. 3 shows the gate voltage-mutual conductance characteristics of a thin film transistor a whose gate insulating film is made of a compound of nitrogen and silicon, and a thin film transistor b whose gate insulating film is made of a compound of oxygen and silicon.
窒素とシリコンの化合物をゲート絶縁膜とした薄膜トラ
ンジスタにおいては、しきい値電圧が一２■、酸素とシ
リコンの化合物をゲート絶縁膜とした薄膜トランジスタ
においては、しきい値電圧が＋２Ｖである。従って、本
実施例のゲート絶縁例では、膜中の窒素と酸素の割合を
変えることによって、−２Ｖから＋２ｖまでしきい値電
圧を制御できる。A thin film transistor with a gate insulating film made of a compound of nitrogen and silicon has a threshold voltage of 12V, and a thin film transistor with a gate insulating film of a compound of oxygen and silicon has a threshold voltage of +2V. Therefore, in the gate insulation example of this embodiment, the threshold voltage can be controlled from -2V to +2V by changing the ratio of nitrogen and oxygen in the film.
また、以上説明した実施例では、ゲート絶縁膜はプラズ
マＣＶＤ法を用いて形成されたが、この方法に限ること
はなく、３００°Ｃ以下の温度で窒素と酸素とシリコン
の化合物によるゲート絶縁膜を形成することができるス
パッタ法、光ＣＶＤ法を用いてもよい。Further, in the embodiments described above, the gate insulating film was formed using the plasma CVD method, but the method is not limited to this method, and the gate insulating film is formed using a compound of nitrogen, oxygen, and silicon at a temperature of 300° C. A sputtering method or a photo-CVD method that can form the above may also be used.
（発明の効果）
以上説明したように、本発明によれば、半導体薄膜トラ
ンジスタとゲート絶縁膜とゲート電極とソース・ドレイ
ン電極を具備した薄膜トランジスタにおいて、前記半導
体薄膜としてシリコンを用い、前記ゲート絶縁膜として
窒素と酸素とシリコンの化合物を用い、該化合物に含ま
れる窒素と酸素の割合を任意に変えることによって、薄
膜トランジスタのしきい値電圧制御を、イオン注入法を
用いず簡便に行えかつ安価なガラスを基板として使用で
きる低温で行える。このため高性能な平面デイスプレィ
を低コストで実現できる。(Effects of the Invention) As described above, according to the present invention, in a thin film transistor including a semiconductor thin film transistor, a gate insulating film, a gate electrode, and a source/drain electrode, silicon is used as the semiconductor thin film, and silicon is used as the gate insulating film. By using a compound of nitrogen, oxygen, and silicon and arbitrarily changing the ratio of nitrogen and oxygen contained in the compound, threshold voltage control of thin film transistors can be easily performed without using ion implantation, and an inexpensive glass can be made. It can be done at low temperatures that can be used as a substrate. Therefore, a high-performance flat display can be realized at low cost.
第１図は本発明の薄膜トランジスタの製造方法を示す、
第２図は従来の薄膜トランジスタの製造方法の一実施例
を示す、第３図は窒素とシリコンの化合物をゲート絶縁
膜とした薄膜トランジスタと酸素とシリコンの化合物を
ゲート絶縁膜とした薄膜トランジスタのゲート電圧−相
互コンダクタンス特性である。
１０１ ・・・ガラス基板
１０２ ・・・シリコン膜
１０３ ・・・ソース
１０４ ・・・ドレイン
１０５ ・・・ゲート絶縁膜
１０６ ・・・ゲート電極
１０７ ・・・層間絶縁膜
１０８ ・・・配線
２０１ ・・・ガラス基板
２０２ ・・・シリコン膜
２０３ ・・・ゲート絶縁膜
２０４ ・・・ゲート電極
２０５ ・・・ソース
２０６ ・・・ドレイン
２０７ ・・・層間絶縁膜
２０８ ・・・配線
第１図
第２図FIG. 1 shows a method for manufacturing a thin film transistor of the present invention.
Figure 2 shows an example of a conventional thin film transistor manufacturing method. Figure 3 shows the gate voltage of a thin film transistor with a gate insulating film made of a compound of nitrogen and silicon and a thin film transistor with a gate insulating film made of a compound of oxygen and silicon. It is a mutual conductance characteristic. 101...Glass substrate 102...Silicon film 103...Source 104...Drain 105...Gate insulating film 106...Gate electrode 107...Interlayer insulating film 108...Wiring 201... -Glass substrate 202...Silicon film 203...Gate insulating film 204...Gate electrode 205...Source 206...Drain 207...Interlayer insulating film 208...Wiring Figure 1 Figure 2
Claims (1)
とソース・ドレイン電極を具備した薄膜トランジスタに
おいて、前記半導体薄膜としてシリコンを用い、前記ゲ
ート絶縁膜として窒素と酸素とシリコンの化合物を用い
、該化合物に含まれる窒素と酸素の割合を任意に変える
ことにより所望のしきい値電圧を得ることを特徴とする
薄膜トランジスタの製造方法。In a thin film transistor including a semiconductor thin film transistor, a gate insulating film, a gate electrode, and a source/drain electrode, silicon is used as the semiconductor thin film, a compound of nitrogen, oxygen, and silicon is used as the gate insulating film, and nitrogen contained in the compound and A method for manufacturing a thin film transistor, characterized in that a desired threshold voltage is obtained by arbitrarily changing the proportion of oxygen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30833887A JPH01149475A (en) | 1987-12-04 | 1987-12-04 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30833887A JPH01149475A (en) | 1987-12-04 | 1987-12-04 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01149475A true JPH01149475A (en) | 1989-06-12 |
Family
ID=17979858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30833887A Pending JPH01149475A (en) | 1987-12-04 | 1987-12-04 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01149475A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0794751A (en) * | 1993-09-16 | 1995-04-07 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of fabrication thereof |
| US6168980B1 (en) | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JP2012119423A (en) * | 2010-11-30 | 2012-06-21 | Toray Ind Inc | Gate insulating material, gate insulating film, and field effect transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62190760A (en) * | 1986-02-18 | 1987-08-20 | Ricoh Co Ltd | Thin-film transistor and manufacture thereof |
| JPS63228757A (en) * | 1987-03-18 | 1988-09-22 | Komatsu Ltd | Manufacture of thin-film transistor |
-
1987
- 1987-12-04 JP JP30833887A patent/JPH01149475A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62190760A (en) * | 1986-02-18 | 1987-08-20 | Ricoh Co Ltd | Thin-film transistor and manufacture thereof |
| JPS63228757A (en) * | 1987-03-18 | 1988-09-22 | Komatsu Ltd | Manufacture of thin-film transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168980B1 (en) | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JPH0794751A (en) * | 1993-09-16 | 1995-04-07 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of fabrication thereof |
| JP2012119423A (en) * | 2010-11-30 | 2012-06-21 | Toray Ind Inc | Gate insulating material, gate insulating film, and field effect transistor |
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