JPH01148890U - - Google Patents
Info
- Publication number
- JPH01148890U JPH01148890U JP4651788U JP4651788U JPH01148890U JP H01148890 U JPH01148890 U JP H01148890U JP 4651788 U JP4651788 U JP 4651788U JP 4651788 U JP4651788 U JP 4651788U JP H01148890 U JPH01148890 U JP H01148890U
- Authority
- JP
- Japan
- Prior art keywords
- control data
- circuit
- integrated circuit
- analog electronic
- volatile memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 4
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 238000001514 detection method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案のアナログ電子時計用ＩＣ及び
アナログ電子時計の一実施例を示すブロツク図。
第２図は第１図の制御信号形成回路３から出力さ
れる信号のタイミングチヤート。第３図は第１図
のリセツト信号形成回路４、モードカウンター５
、及びデコーダー６の具体的構成例を示す回路図
。第４図は第１図の入出力制御回路７の具体的構
成例を示す回路図。第５図は第１図のＥＰＲＯＭ
８及びデータセレクター９の具体的構成例を示す
回路図。第６図は第５図のライトイネーブルブロ
ツク８０１〜８０４の具体的構成例を示す回路図
。第７図は第５図のＲＯＭブロツク８１０〜８４
９の具体的構成例を示す回路図。第８図は第１図
のモータ駆動信号形成回路１２から出力される信
号のタイミングチヤート。第９図は第１図のラツ
チ回路１１及びモータ駆動信号形成回路１２の具
体的構成例の一部分を示す回路図。第１０図は第
１図の出力制御回路１３の具体的構成例を示す回
路図。第１１図は第１図の出力デコーダー１４か
ら出力される信号のタイミングチヤート。第１２
図は第１図のモータドライバー及び検出回路の具
体的構成例を示す回路図。
１００……アナログ電子時計用ＩＣ、１……発
振回路、２……分周回路、２０……1/1024分周回
路、２１……1/32分周回路、２２……1/10分周回
路、２３……1/32分周回路、３……制御信号形成
回路、４……リセツト信号形成回路、５……モー
ドカウンター、６……デコーダー、７……入出力
制御回路、８……ＥＰＲＯＭ、９……ＥＰＲＯＭ
データ用カウンター、１０……データセレクター
、１１……ラツチ回路、１２……モータ駆動信号
形成回路、１３……出力制御回路、１４……出力
デコーダー、１５……モータドライバー及び検出
回路、１６……感温発振回路、１７……温度補償
回路、１８……論理緩急回路、１９……電池、２
４……音叉型水晶振動子、２５……リセツトスイ
ツチ、２６……表示機構。
FIG. 1 is a block diagram showing an embodiment of an IC for an analog electronic watch and an analog electronic watch of the present invention.
FIG. 2 is a timing chart of signals output from the control signal forming circuit 3 of FIG. 1. Figure 3 shows the reset signal forming circuit 4 and mode counter 5 in Figure 1.
, and a circuit diagram showing a specific configuration example of the decoder 6. FIG. FIG. 4 is a circuit diagram showing a specific example of the configuration of the input/output control circuit 7 shown in FIG. 1. Figure 5 is the EPROM of Figure 1.
8 is a circuit diagram showing a specific configuration example of the data selector 8 and the data selector 9. FIG. FIG. 6 is a circuit diagram showing a specific example of the structure of write enable blocks 801 to 804 in FIG. 5. Figure 7 shows the ROM blocks 810 to 84 in Figure 5.
9 is a circuit diagram showing a specific configuration example of No. 9; FIG. FIG. 8 is a timing chart of signals output from the motor drive signal forming circuit 12 of FIG. 1. FIG. 9 is a circuit diagram showing a part of a specific example of the structure of the latch circuit 11 and motor drive signal forming circuit 12 shown in FIG. 1. FIG. 10 is a circuit diagram showing a specific example of the configuration of the output control circuit 13 shown in FIG. 1. FIG. 11 is a timing chart of signals output from the output decoder 14 of FIG. 1. 12th
FIG. 2 is a circuit diagram showing a specific configuration example of the motor driver and detection circuit shown in FIG. 1. 100... IC for analog electronic clock, 1... Oscillator circuit, 2... Frequency dividing circuit, 20... 1/1024 frequency dividing circuit, 21... 1/32 frequency dividing circuit, 22... 1/10 frequency dividing circuit Circuit, 23...1/32 frequency divider circuit, 3... Control signal forming circuit, 4... Reset signal forming circuit, 5... Mode counter, 6... Decoder, 7... Input/output control circuit, 8... EPROM, 9...EPROM
Data counter, 10... Data selector, 11... Latch circuit, 12... Motor drive signal forming circuit, 13... Output control circuit, 14... Output decoder, 15... Motor driver and detection circuit, 16... Temperature-sensitive oscillation circuit, 17...Temperature compensation circuit, 18...Logic slowing/slowing circuit, 19...Battery, 2
4... Tuning fork type crystal oscillator, 25... Reset switch, 26... Display mechanism.
Claims (1)
揮発性メモリーと、前記半導体不揮発性メモリー
から制御データＫ１が出力されたときに制御デー
タＫ１を取り込み保持する制御データ保持手段と
、前記制御データ保持手段が保持する制御データ
Ｋ１の値によつてモータ駆動信号の周期やパルス
幅等を選択できるように構成したモータ駆動信号
形成回路とを有することを特徴とするアナログ電
子時計用集積回路。 (2) 制御データＫ１を記憶する半導体不揮発性
メモリーが他の機能を制御するための制御データ
Ｋ２を記憶する半導体不揮発性メモリーと並列に
配置され出力データ線を共用する様に構成された
ことを特徴とする第１項記載のアナログ電子時計
用集積回路。 (3) 制御データＫ２が歩度を制御するためのデ
ータであることを特徴とする第２項記載のアナロ
グ電子時計用集積回路。 (4) 制御データＫ１及び制御データＫ２の書き
込みを別モードで行なうためのモードカウンター
及びデコーダーを有し、書き込みに必要な端子を
それぞれのモードで共用するように構成したこと
を特徴とする第１項又は第２項又は第３項記載の
アナログ電子時計用集積回路。 (5) 第１項又は第２項又は第３項又は第４項記
載のアナログ電子時計用集積回路を搭載したこと
を特徴とするアナログ電子時計。[Claims for Utility Model Registration] (1) A semiconductor non-volatile memory that stores and outputs control data K1, and a control data holder that captures and holds the control data K1 when the control data K1 is output from the semiconductor non-volatile memory. and a motor drive signal forming circuit configured such that the period, pulse width, etc. of the motor drive signal can be selected according to the value of control data K1 held by the control data holding means. Integrated circuit for watches. (2) The semiconductor non-volatile memory that stores control data K1 is arranged in parallel with the semiconductor non-volatile memory that stores control data K2 for controlling other functions, and is configured to share the output data line. An integrated circuit for an analog electronic watch according to item 1, characterized in that: (3) The integrated circuit for an analog electronic timepiece according to item 2, wherein the control data K2 is data for controlling the rate. (4) A first device characterized in that it has a mode counter and a decoder for writing the control data K1 and the control data K2 in different modes, and is configured so that the terminals necessary for writing are shared in each mode. The integrated circuit for an analog electronic watch according to item 1 or 2 or 3. (5) An analog electronic timepiece characterized by being equipped with an integrated circuit for an analog electronic timepiece according to paragraph 1 or 2 or 3 or 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988046517U JPH0752632Y2 (en) | 1988-04-06 | 1988-04-06 | Electronic clock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988046517U JPH0752632Y2 (en) | 1988-04-06 | 1988-04-06 | Electronic clock circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01148890U true JPH01148890U (en) | 1989-10-16 |
| JPH0752632Y2 JPH0752632Y2 (en) | 1995-11-29 |
Family
ID=31272786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988046517U Expired - Lifetime JPH0752632Y2 (en) | 1988-04-06 | 1988-04-06 | Electronic clock circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0752632Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105490598A (en) * | 2014-10-06 | 2016-04-13 | Em微电子-马林有限公司 | Motor driver device with a horological motor driver and an associated configuration circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6017390A (en) * | 1983-07-11 | 1985-01-29 | Casio Comput Co Ltd | Electronic clock |
| JPS60202378A (en) * | 1984-03-27 | 1985-10-12 | Seiko Epson Corp | Electronic timepiece |
| JPS61127489U (en) * | 1985-01-29 | 1986-08-09 | ||
| JPS6329291A (en) * | 1986-07-10 | 1988-02-06 | イ−エム・マイクロエレクトロニツク−マリン・エスア− | Programming device for electric type rewritable nonvolatile memory for clock |
-
1988
- 1988-04-06 JP JP1988046517U patent/JPH0752632Y2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6017390A (en) * | 1983-07-11 | 1985-01-29 | Casio Comput Co Ltd | Electronic clock |
| JPS60202378A (en) * | 1984-03-27 | 1985-10-12 | Seiko Epson Corp | Electronic timepiece |
| JPS61127489U (en) * | 1985-01-29 | 1986-08-09 | ||
| JPS6329291A (en) * | 1986-07-10 | 1988-02-06 | イ−エム・マイクロエレクトロニツク−マリン・エスア− | Programming device for electric type rewritable nonvolatile memory for clock |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105490598A (en) * | 2014-10-06 | 2016-04-13 | Em微电子-马林有限公司 | Motor driver device with a horological motor driver and an associated configuration circuit |
| JP2016075681A (en) * | 2014-10-06 | 2016-05-12 | イーエム・ミクロエレクトロニク−マリン・エス アー | Motor driver device having timepiece motor driver and related component circuit |
| CN105490598B (en) * | 2014-10-06 | 2018-04-13 | Em微电子-马林有限公司 | Motor driving apparatus with clock-type motor driver and relevant configuration circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0752632Y2 (en) | 1995-11-29 |
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