JPH01147917A - Logic circuit - Google Patents

Abstract

PURPOSE:To simplify the switching signal and to eliminate any transfer gate by using a single switching signal so as to switch a NAND logic and a NOR logic directly. CONSTITUTION:With a switching signal, phi at an L level, a PMOS 34 is turned on and an NMOS 36 is turned off. As a result, PMOS 33-1-33-n connected in parallel, PMOS 31-1-31-n connected in series and NMOS 32-1-32-n connected in series act like an n-input NAND circuit. On the other hand, with the switching signal, phi at an H level, the PMOS 34 is turned off and the NMOS 36 is turned on. As a result, the NMOS35-1-35-n connected in parallel, NMOS32-1-32-n connected in series and PMOS31-1-31-n connected in series act like an n-input NOR circuit. Thus, no complementary switching signal alike a conventional circuit is required for logic switching and no transfer gate is used, the switching is applied at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a NAND/NOR switchable logic circuit used in a self-test circuit in a semiconductor memory circuit or the like.

(Prior Art) Conventionally, in semiconductor memory circuits such as memory that can be read and written at any time (hereinafter referred to as RAM), a self-test circuit has been provided to test whether there are any defective bits in a large number of memory cells. It may happen. This self-test circuit is composed of a logic circuit as shown in FIG. 2, for example.

The logic circuit in Figure 2 consists of multiple (n>input Nant gates)
(hereinafter referred to as NAND gate) 1 and NOAH gate (hereinafter referred to as
A transfer gate 10 is connected to the output sides of the NAND gate 1 and the NOR gate 2 for switching the outputs of these two gates. The transfer gate 10 includes two P-channel MOS transistors (hereinafter referred to as PMO3) 11 and 12 and two N-channel MOS transistors (hereinafter referred to as PMO3).
NMO8) 13.14, and their PMO8
11 and NMO313 are connected in parallel, and PMO
312 and NMO 314 are connected in parallel. One PMO311 and NMO313 and the other PMO812 and NMO814 receive a switching signal φ and an inverter 2.
The on/off operation is performed using the reverse phase signal T which is inverted at 0.

In the above configuration, n input signals MS! 1 to 3in are logically ANDed by NAND gate 1 and then inverted, and also logically summed by NOR gate 2 and then inverted. Here, when the switching signal φ is logic "1", the PMO
311 is turned off, NMO314 is turned on, and NMO313 is turned off by the logic "0'' of the negative phase signal T.
Since the PMO 312 and the PMO 312 are turned on, the output of the NOR gate 2 is output in the form of an output signal SO through the PMO 312 and the NMO 314 that are in the on state. When the switching signal φ switches to “0”, the output of NAND gate 1 turns on PM
It is output through O311 and NMO813 in the form of output signal So.

Therefore, data (S
i 1 to 5 inches) and set the switching signal φ to 1" or "Qlf according to the expected value, and transfer the transfer gate 10
and the data (S i 1 to 3 inches) are all 1
” or “091” is determined by the NAND gate 1 or NOR gate 2, and the result of the determination of match or mismatch is sent to the transfer gate 10 as “1” or “0.”
Defective bits in a large number of memory cells can be detected by outputting the data in the form of data (SO).

(Problems to be Solved by the Invention) However, the logic circuit with the above configuration requires complementary switching signals φ and ■ to switch between NAND logic and NOR logic, which increases the number of circuit elements and increases the number of switching signals. A delay time occurs when the signal φ is inverted by the inverter 20 to generate the opposite phase signal T. Roughly, their complementary switching signals φ.

Since the transfer gate 10 is switched using T, there is a problem that the output is delayed due to the delay time caused by the inverter 20 and the switching time of the transfer gate 10 itself.

The present invention provides a logic circuit that solves the problems of the prior art, such as the need for complementary switching signals and the delay in switching due to transfer gates.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a logic circuit that can switch between NAND logic and NOR logic. n pieces connected in series between (however, n=1.2..., n
) are connected to each control terminal, respectively.
n second transistors connected in series between the output terminal and a second power supply potential and having the n inputs connected to respective control terminals;
n third transistors connected in parallel between the power supply potential of and the first connection point and having the n inputs connected to each control terminal, the first connection point and the output terminal; and a fourth transistor connected in parallel between a second connection point and the second power supply potential and having the n inputs connected to each control terminal. and a sixth transistor connected between the output terminal and the second connection point and having the switching signal connected to the control electrode. It is.

(Function) According to the present invention, since the logic circuit is configured as described above, the switching signal "0" or "1" causes the first.
Second. the third and fourth transistors, or the first . Second. One of the fifth and sixth transistors is NA
The ND circuit is switched so that the other operates as a NOR circuit. This eliminates the need for an anti-phase signal with respect to the switching signal, and also makes it possible to omit the conventional transfer gate. Therefore, the switching signal can be simplified and the switching operation can be restricted. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a logic circuit showing an embodiment of the present invention.

This logic circuit is a switching circuit between NAND logic and NOR logic used in self-test circuits of semiconductor memory circuits, etc., as in the past, and is a switching circuit between the first power supply potential VCC and the output signal @
n first transistors, for example, PMO331-1 to 31-n, are connected in series between the output terminal 30 for So, and roughly connect the output terminal 30 and the second power supply potential (for example,
n second transistors, for example, NMOs 331-1 to 31-n, are connected in series between the ground potential (ground potential) VSS. Each PMO331-1 to 31-n and NMO33
n input signals S11 to 3in are input to the gates serving as control electrodes of 2-1 to 32-n, respectively.

Between the first power supply potential Vcc and the first connection point N31, there are n third transistors, for example, PMO333-1.
~33-n are connected in parallel, and roughly between the first connection point N31 and the output terminal 30, a fourth transistor,
For example, a PMO 334 is connected. Between the second power supply potential yss and the second connection point N32, n fifth transistors, for example, NMO835-1 to 35-n, are connected in parallel, and further between the second connection point N32 and A sixth transistor, for example NMO3, is connected between the output terminal 30 and the output terminal 30.
36 are connected. Each PMO333-1 to 33-n
And n input signals St1 to 3in are input to the gates of NMO335-1 to 35-n, respectively, and further P
The gates of MO334 and NMO336 are configured to receive a switching signal φ.

FIG. 3 is a timing diagram of the signals shown in FIG. 1, and the operation of FIG. 1 will be explained with reference to this diagram.

First, when the switching signal φ is °“O” (=L level),
PMO 834 is turned on and NMO 336 is turned off. At this time, if the input signals Si1 to Sin are all "1", the parallel-connected PMOs 333-1 to 33-n and the series-connected PMOs 331-1 to 31-n are all turned off, and the series-connected NMOs 333-1 to 33-n are all turned off. -1 to 32-n are all turned on, and the output terminal 30 has the second power supply potential VSS (=”
An output signal So of "O") is output. Also, if one or more of the input signals Sil to 3in is "O",
PMO3 corresponding to the input signal "0" among the PMOs 333-1 to 33-n connected in parallel is turned on, and PMO3 corresponding to the input signal "0" among the NMOs 332-1 to 32-n connected in series is turned on. NMO3 turns off and output terminal 30
An output signal So of 1'' (=H level) is outputted from.

That is, in the circuit of FIG. 1, the switching signal φ is (d
When Oee f), it becomes an n-input NAND circuit (NAND mode).

Next, when the switching signal φ is 1'', the PMO 334 is turned off and the NMO 836 is turned on.

At this time, if the input signals Si1 to Sin are all "0", the parallel-connected NMOs 835-1 to 35-nl and the series-connected NMOs 332-1 to 32-n are all turned off, and the series-connected PMOs 831-1 31-n are all turned on, the output terminal 30 has the first power supply potential VCC.
An output signal SO of (='“H-Pa)” is output. Also, if one or more of the input signals Si1 to Sin is “1”, one of the parallel-connected NMOs 335-1 to 35-n “
NMO3 corresponding to the 1″ input signal is turned on, and
Since the PMO 3 corresponding to the 1'' input signal among the series-connected PMOs 331-1 to 31-n is turned off, an output signal SO of "0" is output to the output terminal SO. In other words,
The circuit shown in FIG. 1 has n
It becomes an input NOR circuit (NOR mode).

In this embodiment, when the switching signal φ is “0”, the
As an ANO circuit, each operates as an n-input NOR circuit when the switching signal φ is "1", so it does not require complementary switching signals like conventional ones for logic switching, and does not use transfer gates. Therefore, the number of circuit elements is small, and high-speed switching operation with almost no delay time is possible.

FIG. 4 is a circuit diagram of a logic circuit showing another embodiment of the present invention, and the same elements as those in FIG. 1 are given the same reference numerals.

This logic circuit consists of n PMs connected in series in FIG.
One PMO3 which uses any one of the input signals Si1 to 3in as a gate input for O831-1 to 31-n.
31, and n of the series connection in FIG.
input signals 3i1 to 3i1 to
In this case, one NMO 332 is substituted with one of the 3 inches as a gate input. This PMO33
1 and NMO 332 function as load transistors. The circuit as a whole operates in the same way as the circuit shown in FIG. Therefore, in addition to having substantially the same advantages as the circuit shown in FIG. 1, the number of circuit elements is reduced.

Note that the present invention is not limited to the illustrated embodiment; for example, PM
O331-1 to 31-n, 31.33-1 to 33-n,
Replace 34 with NMO3, along with NMO832-1
~32-n, 32.35-1~35-n, 36 as PMO
3 or their PMO3 and NM
Use O3 with other field effect transistors, PNP type, NPN
It is also possible to configure it with a type of bipolar transistor. Further, the logic circuit of the above embodiment can be applied to circuits other than memory self-test circuits.

(Effects of the Invention) As described in detail above, according to the present invention, the configuration is such that the switching signal is used to directly switch between NAND logic and NOR logic, so the switching signal can be simplified, and the transfer gate can be omitted, thereby reducing the number of circuit elements and enabling high-speed switching operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a logic circuit showing an embodiment of the present invention, and FIG.
3 is a circuit diagram of a conventional logic circuit, FIG. 3 is a timing diagram of FIG. 1, and FIG. 4 is a circuit diagram of a logic circuit showing another embodiment of the present invention. 30...Output terminal, 31-1 to 31-n, 31
゜33-1 to 33-n, 34-------PMO3,3
2-1 to 32-n, 32, 35-1 to 35-n, 36.
...NMO3, N31. N32・・・・・・1st
．． Second connection point, Si1-3in...input signal, SO...output signal, vcc, vss...
...First. Second power supply potential, φ...Switching signal. Applicant's agent Kakimoto Kyo Seikai and output f4+ N31. N32: 1st. Second connection point 5jI-5Lr
L: Irukaijima SO: Output signal Vcc, Vss: 1st. 2nd (7) Power supply potential cp: Logic circuit of the present invention Figure 1 Figure 2

Claims (1)

[Claims] 1. Connected in series between the first power supply potential and the output terminal, and n inputs (n = 1, 2, ..., n) connected to each control terminal, respectively. n first transistors connected in series between the output terminal and a second power supply potential and having the n inputs connected to each control terminal, respectively; , n third transistors connected in parallel between the first power supply potential and the first connection point and having the n inputs connected to each control terminal, and the first connection point. and the output terminal, the switching signal being connected to the control electrode; and the n inputs being connected in parallel between the second connection point and the second power supply potential. n fifth transistors each connected to each control terminal, the output terminal and the second
and a sixth transistor connected between the connection point and the switching signal connected to the control electrode. 2. The first, third and fourth transistors are P-channel MOS transistors, and the second, fifth and sixth transistors are N-channel MOS transistors, respectively. The logic circuit described.