JPH01147827A - Manufacture of multilayer semiconductor substrate - Google Patents

Manufacture of multilayer semiconductor substrate

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Publication number
JPH01147827A
JPH01147827A JP30589187A JP30589187A JPH01147827A JP H01147827 A JPH01147827 A JP H01147827A JP 30589187 A JP30589187 A JP 30589187A JP 30589187 A JP30589187 A JP 30589187A JP H01147827 A JPH01147827 A JP H01147827A
Authority
JP
Japan
Prior art keywords
semiconductor layer
single crystal
silicon
thickness
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30589187A
Other languages
Japanese (ja)
Other versions
JP2526380B2 (en
Inventor
Kazuyuki Sugahara
和之 須賀原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62305891A priority Critical patent/JP2526380B2/en
Publication of JPH01147827A publication Critical patent/JPH01147827A/en
Application granted granted Critical
Publication of JP2526380B2 publication Critical patent/JP2526380B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To form a single crystal layer having few irregularities onto an insulator by bringing the thickness of a semiconductor layer melted and recrystallized by laser beams to 1500Angstrom or less. CONSTITUTION:An SiO2 film 2 in thickness of 1mum is shaped onto a single crystal Si substrate 1, and poly Si 3 in thickness of 1500Angstrom is deposited onto the film 2 through a CVD method. Poly Si 3 is irradiated with argon laser beams 4 diaphragmed to a diameter of 100mum and the laser beams 4 are scanned in 25cm/s. Since the greater parts of laser beams 4 reach up to the Si substrate 1 and the substrate 1 is heated, temperature distribution in molten Si 5 is made gentler than conventional examples (poly Si in thickness of 6000Angstrom ), and the irregularities of the surface of a single crystal Si film 6 after recrystallization are inhibited to 150Angstrom or less.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は多層半導体基板の製造方法に関し、特に絶縁
体上に半導体単結晶膜を形成しこれを基板としてトラン
ジスタ等の回路素子を形成する方法に関するものである
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer semiconductor substrate, and particularly to a method for forming a semiconductor single crystal film on an insulator and using this as a substrate to form circuit elements such as transistors. It is related to.

[従来の技術] 従来半導体装置の高速化・高密度化のため回路素子を誘
電体で分離した浮遊容量の少ない半導体集積回路を製造
する試み、また回路素子を立体的に積層するいわゆる3
次元回路素子を製造する試みがなされており、その一方
法として絶縁体上に半導体層を形成しその半導体結晶中
に回路素子を構成する方法がある。この半導体結晶層を
形成する方法として絶縁体上に多結晶または非晶質の半
導体層を堆積し、その表面にレーザ光または電子線のエ
ネルギ線を照射することによって表面層のみを加熱し、
単結晶の半導体層を形成する方法がある。
[Prior art] Conventionally, in order to increase the speed and density of semiconductor devices, attempts have been made to manufacture semiconductor integrated circuits with low stray capacitance in which circuit elements are separated by dielectrics, and so-called 3-dimensional integrated circuits in which circuit elements are stacked three-dimensionally.
Attempts have been made to manufacture dimensional circuit elements, and one method is to form a semiconductor layer on an insulator and construct the circuit element in the semiconductor crystal. As a method for forming this semiconductor crystal layer, a polycrystalline or amorphous semiconductor layer is deposited on an insulator, and only the surface layer is heated by irradiating the surface with energy beams such as laser light or electron beams.
There is a method of forming a single crystal semiconductor layer.

第3A図〜第3E図はこの従来の製造方法についての概
略工程断面図である。
3A to 3E are schematic process cross-sectional views of this conventional manufacturing method.

以下、図を参照してこの製造方法について説明する。This manufacturing method will be described below with reference to the drawings.

まず、単結晶のシリコン基板1の主面上に厚さ1μmの
二酸化シリコン膜よりなる酸化膜2が形成され、さらに
酸化膜2上に化学気相成長(CVD)法で多結晶シリコ
ン10を厚さ6000Aで堆積させる(第3A図参照)
。次に直径100μmに絞ったアルゴンレーザ光4を走
査速度25cm/sで走査しながら多結晶シリコン10
に照射する。するとレーザ光4の照射された領域の多結
晶シリコン10は溶融されて溶融シリコン11になり、
それが固化再結晶化することによってIll結晶化シリ
コン12が形成される(第3B図参−照)。
First, an oxide film 2 made of a silicon dioxide film with a thickness of 1 μm is formed on the main surface of a single-crystal silicon substrate 1, and then a thick polycrystalline silicon 10 is further deposited on the oxide film 2 by chemical vapor deposition (CVD). Deposit at 6000A (see Figure 3A)
. Next, while scanning the argon laser beam 4 focused to a diameter of 100 μm at a scanning speed of 25 cm/s, the polycrystalline silicon 10
irradiate. Then, the polycrystalline silicon 10 in the area irradiated with the laser beam 4 is melted and becomes molten silicon 11.
By solidifying and recrystallizing it, Ill crystallized silicon 12 is formed (see FIG. 3B).

この単結晶化の機構については特開昭61−04846
8に詳細が述べられている。レーザ光4の1回の走査が
終了するとレーザ光4を走査方向に垂直に30μm移動
して次の走査を行なう。このような要領でウェハ全面に
レーザ光4の走査が完了すると、多結晶シリコン10は
全面にわたって単結晶化シリコン12になる(第3C図
参照)。
Regarding the mechanism of this single crystallization, please refer to JP-A No. 61-04846.
8 provides details. When one scan of the laser beam 4 is completed, the laser beam 4 is moved 30 μm perpendicularly to the scanning direction to perform the next scan. When the scanning of the laser beam 4 over the entire surface of the wafer is completed in this manner, the entire surface of the polycrystalline silicon 10 becomes monocrystalline silicon 12 (see FIG. 3C).

この単結晶化シリコン12上にMOS)ランジスタ等を
通常のプロセスに従って作成するわけであるが、接合容
量接合面積を減少させ素子の高性能化を図るためトラン
ジスタを作成する単結晶化シリコン12の膜厚を注入さ
れた不純物の拡散によって決まる不純物接合深さ(約1
500A−0゜15μm)より薄くする必要がある。し
たがって第3C図の状態のウェハを1000℃程度の酸
化雰囲気中に長時間さらして、t11結晶化シリコン1
2の表面を酸化する。すると単結晶化シリコン12は表
面部は酸化されるので厚さ1500Aの単結晶化シリコ
ン6となり、その上に厚さ9000Aの酸化膜13が形
成される(第3D図参照)。
A MOS (MOS) transistor, etc. is fabricated on this single crystal silicon 12 according to a normal process, and in order to reduce the junction capacitance junction area and improve the performance of the device, a film of the single crystal silicon 12 is used to fabricate a transistor. The impurity junction depth is determined by the diffusion of the implanted impurity (approximately 1
It is necessary to make it thinner than 500A-0°15 μm). Therefore, by exposing the wafer in the state shown in FIG. 3C to an oxidizing atmosphere at about 1000°C for a long time,
Oxidize the surface of 2. Then, the surface portion of the single crystal silicon 12 is oxidized to become a single crystal silicon 6 with a thickness of 1500 Å, and an oxide film 13 with a thickness of 9000 Å is formed thereon (see FIG. 3D).

最後に、最上層の酸化膜13をエツチングにより除去し
て厚さ1500Aの単結晶化シリコン6を露出させ(第
3E図参照)、この単結晶化シリコン6に通常のトラン
ジスタ製造プロセス等によって素子を形成する。
Finally, the top layer oxide film 13 is removed by etching to expose the single crystal silicon 6 with a thickness of 1500 Å (see Figure 3E), and elements are formed on this single crystal silicon 6 using a normal transistor manufacturing process. Form.

[発明が解決しようとする問題点] 従来の半導体装置の製造方法においては、厚さ6000
Aの多結晶シリコンを溶融再結晶化しているため、溶融
シリコンの移動に起因する再結晶化シリコンの表面凹凸
がその段差で60OAの大きさで発生するという問題点
があった。この表面凹凸発生の機構を第4図〜第6図に
従って説明する。
[Problems to be Solved by the Invention] In the conventional method of manufacturing a semiconductor device, a thickness of 6000 mm
Since the polycrystalline silicon of A was melted and recrystallized, there was a problem in that the surface unevenness of the recrystallized silicon caused by the movement of the molten silicon occurred at a level difference of 60 OA. The mechanism of this surface unevenness generation will be explained with reference to FIGS. 4 to 6.

第4図はレーザ光照射時のウェハを示す平面図であり、
第5図は第4図のv−■断面図、第6図は第4図のVl
−Vl断面図である。
FIG. 4 is a plan view showing the wafer during laser beam irradiation;
Figure 5 is a sectional view taken along line v-■ in Figure 4, and Figure 6 is a cross-sectional view of Vl in Figure 4.
-Vl sectional view.

第4図、第5図に示すようにレーザ光4の照射された領
域の多結晶シリコン10は溶融シリコン11になるが、
■溶融シリコン11の密度は固体のシリコンの密度より
大きい、■レーザ光4の強度分布がビーム中心で高くビ
ーム周辺で低い、いわゆるガウス型分布のため溶融シリ
コン11の中心の温度は周辺より高い。すなわち■の理
由により溶融シリコン11の体積は小さくなり、かつ■
の理由に基づく表面張力により溶融シリコン11の中央
部のシリコンが周辺部へ移動する。したがって溶融シリ
コン11は周辺から固化するため、再結晶化のこの単結
晶化シリコン12は第6図に示すような凹凸が発生して
しまう。この凹凸の段差の大きさ(図中aで示す)は多
結晶シリコン10の厚さに比例して600人程度となる
。このように1回のレーザ光の走査によりて600Aの
凹凸がビーム径(溶融幅)100μmの領域に発生する
。実際はレーザ光を30μmずつ移動させて走査させて
いるので、30μmを周期にして600への凹凸が単結
晶化シリコン12上に形成される。この凹凸は後工程の
酸化後にもそのままの形状で残留するため、結局第3E
図での単結晶化シリコン6は1200Aから1800A
までその膜厚がばらつき部分的に不純物接合深さ(15
00A)より厚い領域が発生して単結晶化シリコン6内
に形成された素子の特性が劣化する。
As shown in FIGS. 4 and 5, the polycrystalline silicon 10 in the area irradiated with the laser beam 4 becomes molten silicon 11.
(2) The density of the molten silicon 11 is higher than that of solid silicon; (2) The intensity distribution of the laser beam 4 is high at the beam center and low at the periphery of the beam, a so-called Gaussian distribution; therefore, the temperature at the center of the molten silicon 11 is higher than the surrounding area. In other words, the volume of molten silicon 11 becomes smaller due to the reason (■), and ()
Silicon in the center of the molten silicon 11 moves to the periphery due to surface tension due to this reason. Therefore, since the molten silicon 11 is solidified from the periphery, the recrystallized single crystal silicon 12 has irregularities as shown in FIG. The size of the step (indicated by a in the figure) of this unevenness is approximately 600 in proportion to the thickness of the polycrystalline silicon 10. In this way, one scan of the laser beam generates irregularities of 600 A in an area with a beam diameter (melting width) of 100 μm. In reality, the laser beam is moved and scanned in steps of 30 μm, so that 600 concavities and convexities are formed on the single crystal silicon 12 with a period of 30 μm. This unevenness remains in the same shape even after oxidation in the subsequent process, so the 3rd E
Single crystal silicon 6 in the figure is 1200A to 1800A
The film thickness varies up to the impurity junction depth (15
00A) A thicker region is generated and the characteristics of the device formed in the single crystal silicon 6 are deteriorated.

この発明は上記のような問題点を解決するためになされ
たもので、絶縁体上に凹凸の少ない単結晶半導体層を得
る多層半導体基板の製造方法を提供することを目的とす
る。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a multilayer semiconductor substrate that obtains a single crystal semiconductor layer with less unevenness on an insulator.

[問題点を解決するための手段] この発明に係る半導体装置の製造方法は、エネルギ線の
照射等によって溶融再結晶化する非単結晶半導体層の厚
さを1500A以下にしたものである。
[Means for Solving the Problems] In the method for manufacturing a semiconductor device according to the present invention, the thickness of the non-single crystal semiconductor layer melted and recrystallized by irradiation with energy beams or the like is set to 1500 Å or less.

[作用コ この発明における1500A以下の非Ill結晶半導体
層はエネルギ線の照射によって溶融再結晶化する際、表
面の凹凸の発生を低減する。
[Function] The non-Ill crystal semiconductor layer of 1500A or less in this invention reduces the occurrence of surface irregularities when melted and recrystallized by irradiation with energy beams.

[実施例] 第1A図〜第1C図はこの発明の一実施例を示す概略工
程断面図である。
[Example] Figures 1A to 1C are schematic process cross-sectional views showing an example of the present invention.

以下、図を参照してこの発明の製造方法について説明す
る。
Hereinafter, the manufacturing method of the present invention will be explained with reference to the drawings.

まず、単結晶のシリコン基板1の主面上に厚さ1μmの
二酸化シリコン膜よりなる酸化膜2が形成され、さらに
酸化膜2上にCVD法で多結晶シリコン3を厚さ150
OAで堆積させる(第1A図参照)。
First, an oxide film 2 made of a silicon dioxide film with a thickness of 1 μm is formed on the main surface of a single-crystal silicon substrate 1, and then polycrystalline silicon 3 is deposited on the oxide film 2 to a thickness of 150 μm using the CVD method.
Deposit with OA (see Figure 1A).

次に、直径100μmに絞ったアルゴンレーザ光4を走
査速度25cm/sで走査しながら多結晶シリコン3に
照射する。すると照射された多結晶シリコン3は溶融さ
れて溶融シリコン5となり、それが同化再結晶化するこ
とによって単結晶化シリコン6が形成される(第1B図
参照)。
Next, polycrystalline silicon 3 is irradiated with argon laser light 4 focused to a diameter of 100 μm while scanning at a scanning speed of 25 cm/s. Then, the irradiated polycrystalline silicon 3 is melted and becomes molten silicon 5, which is assimilated and recrystallized to form single crystal silicon 6 (see FIG. 1B).

このレーザ光照射、再結晶化(単結晶化)の機構は従来
の方法と同一であるが、レーザ光のパワーは第1A図の
構造に適した量に調整する必要がある。ウェハ全面への
レーザ光の照射が完了すると多結晶シリコン3は全面単
結晶化シリコン6になる(第1C図参照)。
The mechanism of this laser beam irradiation and recrystallization (single crystallization) is the same as the conventional method, but the power of the laser beam needs to be adjusted to an amount suitable for the structure shown in FIG. 1A. When the irradiation of the laser beam to the entire surface of the wafer is completed, the polycrystalline silicon 3 becomes the entire surface of single crystal silicon 6 (see FIG. 1C).

さて、この場合溶融シリコンの形状その移動および単結
晶化シリコンの形状は従来の方法と同様の機構によって
第4図〜第6図で説明したものと基本的には同様の形状
になる。しかし、溶融する多結晶シリコン3の膜厚が薄
いため、レーザ光4は多結晶シリコン3にすべて吸収さ
れず(アルゴンレーザ光のシリコンの侵入量は0.7μ
m)、大部分は多結晶シリコン3を通過してシリコン基
板1を加熱する。シリコン基板1の熱は速やかに下方に
拡散するため溶融シリコン5内の温度分布は従来の例に
比べて緩かになる。その結果溶融シリコン5の周辺部の
移動量は、はぼ多結晶シリコン3の膜厚に比例する(膜
厚1000〜10000Aの範囲内で)ことから再結晶
化後の表面凹凸の段差は150A以内に抑えられ、後の
デバイスを作成する際に問題のないレベルになる。
In this case, the movement of the shape of the molten silicon and the shape of the single crystal silicon basically become the same shape as explained in FIGS. 4 to 6 by a mechanism similar to that of the conventional method. However, since the film thickness of the melted polycrystalline silicon 3 is thin, the laser beam 4 is not completely absorbed by the polycrystalline silicon 3 (the amount of argon laser beam that penetrates into the silicon is 0.7μ).
m) Most of the heat passes through the polycrystalline silicon 3 and heats the silicon substrate 1. Since the heat of the silicon substrate 1 quickly diffuses downward, the temperature distribution within the molten silicon 5 becomes gentler than in the conventional example. As a result, the amount of movement of the periphery of the molten silicon 5 is approximately proportional to the film thickness of the polycrystalline silicon 3 (within a film thickness range of 1000 to 10000 A), so the step difference in the surface unevenness after recrystallization is within 150 A. is suppressed to a level that will not cause problems when creating later devices.

なお、上記実施例ではエネルギ線としてレーザ光を用い
たが電子線を使用しても同様の効果が得られる。
In the above embodiment, a laser beam is used as the energy beam, but the same effect can be obtained even if an electron beam is used.

また、上記実施例では1500Aの多結晶シリコンを単
結晶化後そのまま素子を形成したが素子を形成する前に
単結晶化シリコン表面の酸化を行なって単結晶化シリコ
ンの厚さをさらに薄くしてもよい。
In the above example, the device was formed as it was after single crystallizing polycrystalline silicon of 1500A, but before forming the device, the surface of the single crystal silicon was oxidized to further reduce the thickness of the single crystal silicon. Good too.

また、上記実施例では、レーザ光照射の雰囲気について
特に述べていないが照射時における高熱による単結晶化
シリコンの表面の酸化影響等を避けるためには真空雰囲
気中が望ましい。
Further, although the above embodiments do not specifically mention the atmosphere for laser beam irradiation, a vacuum atmosphere is preferable in order to avoid the effects of oxidation on the surface of single crystal silicon due to high heat during irradiation.

さらに、」二記実施例では、レーザ光を直接多結晶シリ
コンに照射して溶融させたが、溶融は必ずしも直接的で
なくてもよい。
Furthermore, in Example 2, the polycrystalline silicon was directly irradiated with a laser beam to melt it, but the melting does not necessarily have to be done directly.

第2図はこの発明の他の実施例によるレーザ光照射前の
構造断面図である。
FIG. 2 is a cross-sectional view of the structure before laser beam irradiation according to another embodiment of the present invention.

図において第1A図に示した1500A厚さの多結晶シ
リコン3」二にさらに絶縁膜7を形成し、さらにその上
に第2の多結晶シリコン8(この層の厚さは1500A
以下である必要はない)を設けた構造にレーザ光等のエ
ネルギ線を上層の第2の多結晶シリコン8に照射する。
In the figure, an insulating film 7 is further formed on the polycrystalline silicon layer 3'' with a thickness of 1500 Å shown in FIG.
The second polycrystalline silicon 8 in the upper layer is irradiated with an energy beam such as a laser beam.

第2の多結晶シリコン8が溶融するので、その熱でもっ
て間接的1:1500Aの厚さの多結晶シリコン3を溶
融しても同様の効果を奏する。この場合レーザ光等エネ
ルギ線の照射後エツチングにより第2の多結晶シリコン
8および絶縁膜7を除去した後、単結晶化した1500
Aの多結晶シリコン3に素子を形成することになる。
Since the second polycrystalline silicon 8 is melted, the same effect can be obtained even if the polycrystalline silicon 3 having a thickness of 1:1500 Å is indirectly melted using the heat. In this case, the second polycrystalline silicon 8 and the insulating film 7 are removed by etching after irradiation with a laser beam of equal energy.
An element will be formed on the polycrystalline silicon 3 of A.

この実施例によれば多結晶シリコンの上に絶縁膜が形成
された状態で単結晶化が行なわれるので、雰囲気中の影
響を受けることがより少なくなる利点も有する。
According to this embodiment, since single crystallization is performed with an insulating film formed on polycrystalline silicon, it also has the advantage of being less influenced by the atmosphere.

以」二のように非単結晶の半導体層を溶融する方法は熱
エネルギを用いて走査するものであれば何であってもよ
い。
Any method for melting a non-single crystal semiconductor layer as described above may be used as long as it scans using thermal energy.

[発明の効果] 以1−のようにこの発明によれば、溶融単結晶化させる
非lit結晶の半導体層の膜厚を1500A以下に設定
したので、絶縁体上に凹凸の少ないlli結晶半導体層
が得られ、この半導体層に形成される回路素子の高性能
化に大いに寄与する効果がある。
[Effects of the Invention] As described in 1- above, according to the present invention, since the thickness of the non-lit crystal semiconductor layer to be melted into a single crystal is set to 1500A or less, it is possible to form an lli crystal semiconductor layer with less unevenness on the insulator. This has the effect of greatly contributing to improving the performance of circuit elements formed in this semiconductor layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1A図〜第1C図はこの発明の一実施例を示す概略“
1′、程断面図、第2図はこの発明の他の実施例による
レーザ光照射前の構造断面図、第3A図〜第3E図は従
来の製造方法を示す概略工程断面図、第4図は従来のレ
ーザ光照射時のウェハを示す平面図、第5図は第4図の
v−■断面図、第6図は第4図のVl−Vl断面図であ
る。 図において、1はシリコン基板、2は酸化膜、3は多結
晶シリコン、4はレーザ光、5は溶融シリコン、6は単
結晶化シリコン、7は絶縁膜、8は多結晶シリコンであ
る。 なお、各図中同一符号は同一または相当部分を示す。 特許出願人 工業技術院長 飯塚幸三 萬1A図 第1B図 萬IC図 82図 第3A図 萬30図 萬3D図 第3E図 第4図 85図 第6図 手続補正書(自発) イ成ζ年り月+6日
1A to 1C are schematic diagrams showing an embodiment of the present invention.
1', a cross-sectional view of the main body, FIG. 2 is a structural cross-sectional view of another embodiment of the present invention before laser beam irradiation, FIGS. 3A to 3E are schematic process cross-sectional views showing a conventional manufacturing method, and FIG. 5 is a plan view showing a wafer during conventional laser beam irradiation, FIG. 5 is a cross-sectional view taken along the line v--■ in FIG. 4, and FIG. 6 is a cross-sectional view taken along the line Vl--Vl in FIG. 4. In the figure, 1 is a silicon substrate, 2 is an oxide film, 3 is polycrystalline silicon, 4 is a laser beam, 5 is molten silicon, 6 is single crystal silicon, 7 is an insulating film, and 8 is polycrystalline silicon. Note that the same reference numerals in each figure indicate the same or corresponding parts. Patent applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka 1A Figure 1B Figure 10 IC Figure 82 Figure 3A Figure 30 Figure 3D Figure 3E Figure 4 Figure 85 Figure 6 Procedural amendment (self-motivated) month + 6th

Claims (5)

【特許請求の範囲】[Claims] (1)主面を有する半導体基板を準備する工程と、前記
半導体基板の前記主面上に第1の絶縁膜を形成する工程
と、前記第1の絶縁膜上に膜厚が1500Å以下である
非単結晶の第1の半導体層を形成する工程と、前記第1
の半導体層に熱エネルギを走査しながら与えることによ
って、前記第1の半導体層を溶融再結晶化して単結晶化
する工程とを備えた、多層半導体基板の製造方法。
(1) A step of preparing a semiconductor substrate having a main surface, a step of forming a first insulating film on the main surface of the semiconductor substrate, and a film thickness of 1500 Å or less on the first insulating film. a step of forming a non-single crystal first semiconductor layer;
A method for manufacturing a multilayer semiconductor substrate, comprising the step of melting and recrystallizing the first semiconductor layer to form a single crystal by applying thermal energy to the semiconductor layer while scanning.
(2)前記熱エネルギは、エネルギ線の照射によって発
生する、特許請求の範囲第1項記載の多層半導体基板の
製造方法。
(2) The method for manufacturing a multilayer semiconductor substrate according to claim 1, wherein the thermal energy is generated by irradiation with energy beams.
(3)前記エネルギ線は、連続発振のアルゴンレーザ光
である、特許請求の範囲第2項記載の多層半導体基板の
製造方法。
(3) The method for manufacturing a multilayer semiconductor substrate according to claim 2, wherein the energy beam is continuous wave argon laser light.
(4)前紀第1の半導体層を単結晶化する工程は、前記
非単結晶の前記第1の半導体層上に第2の絶縁膜を形成
する工程と、前記第2の絶縁膜上に非単結晶の第2の半
導体層を形成する工程と、前記第2の半導体層に熱エネ
ルギを走査しながら与えることによって前記第2の半導
体層を溶融し、その溶融熱でもって前記第2の絶縁膜を
介して前記第1の半導体層を溶融再結晶化して単結晶化
する工程と、溶融された前記第2の半導体層および前記
第2の絶縁膜を除去する工程とからなる、特許請求の範
囲第1項、第2項または第3項記載の多層半導体基板の
製造方法。
(4) The step of monocrystalizing the first semiconductor layer includes a step of forming a second insulating film on the non-single crystal first semiconductor layer, and a step of forming a second insulating film on the non-single crystal first semiconductor layer. forming a non-single-crystal second semiconductor layer, melting the second semiconductor layer by scanningly applying thermal energy to the second semiconductor layer, and using the melting heat to melt the second semiconductor layer; A patent claim comprising the steps of: melting and recrystallizing the first semiconductor layer to form a single crystal through an insulating film; and removing the melted second semiconductor layer and the second insulating film. A method for manufacturing a multilayer semiconductor substrate according to item 1, item 2, or item 3.
(5)前記第1の半導体層を単結晶化する工程は、真空
雰囲気中において実施される、特許請求の範囲第1項、
第2項または第3項記載の多層半導体基板の製造方法。
(5) The step of single-crystallizing the first semiconductor layer is carried out in a vacuum atmosphere,
The method for manufacturing a multilayer semiconductor substrate according to item 2 or 3.
JP62305891A 1987-12-04 1987-12-04 Method for manufacturing multilayer semiconductor substrate Expired - Lifetime JP2526380B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62305891A JP2526380B2 (en) 1987-12-04 1987-12-04 Method for manufacturing multilayer semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62305891A JP2526380B2 (en) 1987-12-04 1987-12-04 Method for manufacturing multilayer semiconductor substrate

Publications (2)

Publication Number Publication Date
JPH01147827A true JPH01147827A (en) 1989-06-09
JP2526380B2 JP2526380B2 (en) 1996-08-21

Family

ID=17950554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62305891A Expired - Lifetime JP2526380B2 (en) 1987-12-04 1987-12-04 Method for manufacturing multilayer semiconductor substrate

Country Status (1)

Country Link
JP (1) JP2526380B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56111239A (en) * 1980-01-07 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
JPS6254910A (en) * 1985-09-03 1987-03-10 Sharp Corp Manufacturing semiconductor device
JPS6281709A (en) * 1985-10-07 1987-04-15 Agency Of Ind Science & Technol Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56111239A (en) * 1980-01-07 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
JPS6254910A (en) * 1985-09-03 1987-03-10 Sharp Corp Manufacturing semiconductor device
JPS6281709A (en) * 1985-10-07 1987-04-15 Agency Of Ind Science & Technol Manufacture of semiconductor device

Also Published As

Publication number Publication date
JP2526380B2 (en) 1996-08-21

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